VGA display based on FPGA

VGA display based on FPGA VGA (video graphics array), as a standard interface, has already been applications widely. There are a lot of FPGAbased VGA controller designs on which, however, there are still larger defects such as lowresolution display and the Chinese characters display modules occupying large resource. Therefore, we propose the use of VHDL as a logical means to describe the completion of highresolution VGA control module and a resourceconserving string display module design, and provide two main modules of designing ideas and logic diagrams. And experiments show that: while the Chinese characters ensure a highresolution display, the storage resources needed by the display decreased significantly.

VGA Display Based VHDL on FPGA

Anh, Nguyen Tuan

Thai Nguyen University of Technology

Thai nguyen, Viet Nam

Email: tuananhktmt@gmail.com

Dung, Hoang Thi Kim Thai Nguyen University of Technology

Thai nguyen, Viet Nam Email: hoangthikimdung85@gmail.com

Abstract—VGA (video graphics array), as a standard interface, has already been applications

widely There are a lot of FPGA-based VGA controller designs on which, however, there are still larger defects such as low-resolution display and the Chinese characters display modules occupying large resource Therefore, we propose the use of VHDL as a logical means to describe the completion of high-resolution VGA control module and a resource-conserving string display module design, and provide two main modules of designing ideas and logic diagrams And experiments show that: while the Chinese characters ensure a high-resolution display, the storage resources needed by the display decreased significantly

Keywords: VGA; display interface; character string; FPGA; VHDL VGA

I INTRODUCTION

VGA interface (Video Graphic Array[1]), as a

standard interface, has already been

applications widely VGA have to be working in

a certain display mode anytime, and there are

two kinds of these modes: character display

mode and graphics display mode While, in

applications, all that we talk is the later one

And there are three kinds of the graphics

display mode: the mode which CGA and EGA

are compatible, the standard VGA graphics

display mode and the expanding VGA graphics

display mode The latter two kinds mode are

named VGA graphics display mode And to

make a high-resolution and refreshing rate, we

take the standard VGA graphics display mode

with 800×600@72Hz People formerly used

Generic Processor widely to control VGA

interface to display the character and other

messages In this way, while there is one

advantage which is the easy controlled, there is

also a mainly weakness which is the bad

real-time ability, especially we can hardly keep the

real-time ability when we do the complex and

high-resolution control, besides this design is

less flexible and lager resource occupying To

work out these things, we bring forward the

design that based on line, field refresh scan which is controlled by FPGA

II THEORY OF VGA INTERFACE VGA is an analog signals standard of the computer display which is brought forward by IBM in.1987 Recently most computers transport data to the exterior display equipments through the analog signals VGA interface The graphics data which is processed through digital mode in the computer, will be firstly transformed into tricolor signals (R, G and B) and horizontal, vertical synchronization signals through D/A switch on the display card, and will finally be sent to the display equipment to show And in the analog display equipment, such as analog CRT display, signals are sent to the relevant processing unit directly

to drive kinescope to draw picture

A VGA Interface Signals

There are two kinds VGA interface signals to display One is data signal, and the other one is control signal They are just shown in Table1 Table1 List of VGA Interface Signals

Data Signal

Red Green

Blue Control

Signal

Horizontal Synchronization Vertical Synchronization And there are different frequencies of the

horizontal synchronization signal and vertical

synchronization signal for the changeable

output resolution Here is a table to imply the

range of frequencies corresponding to these

common resolutions They are just shown in

Table 2

Table2 List of Frequencies Corresponding to

Common Resolutions [3]

Resolutio

n

Horizontal

Sync(KHz

)

Vertical Sync (Hz)

Pixel Clock (MHz) 640×480

800×600

800×600

1024×76

8

1024×76

8

31.496

48.077

46.875

48.363

56.476

59.940 72.188 75.000 60.004 70.069

25.175 50.000 49.500 65.000 75.000

In VGA control based on FPGA, we only need to

consider these five signals: horizontal

synchronization signal, vertical synchronization

signal, red data signal, green data signal and

blue data signal As the five signalscan be sent

to VGA interface from FPGA, we can make the

control of VGA

B VGA Interface Definition[4]

VGA interface sends corresponding display

signals to display through DB-15 linker which is

directly connected to PC display or LCD by

monitor cable And there are 15 pinholes which

are asymmetrically divided into 3 lines, and

there are 5 on each line Here is Figure 1

showing how these pinholes are arranged

C VGA Color

Signal In this system, FPGA drives 5 VGA signals directly using series resistance Every color signal is linked to a resistance serially, and a bit

of color signals are made up of VGA_RED, VGA_GREEN, VGA_BLUE Every resistance should match the cable resistance of 75 Ohm in terminal, and this can make sure that the voltage of color signals are kept between 0~0.7V which is the rated load While, VGA_Hs and VGA_Vs drive level use standard LVTTL or LVCMOS3 I/O Finally, there will be 8 kinds of color according to which level are VGA_RED, VGA_GREEN, VGA_BLUE put They are just shown in Table 3

Table 3 3-Bit Code of Color Signal

VGA_RE D

VGA_GREE N

VGA_BLU

0 0 0 0 1 1 1 1

0 0 1 1 0 0 1 1

0 1 0 1 0 1 0 1

Black Blue Green Cyan Red Pink Yellow White

D VGA Timing Control

[5] Timing of VGA signals are ruled by VESA Here is a short introduction about how FPGA drive the VGA display with 800×600@72Hz In the standard of VGA industry, the output frequency of pixel is 50.000MHz, and the frequencies of horizontal scan and vertical scan are 48.077 KHz and 72.188 Hz If display receives this standard frequency, then the resolution will be 800×600, and refresh rate is 72Hz Figure 2 show us the process of horizontal and vertical scan of VGA

Besides this area, there are line blanking zone

and field blanking zone And to realize the

ranks of synchronization, the actual output

pixel of VGA interface is 1040×666, when the

resolution is 800×600 And here, the timing

demands of horizontal scan are listed in Table

4, while timing picture is shown on Figure 3

Figure 3 Horizontal Scan Timing

The timing demands of vertical scan are listed

in Table 5, while timing picture is shown in

Figure 4

Figure 4 Vertical Scan Timing

The timing of VGA signals must be exact in order to create output that a monitor can understand and interpret correctly This means

if the timing is incorrect the output will be incorrect [10]

Tutorial Goals:

Resolution: 640x480 pixels (307,200 total pixels)

Field Refresh Rate: 60 Hz Line Refresh Rate: 31,476 Hz

These numbers can be found in any monitor manual It is the standard that has been developed so that videocard manufacturers can know how to output video properly to all monitors Now, how do we apply these numbers to create video with our little CPLD? Understanding the above picture is where things get confusing

Field Refresh Rate = 60 Hz = Screen Refreshed Once every 16.66 ms

Line Refresh Rate = 31,476 Hz = Once every 31.77 uS

31.77 uS * 480 Lines = 15.249 mS as Seen above for the Display

The extra 1.41 mS is used for the Vertical Sync 1.41 mS + 15.249 mS = 16.666 mS

Figure 6 Theory of the VGA signal Since our microcontroller executes 1 instruction every 1uS we will end up only being able to control 25 distinct spots across each line as data output is 25uS per line That's all

the math & numbers I'll through in for the

moment, but that is a more indepth & less high

level explaination of VGA signals

Key Concepts

·Every line gets roughly 25 uS to display data

·The combination of all the lines creates the

entire picture on the screen

·The Screen is refreshed once every 16.66 mS,

or with a frequency of 60 Hz

III THE SOFTWARE [10]

The entire software project is included in the

zip file for download The main vhdl file (.vhd)

is heavily commented to help you understand

what is going on The pin assignments are also

already done as well

What It Takes

The software for this project is quite long so I'll

only go over some of the more important

parts For the entity that we are creating in

VHDL:

-« Begin Code » -

ENTITY VHDL_VGA IS

PORT(

Counter/VGA Timing

clk: IN STD_LOGIC;

-VGA Signals/Pins

hsync,

vsync,

red,

green,

blue : OUT STD_LOGIC;

Sync Counters

row,

column:OUT STD_LOGIC_VECTOR(9 DOWNTO

0));

end VHDL_VGA;

-« End Code » -

As you can see in the entity we only need 5 outputs

to the VGA connector to output a signal to the

monitor The one input we use will be a clock input

from the 25.175MHz clock which is 'perfect' for

640x480 resolution & VHDL

Specific Timing

The following code will allow us to create the

specific timing necessary for each signal:

-« Begin Code » -

WAIT UNTIL(clk'EVENT) AND (clk = '1'); IF(cnt = 25175000) THEN

cnt := 0;

ELSE cnt := cnt + 1;

END IF;

-« End Code » -

The first line shows that we will always wait 1 clock cycle before performing the rest of the process The rest of the code is not actually used in the problem but through the rest of the process cnt can be used

as a reference for timing necessities

FULL TEST CODE :

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

USE IEEE.STD_LOGIC_ARITH.ALL;

USE IEEE.STD_LOGIC_UNSIGNED.ALL;

Define The Core Entity ENTITY VHDL_VGA IS

PORT(

Counter/VGA Timing clk : IN STD_LOGIC;

VGA Signals/Pins (Outputs) hsync,

vsync, red, green, blue : OUT STD_LOGIC;

Sync Counters row,

column : OUT STD_LOGIC_VECTOR(9 DOWNTO 0));

end VHDL_VGA;

Define The Architecture Of The Entity ARCHITECTURE behavior of VHDL_VGA IS

Sync Signals SIGNAL h_sync, v_sync:STD_LOGIC;

Video Enables SIGNAL video_en,

horizontal_en, vertical_en : STD_LOGIC;

Color Signals SIGNAL red_signal,

green_signal, blue_signal : STD_LOGIC;

Sync Counters SIGNAL h_cnt,

v_cnt : STD_LOGIC_VECTOR(9 DOWNTO 0); BEGIN

video_en <= horizontal_en AND vertical_en; PROCESS

variable cnt: integer range 0 to 25175000;

BEGIN

WAIT UNTIL(clk'EVENT) AND (clk = '1');

IF(cnt = 25175000)THEN

cnt := 0;

ELSE

cnt := cnt + 1;

END IF;

Horizontal Sync

Reset Horizontal Counter

IF (h_cnt = 799) THEN

h_cnt <= "0000000000";

ELSE

h_cnt <= h_cnt + 1;

END IF;

Generate Horizontal Data

160 Rows Of Red

IF (v_cnt >= 0) AND (v_cnt <= 159) THEN

red_signal <= '1';

green_signal <= '0';

blue_signal <= '0';

END IF;

160 Rows Of Green

IF (v_cnt >= 160) AND (v_cnt <= 319) THEN

red_signal <= '0';

green_signal <= '1';

blue_signal <= '0';

END IF;

160 Rows Of Blue

IF (v_cnt >= 320) AND (v_cnt <= 479) THEN

red_signal <= '0';

green_signal <= '0';

blue_signal <= '1';

END IF;

Generate Horizontal Sync

IF (h_cnt <= 755) AND (h_cnt >= 659) THEN

h_sync <= '0';

ELSE

h_sync <= '1';

END IF;

Vertical Sync

Reset Vertical Counter

IF (v_cnt >= 524) AND (h_cnt >= 699) THEN

v_cnt <= "0000000000";

ELSIF (h_cnt = 699) THEN

v_cnt <= v_cnt + 1;

END IF;

Generate Vertical Sync

IF (v_cnt <= 494) AND (v_cnt >= 493) THEN

v_sync <= '0';

ELSE

v_sync <= '1';

END IF;

Generate Horizontal Data

IF (h_cnt <= 639) THEN

horizontal_en <= '1';

column <= h_cnt;

ELSE

horizontal_en <= '0';

END IF;

Generate Vertical Data

IF (v_cnt <= 479) THEN

vertical_en <= '1';

row <= v_cnt;

ELSE vertical_en <= '0';

END IF;

Assign Physical Signals To VGA red <= red_signal AND video_en;

green <= green_signal AND video_en;

blue <= blue_signal AND video_en;

hsync <= h_sync;

vsync <= v_sync;

END PROCESS;

END behavior;

What To Do Now

There are many directions you can take after understanding the VHDL code for generating such a simple VGA output You can explore how to create different colors, different shapes You will be surprised at how complex it can be to create simple shapes like triangles, pentagons or circles

IV CONCLUSIONS

Using programmable logic device we can easily design a digital system, and with VGA which is based on FPGA we can realize real-time show

of display Controlling VGA through FPGA, we can make use of wee and flexibility which is the

advantage of FPGA, and work out these

weaknesses such as inflexibility of processor

and too much space-taking

This tutorial has a redeeming value in that you

create vga signals that work on any and all vga

monitors, LCDs and projectors There is plenty

of room to continue working past what is done

in this tutorial and I feel this tutorial has given the reader a solid base for VGA generation

REFERENCES

[1] Song Pan, Jiye Huang EDA Technology and VHDL [M] Beijing ： Tsinghua University Press，2007：22-26

[2] Yaping Zhang, Zhanzhuang He Designing of VGA Display Module Base on FPGA [J] Computer Technology and development，2007.6，17（6）：242-245

[3] Spartan-3E Starter Kit Board User Guide [EB/OL].http://www.xilinx.com

[4] Definition of VGA Interface [EB/OL] http://www.christie.cn/vga15.htm

[5] VGA timing information [EB/OL] http://www.epanorama.net/documents/pc/vga_timing.html [6] Bing Dong, Qidan Zhu, Rui Wen Realization and Design of VGA Graphics Control Based on FPGA [J] Applied Science and Technology，2006.10，33（10）：42-45

[7] Liang Wang, Zhen Li, Tingting Ning Realization and Design of Chinese Characters on FPGA[C] ICCSE2008，2008.6.25-2008.6.27

[8] Yun Cao Realization and Design of VGA Timing Color Bar Signal Based on FPGA[J] Electronic Application Technology, 2002, 28（7）：42-45

[9] Pengbo Wu, Qiming Zhang, Zhaoyang Wang, Dou Niu Design of VGA Graphics Control Based on FPGA[J] Journal of Northeast China Electric Power University 2006，26（4）：89-92

[10] http://www.pyroelectro.com/tutorials/vhdl_vga/index.html