Handbook of High Temperature Superconductor Electronics Part 4 pdf

The ramp-edge SNS is one of the very attractive device structures used to fabricate high-temperature superconducting junctions because it provides many advantages.. This ramp-edge SNS st

High-Temperature Superconducting

Multilayer Ramp-Edge Junctions

Q X Jia

Los Alamos National Laboratory, Los Alamos, New Mexico, U.S.A.

There has recently been tremendous progress in the development of high-temper-ature superconducting Josephson junctions and superconducting quantum inter-ference devices (SQUIDs) fabricated from YBa2Cu3O7 (YBCO) thin films Josephson junctions have potential applications to high-speed low-power digital logic, whereas SQUIDs are the most sensitive sensors to the magnetic field A Josephson junction is composed of two superconductors separated by a barrier Cooper pairs can tunnel or diffuse through the barrier and current flows through it with no voltage appearing across the junction (1,2)

Josephson junctions and their related devices have been fabricated using conventional low-temperature superconductors where the main building block of the device is based on a configuration of superconductor/insulator/superconduc-tor (SIS) In contrast to low-temperature superconducting junctions, many junc-tion structures have been investigated for high-temperature superconductors in or-der to fabricate reproducible and controllable junctions Since the first report on the fabrication of a natural grain-boundary Josephson junction using YBCO (3), there have been many efforts in the fabrication of Josephson junctions and

SQUIDs based on different device constructions Bicrystal grain boundary (4), biepitaxial grain boundary (5), step-edge grain boundary (6), step-edge supercon-ductor/normal-metal/superconductor (SNS) (7), ramp-edge SNS (8), locally dam-aged superconducting line by ion beams (9), and interface-engineered junctions (10) are the most commonly investigated configurations

The ramp-edge SNS is one of the very attractive device structures used to fabricate high-temperature superconducting junctions because it provides many advantages Shown in Figure 3.1 is a generic structure of a ramp-edge SNS junc-tion The device is composed of top and bottom superconductor electrodes iso-lated in the overlapping region by an insulating layer The active area of the de-vice is located on the ramp, where the N-layer is sandwiched between the top

and bottom superconductor electrodes This ramp-edge SNS structure uses

c-axis-oriented superconducting films, where the Josephson current flows along

the a-b planes of the electrodes The most important feature of this SNS scheme

compared to that of the grain boundary is that the device can be put anywhere

on a chip without affecting other devices This feature allows flexibility in de-vice design and substrate choice, which makes it possible to fabricate more com-plicated circuitry Because the junction performance depends on the N-layer thickness and resistivity in the ideal case, one can control the physical proper-ties of the N-layer to fabricate Josephson junctions for specific applications This chapter describes the processes and materials issues to fabricate ramp-edge SNS junctions and SQUIDs It also discusses the recent progress in the fabrica-tion of high-temperature superconducting ramp-edge SNS juncfabrica-tions and SQUIDs

F IGURE 3.1 Cross-sectional diagram of a ramp-edge superconductor/normal-metal/superconductor (SNS) junction The active area of the device is located

on the ramp, where the normal metal is sandwiched between the top and bot-tom superconductor electrodes.

3.2 PROCESS AND FABRICATION OF MULTILAYER

RAMP-EDGE SNS JUNCTIONS

To fabricate the multilayer ramp-edge SNS junction shown in Figure 3.1, one has

to go through several processing steps, such as multilayer thin-film deposition, patterning, metallization, packaging, and so on The most commonly used tech-nique to deposit high-temperature superconducting electrodes and the normal-metal layer is pulsed-laser deposition (PLD), although high-temperature super-conducting thin films have been deposited by other techniques The substrates commonly used are highly polished single-crystal LaAlO3, MgO, NdGaO3, Sr-TiO3, (LaAlO3)0.3–(Sr2AlTaO6)0.7, and yttria-stabilized zirconia (YSZ) The most commonly used insulating materials to isolate the superconducting electrodes are PrBa2Cu3O7(PBCO), LaAlO3, NdGaO3, SrTiO3, MgO, and CeO2 The insulating layer should be highly resistive at operating temperatures It should also be ther-mally stable at a deposition temperature as high as 800°C and not be poisonous to superconductors or N-layer materials

The following presents an example of processing steps in the fabrication of

a multilayer ramp-edge SNS junction by using YBCO as electrodes and PBCO as the N layer The bottom YBCO (250  20 nm) electrode and the insulating CeO2

layer (300  20 nm) are deposited first on the LaAlO3substrate The first pho-tolithographic mask is used to define the location and geometry of the bottom YBCO electrode Ion milling with 200–250-eV Ar ions is used to etch the CeO2/YBCO and to form the active ramp edge of the device The angle between the edge and the substrate surface is controlled in the range of 15° 3° (11) The N-layer PBCO and the top YBCO electrode are deposited after strip-ping off the photoresist (PR) and cleaning the edge surface The second mask is used to define the geometry of the active area of the device Ion milling is used again to remove unnecessary material and to expose the bottom YBCO for elec-tric contact

The third mask is a lift-off mask that is used to define the location and ge-ometry of contact pads The contact electrodes can be either Ag or Au The fin-ished chip is annealed at 400–500°C in oxygen for a desired period of time before packaging for electrical measurements In total, three masks and two ion-milling steps are used to finish the device fabrication Figure 3.2 shows the processing se-quence to fabricate ramp-edge SNS junctions Figure 3.3 shows a top view of a finished SNS junction near the active area of the device Top and bottom YBCO electrodes could be clearly distinguished from this photograph The contrast of the electrodes shown in Figure 3.3 is due to different surface finishes

It is very important to have a shallow angle ( 30°) between the plane of the exposed ramp edge and the substrate plane This is essential because a

high-qual-ity epitaxial c-axis-oriented N layer cannot be grown on a steep edge A shallow

angle also makes it easier for the N layer to cover the ramp region with high uni-formity and homogeneity The degree of the angle can be controlled by baking the

PR before the first ion milling For example, the angle between the substrate sur-face and the edge is above 70° with no bake of PR before ion-milling, but around 15° with a bake of PR at 170°C for 1 min (11)

As an alternative to ion milling for the formation of the ramp edge, a mi-croshadow mask can be used to form a very shallow angle and damage-free edge This can be done in a completely in situ process (12,13) The in situ growth and

the avoidance of any treatment of the interfaces result in junctions with a high I c R n

product and in the possibility of using a rather thick N-layer barrier

The ion-milling energy and the beam orientation have been found to be cru-cial to success in the fabrication of high-performance junctions A series of sam-ples have been fabricated by varying the ion-milling energy (200, 300, 600, and

F IGURE 3.2 Processing sequences in the fabrication of high-temperature su-perconductor multilayer ramp-edge SNS Josephson junctions, where PR rep-resents photoresist.

900 eV) while fixing the orientation of the ion beam at 60° from normal into the edge of the PR The experimental results have shown that the higher ion beam en-ergies lead to less control of the device performance The device yields are also lower when using a high ion-milling energy (14) It has been reported that the de-position of PBCO on an ion beam (with energy of 600 eV) etched and annealed YBCO surface produces an additional layer of cubic and cation-disordered YBCO

or PBCO in a few nanometers thickness The annealing treatment of the damaged surface at 800°C in oxygen atmosphere does not restore the perfect lattice struc-ture of the film (15) However, it should be noted that the degree of the damage to the crystal structure and of the suppression of superconducting properties of YBCO due to ion irradiation depends on the energy and fluence of the ions used (16) In general, ion beam energy of around 250 eV or lower should be used in or-der to minimize the surface damage Substrate cooling during ion milling is also important to preserve electrical properties of superconductor electrodes and the mechanical properties of the PR Cooling the substrate stage with chilled water should be sufficient Liquid nitrogen has also been used to cool the substrate stage during ion milling (17)

Ion-milling damage to the ramp edge can be partially removed by Br–ethanol etching after the ion-milling process (18) It has shown that the inter-faces produced involving Br–ethanol etching are essentially of the same structural quality as those produced by the microshadow mask technique, which leads to

F IGURE 3.3 Top view of a finished SNS junction, where the ramp-edge and top/bottom superconductor electrodes are clearly evident.

abrupt and coherent interfaces (15) However, it should be noted that the angle of the edge could be significantly increased by increasing the time of the chemical etching or in combination with ion beam etching (19) In addition, for using low ion-milling energy, annealing the sample in oxygen can be also performed prior

to the N-layer deposition to reduce the surface damage

RAMP-EDGE SNS JUNCTIONS

High-quality epitaxial superconducting electrodes are essential for high-perfor-mance devices because these films show less critical current fluctuation and vor-tex hopping For ramp-edge SNS junctions, the superconducting electrode needs

to be oriented with the c axis normal to the substrate surface The typical thickness

of the superconductor electrode is in the range 200–300 nm The general require-ments of physical and superconducting properties of the electrodes are as follows: The orientation mosaic from both the out of plane and in plane should be as small

as possible; the surface should be as smooth as possible; and the zero-resistance temperature and the critical current density at 77 K should be as high as possible The bottom superconducting electrode plays an important role in determin-ing the properties of the ramp-edge SNS junctions Thus far in high-temperature superconductor ramp-edge SNS junction development, YBCO is the most widely investigated electrode material Recently, DyBa2Cu3O7(20), GdBa2Cu3O7(21), Ag-doped YBCO (22), Y1
xCaxBa2
yLayCu3O7 (23), YBa1.95La0.05Cu3O7(24), and NdBa2Cu3O7(25) have been investigated as superconductor electrodes It has been shown that both the base-electrode material and deposition technique can have a strong effect on SNS device resistance (25)

The choice of GdBa2Cu3O7instead of YBCO as the superconductor

elec-trode is mainly due to the close lattice match (either a and b or c) between

GdBa2Cu3O7 and Pr-doped YBCO (21) The GdBa2Cu3O7 also tends to give a higher zero-resistance temperature than YBCO Ag-doped YBCO is used as elec-trodes because it provides superior environmental stability compared to pure YBCO (26) Ramp-edge SNS junctions fabricated from Ag-doped YBCO super-conducting electrodes exhibit little sign of degradation in air (27) Importantly, the controllability and reproducibility of the processing is improved substantially when using Ag-doped YBCO for the electrode (28)

The high corrosion resistance of Y1
xCaxBa2
yLayCu3O7makes it attrac-tive as an electrode in ramp-edge SNS junctions It has been found that a cosub-stitution of Ca2+for Y3+and La3+for Ba2+in Y1
xCaxBa2
yLayCu3O7can com-pensate the Cu valence and maintain the transition temperature above 80 K For

this system, an orthorhombic to tetragonal transition is found to occur at y
0.4 (29) Experimental results have shown that Y0.6Ca0.4Ba1.6La0.4Cu3O7 possesses high corrosion resistance in water as well as enhanced processability (30) YBa2
xLaxCu3O7with x 0.025–0.05 is chosen as the electrode because a

small amount of La doping can help suppress a-axis grain formation (24) The use

of NdBa2Cu3O7is probably due to the fact that the newly optimized NdBa2Cu3O7

films are superior to YBCO thin films, with respect the transition temperature, crystallinity, surface stability and smoothness, and oxygenation properties (31)

RAMP-EDGE SNS JUNCTIONS

Many N-layer materials have been investigated to fabricate ramp-edge SNS junc-tions Conductive oxides and doped YBCO are the main choice for N-layer mate-rials because of their favorable electrical and structural properties The thickness

of the N layer depends on the material used and the requirements of the specific designs It is necessary to consider the following factors when choosing N-layer material It should be lattice and thermal expansion matched with the supercon-ductor electrode; there should be negligible chemical reactions with the electrode; the growth conditions should be compatible with the stability of the superconduc-tor electrode; and the thin N layer should be smooth and pinhole free The electri-cal properties of the N-layer material should also be considered in order to tune the device performance for specific applications Table 1 outlines the N-layer ma-terials reported in the literature for the fabrication of ramp-edge SNS junctions (32–46) For completeness, Table 3.1 also outlines the superconductor electrodes

T ABLE 3.1 Different N-Layer Materials Used in Edge-Geometry SNS Junctions

YBCO Y 0.7 Ca 0.3 Ba 2 Cu 3 O 7
 11,40 YBCO YBa2Cu2.79Co0.21O7
 40, 41

YBCO LaO.5Sr0.5CoO3, La1.4Sr0.6CuO4 40 YBCO PrBa 2 Cu 3
xGaxO 7(x 0.15, 0.3) 42

YBCO Y 1
xPrxBa 2 Cu 3 O 7 (radient) 43

used to fabricate these devices Currently, the most commonly used N-layer ma-terials for ramp-edge SNS junctions are Co-doped YBCO and PBCO

It should be noted that the N layer may not always determine the junction properties in ramp-edge SNS configuration due to the interface and the inhomo-geneity of the N layer Depending on the N-layer materials and fabrication pro-cesses, the resistance of junctions can be controlled by the interface instead of the N-layer barrier For example, the majority of the junction resistance comes from the interface between YBCO and the barrier with conductive oxides such

as CaRuO3 and SrRuO3 as N-layer material It is speculated that the stress due

to the thermal expansion mismatch between YBCO and CaRuO3 may give rise

to oxygen disorder in the vicinity of the interface and thereby increase the in-terface resistance (40) Resistance of junctions can be only determined by the physical properties of the N layer if the interface resistance is negligibly small compared with the N-layer resistance For example, the use of Co-doped YBCO

as a barrier for ramp-edge SNS junctions seems quite promising based on the published results No significant interface resistance between YBCO and the barrier has been observed (40) In this case, the temperature dependence of the critical current of the junction can be well described by the conventional prox-imity effect (47) It should be noted also that the inhomogeneity of the N layer can lead to pinholes or microshorts in the barrier The rough ramp-edge mor-phology of YBCO may even induce the nucleation of secondary phases which have completely different electrical characteristics, thus changing the behavior

of the junctions (48) In this case, the junction current and resistance may not be controlled by the N-layer thickness Therefore, it is important to carefully con-trol the morphology of ramp-edge

Recently, interface-engineered ramp-edge Josephson junctions have been fabri-cated by modification of the edge surface prior to counterelectrode deposition These devices appear to be uniform and reproducible A detailed description of the processing procedures can be found in Ref 10 It is well known that the crystal structure and chemical composition strongly influence electrical properties of YBCO materials The idea in this scheme is to create a few-nanometer-thick sur-face layer of YBCO on the junction edge by altering the structure or chemistry of the existing YBCO to form an effective barrier

It should be noted that the nature of the barrier based on this technique is still unclear It is speculated that the barrier material created in this way is near some sort of metal–insulator transition It is also argued that a normal conducting barrier is formed by the depression in the transition temperature of the YBCO due

to the induced particle damage from this process (49)

3.6 CHARACTERISTICS OF MULTILAYER RAMP-EDGE SNS

JUNCTIONS

The current–voltage (I–V ) characteristic of an ideal

superconductor/insulator/su-perconductor Josephson junction is described by a resistively and capacitively

shunted junction model for which the device shows a hysteretic I–V curve For the

high-temperature superconducting ramp-edge SNS junction, on the other hand,

the capacitance of the device is negligibly small In this case, the I–V

characteris-tic can be described by a resistively shunted junction (RSJ) model:

V  I c R nI I

c

2

11/2

where the device shows a nonhysteretic I–V curve as shown in Figure 3.4 In Eq (1), the I c is the critical current of the junction and the R nis the junction resistance determined from the slope of the dashed line shown in Figure 3.4

F IGURE 3.4 Current versus voltage characteristic of a ramp-edge SNS junc-tion The current versus voltage characteristic can be described by a RSJ model The dashed line in the figure is used to determine the junction resis-tance.

For an ideal SNS junction, the conventional theory of the proximity effect should apply The proximity theory predicts that

I c
I c0exp
L

n n

wheren is the coherence length of the normal-metal barrier and L nis the

effec-tive barrier thickness (L n n ) I c0is somewhat temperature and superconduct-ing electrode dependent The coherence length in the N layer is given by

wherenc  h-v F/2 nd (nc l/3)1/2are the clean-limit (l n) and

dirt-limit (l n ) coherence lengths in the N layer Here, h- is h/2 Fis the Fermi

velocity in the material, and l is the carrier mean free path An excellent review

ar-ticle on the theoretical understanding of SNS junctions is Ref 50 It should be

noted that the effective N-layer thickness L nis proportional to the N-layer

thick-ness (t) with the relationship t/sin, where  is the angle between the substrate

sur-face and the ramp edge In a very shallow-angle ramp-edge junction, the L ncan be

much larger than t.

The presence of well-defined Shapiro steps in the I–V curve under

mi-crowave irradiation is widely used as a verification of the Josephson effect The ramp-edge SNS junctions fabricated using variety of N-layer materials and high-temperature superconducting electrodes also show clear Shapiro steps under mi-crowave irradiation with frequencies in the gigahertz range Figure 3.5 shows a

typ-ical I–V curve under microwave irradiation for a ramp-edge SNS junction

fabricated using Ag-doped YBCO as the electrode and PBCO as an N-layer bar-rier (51) The measured voltage step height agrees well with the theoretical

calcu-lation based on the Josephson recalcu-lation of V n  nhƒ/2e (n  1, 2, ), where

ƒ is the frequency of the applied microwaves and the other symbols have their usual meaning

The actual device performance, on the other hand, is affected by many fac-tors The interface between S/N or N/S has been recognized as the most important controlling factor in determining the performance of SNS junctions (40) The dif-ficulty in controlling the interface comes from several intrinsic and extrinsic sources The interface between S/N or N/S can be degraded due to the anisotropic nature of high-temperature superconductor materials, mismatch in the lattice and thermal expansion coefficient between the superconductor and N-layer, chemical incompatibility between the superconductor electrode and N-layer, growth of the multilayer thin film on a ramp edge instead of on a flat surface, damage to the su-perconductor bottom electrode from the ion beam used to pattern the film, or the unavoidable grain-boundaries intrinsic to the oxides

1 2

nd

1 2

nc

1 2