Micro Electro Mechanical System Design - James J. Allen Part 3 docx

After it is exposed and developed, the photoresist will be used as a physicalmask during subsequent etching processes to transfer the pattern in photoresist on to the thin film of MEMS m

• Easy to start and stop the etch process

• Repeatable etch process

• Anisotropic etches

• Few particulates

Plasma etching includes a large variety of etch processes and associatedchemistries that involve varying amounts of physical and chemical attack Theplasma provides a flux of ions, radicals, electrons, and neutral particles to thesurface to be etched Ions produce physical and chemical attack of the surface,

FIGURE 2.21 Directional etching of crystalline silicon.

TABLE 2.6

Common Crystalline Silicon Etchant Selectivity and

Etch Rates

18HF + 4HNO3+ 3Si → 2H2 SiF6+ 4NO + 8H2O Nonselective

Si +H2O2+ 2KOH → K2 SiO3+ 2H2 {100} 0.14 µm/min

{111} 0.0035 µm/min SiO20.0014 µm/min SiN4not etched Ethylene diamine pyrocatechol (EDP) {100} 0.75 µm/min

{111} 0.021 µm/min SiO20.0002 µm/min SiN40.0001 µm/min Tetramethylammonium hydroxide (TMAH) {100} 1.0 µm/min

{111} 0.029 µm/min SiO20.0002 µm/min SiN40.0001 µm/min

and the radicals contribute to chemical attack The sequence of events that occur

in a plasma etch chamber (Figure 2.23) are listed below:

• Plasma breaks down the feed gases into chemically reactive species

• Reactive species diffuse to the wafer surface and are adsorbed

• Surface diffusion of reactive species takes place until they chemicallyreact

• Reaction product desorption occurs

• Reaction products diffuse away from the surface

• Reaction products are transported out of the chamber

The details and types of etch chemistries involved in plasma etching are variedand quite complex This topic is too voluminous to be discussed in detail here,but a number of excellent references on this subject are available [3,4] The properchoice of these chemistries produces various etch rates and selectivity of materialetch rates, which is essential to the integration of processes to produce micro-

FIGURE 2.22 Boron-doped silicon used to form features or an etch stop.

B B B B B B B B B B B B B B B B B B B B B B B B

Single Crystal Silicon

a Implant Boron in Single Crystal Silicon wafer

electronics or MEMS devices Fluoride etch chemistries are one of the mostwidely studied for silicon etches Equation 2.6 through Equation 2.8 illustratesome of the fluoride reactions involved in the etching of silicon, silicon dioxide,and silicon nitride, respectively A number of feed gases can produce the freeradicals involved in these reactions.

in the polymerization

End point detection of an etch is important in controlling the etch depth orminimizing the damage to underlying films This detection is accomplished byanalysis of the etch effluents or spectral analysis of the plasma glow discharge Types of plasma etches include reactive ion etching (RIE) and high-densityplasma etching (HDP) RIE etching utilizes a low-pressure plasma Chlorine (Cl)-based plasmas are commonly used to etch silicon, GaAs, and Al RIE etchingmay damage the material due to the impacts of the ions; this can be removed byannealing at high temperatures HDP etches utilize magnetic and electric fields

FIGURE 2.23 Schematic of a plasma etch chamber.

Si+4F*→SiF4

3SiO2 +4CF3+ →2CO+2CO2 +3SiF4

Si N3 4 +12F*→3SiF4 +2N2

to increase dramatically the distance that free electrons can travel in the plasma.HDP etches have good selectivity of Si to SiO2 and resist.

Ion milling is a purely physical etching process; no chemical reactions areinvolved Ion milling uses noble gases with significant mass such as argon in aprocess analogous to sputtering This process is very isotropic because the ionimpinges the surface nearly vertically However, the process has an etch rateselectivity of the material to be etched to the mask material of nearly 1:1 becausethe process is purely physical Ion milling is not widely used for productionapplications, and it is generally limited to the smaller wafer sizes (<200 mm).The etch rates can be increased by increasing the ion densities impacting thesurface through the use of magnetic fields

2.6 PATTERNING

The ability to pattern deposited layers is an essential capability required inmicroelectronics and MEMS processing Three widely utilized methods of pat-terning will be discussed: lithography, the lift-off process, and the damasceneprocess

Lithography is the mainstream process utilized for patterning in MEMSprocesses Lift-off and damascene are processes used for patterning materials inwhich a reliable etch process such as metallization layers or optical coating layersdoes not exist These are frequently required in the postprocessing of MEMSdevices

The current research and development in patterning for very fine line widths(<0.35 µm) involve the development of sophisticated tools such as x-ray lithog-raphy [7] or direct-write E-beam lithography [8] Microelectronics will need thecapability to pattern features (line widths) of this size in the future in order tocontinue development of microelectronic devices of increasing speed and capa-bility However, mainstream MEMS technology does not currently require suchfine features, so these methods will not be discussed here

Lithography is the most widely used method to pattern layers in microelectronicand MEMS processing Figure 2.24 is a schematic of a basic lithography system.The basic components of a photolithographic system include:

• Illumination source

• Shutter

• Mask

• Wafer alignment/support system

• Photosensitive layer (photoresist or “resist”) on a wafer

Lithography is the most critical process in microelectronics and MEMSprocesses, and the equipment is generally the most costly in a microelectronics

or a MEMS fabrication facility For example, a microelectronic process willrequire 20 or more lithography steps, and a surface micromachine process willrequire 10 or more lithography steps A lithography process step will generallyrequire application and prebaking of the photoresist to harden the resist; theexposure of the photoresist in the lithography tool; development of the photoresist;and a postbake of the photoresist to fully harden the resist to define the featureaccurately Thus, a lithography step requires several subprocesses that are repeat-edly performed to fabricate a MEMS or microelectronic device The other pro-cessing steps required in a MEMS or microelectonic fabrication may go throughdifferent tools for a specific deposition or a particular type of etch, but lithography

is the common tool that will always be used Therefore, lithography is the criticalpath in the fabrication facility and much attention is paid to the development oftechnology and enhancements that can speed this process step

The performance metrics most important to lithographic processing are olution, registration, and processing throughput The resolution for optical lithog-raphy is very closely tied to the wavelength of the illumination source Thedevelopment of lithographic equipment has used ever decreasing wavelengthillumination from the visible spectrum to ultraviolet (UV) and on to the researchand development use of extreme ultraviolet (EUV)

res-The design of the optical system of the lithographic equipment is very plex, as can be illustrated by the discussion of a few key parameters of the optical

com-system The minimum line width, Wmin, capability of the lithographic system can

be expressed by Equation 2.9, which is very similar to the Raleigh criteria [9]for optical resolution:

FIGURE 2.24 Lithography system schematic.

resist optical system

mask shutter

illumination source

alignment stage

wafer

where

Wmin = minimum line width

K= a measure of the ability of the photoresist to distinguish changes in intensity

λ = illumination source wavelength

NA = numerical aperture

The numerical aperture defined by Equation 2.10 is a function of the refractive

index, n, of the medium between the objective and wafer and the half angle of

the image, α:

(2.10)

Another optical parameter of interest in the design of the lithographic system

is the depth of focus, σ (Equation 2.11) The depth of focus is an issue in MEMSfabrication due to the thickness of the films involved and the possible waferwarpage due to residual stress of the deposited films Films involved in MEMSprocesses can be several microns thick Patterning of the various layers will giverise to topographic features on the wafers When photoresist is spread on a wafercontaining these topographical features or the wafer is warped due to film residualstress, the lithographic process will attempt to expose the photoresist at variousheights, thus making the depth of focus capability a critical issue

(2.11)

As can be seen from this limited subset of the optical design parameters, theoptical design is complex and the design parameters interrelated For example,

to make Wmin smaller, utilizing a smaller wavelength source, λ, and a larger

NA would be beneficial; however, the depth of focus, σ, will be reduced as aresult

Masks contain the patterns that need to be etched into the material to ment the MEMS design The masks can be the same size (1:1) as the patterns to

imple-be transferred and etched into the MEMS material Depending on the lithographicsystem, the masks may be larger than the patterns to be etched into the material.Masks are typically 1×, 5×, or 10× larger than the patterns to be imaged andetched The mask is made of materials (e.g., fused silica) that are transparent atthe illumination wavelength, with the patterns defined by an opaque material(e.g., chromium) at the illumination wavelength The mask will need to be veryflat and insensitive to changes in temperature (e.g., small coefficient of thermal

expansion,αT) Contamination control is also an issue in the lithography process.

For example, masks may have a pellicle membrane (Figure 2.25) held above the

patterned area to keep particles off the mask surface and out of the image plane

of the mask to prevent degradation of the lithographic image

Photoresist is a photosensitive organic compound applied to the wafer surface.The photoresist consists of three components:

• Resin material is organic material that forms the bulk material of thephotoresist that will affect the durability during subsequent processingand resolution of the photoresist

• Photoactive compound is the photosensitive material that determinesthe sensitivity of the photoresist (mJ/cm2) to the illumination needed

to produce a chemical change

• Solventis the component affecting the viscosity of the resist that affectsthe application of photoresist, which is generally done by spinning thewafer and using centrifugal force to spread the photoresist to a uniformthickness The solvent in the resist is then removed during the bakingsteps to make the material structurally rigid

FIGURE 2.25 Photomask with pellicle.

The lithographic process will transfer the image from the mask to photoresist

on the wafer surface Two types of photoresist can be used:

• Negative resist The region of photoresist that has not been exposed tothe illumination will dissolve during the development process and beremoved

• Positive resist The region of photoresist that has been exposed to theillumination will dissolve during the development process and beremoved Positive resist has the best resolution and is more widely used

After it is exposed and developed, the photoresist will be used as a physicalmask during subsequent etching processes to transfer the pattern in photoresist

on to the thin film of MEMS material beneath the photoresist Photoresist is akey material in the lithographic processing sequence as well as the subsequentetch steps It must have a diverse set of properties to enable the definition of thepattern and also maintain physical integrity during subsequent etching processes The aligner is the piece of mechanical equipment that supports the litho-graphic optical system and mask It will align the masks relative to target patterns

on the wafer; this will have the effect of aligning the masks and their subsequentlyetched patterns on the wafer with the mask and patterns utilized later in thefabrication sequence Figure 2.26 shows a typical alignment target, which istypically specified by the lithographic system manufacturer Two general types

of aligners will be considered here:

• Contact/proximity aligner The mask is held in contact or close imity (a few microns) of the photoresist surface These aligners utilize

prox-1× masks and do not have pellicles due to the lack of available ance between the mask and photoresist The contact aligner actually

clear-FIGURE 2.26 Example of a lithographic alignment target.

presses the mask under pressure against the photoresist, which willhave the effect of degrading the mask under repeated use This category

of aligner is the least expensive, and has the lowest resolution bility These aligners are generally used for research or limited pro-duction applications

capa-• Projection aligner The mask and wafer are separated as dictated bythe design of the optical system This class of aligner can have highresolution that is only limited by optical system performance Thesesystems can be very expensive and are utilized in high-volumemanufacturing

Lift-off is a patterning process frequently used in MEMS for patterning materialsthat do not possess a reliable process to etch them (e.g., noble metals) The lift-off process is accomplished via the use of an intermediate layer and depositionprocess, which has poor step coverage Figure 2.27 is a schematic of a lift-offprocess that will deposit and pattern a material on a substrate or underlying layer.This process involves the following steps:

• Deposit and pattern a thick intermediate layer of a material that is easy

to remove (e.g., SiO2 or photoresist) and that will have a slightlyreentrant profile

• Deposit a layer of the material to be patterned utilizing a process thathas poor step coverage (e.g., evaporation) The material thicknessshould be a fraction of the intermediate layer thickness

FIGURE 2.27 Lift-off process schematic.

patterned SiO2/resist

evaporated metal layer

substrate

a Evaporated metal layer on a patterned SiO2or resist layer

b Strip the SiO2or resist layer leaving the metal on the substrate

• Removal of the intermediate layer will cause the metal layer to fracturedue to the stress concentration in the region of poor step coverage.

Alternatively, the lift-off process can involve a process that will explicitlyform an undercut metal layer and not rely on the metal layer to fracture at thestep Figure 2.28 is a schematic of a process that will involve the explicit devel-opment of an undercut region:

• Deposit thick intermediate layer of a material (e.g., SiO2)

• Deposit and pattern a layer of photoresist

• Undercut the photoresist with a process such as wet chemical etching

• Deposit a layer of the material to be patterned utilizing a process thathas poor step coverage (e.g., evaporation) The material thicknessshould be a fraction of the photoresist and oxide layers

• Remove the SiO2 and photoresist, which will leave only the patternedmetal layer

FIGURE 2.28 Lift-off process schematic with undercut metal layer.

resist

substrate (a) Substrate with an oxide layer and patterned resist

(b) Wet etch oxide layer to undercut the resist layer

(c) Evaporate metal layer metal

(d) Strip resist

(e) Remove oxide SiO2

2.6.3 DAMASCENE PROCESS

The damascene process is an ancient process first developed in the Middle East[10] and utilized to inlay elaborate patterns on metal swords with various softmetals that could be easily polished The concept of the damascene process(Figure 2.29) starts with forming a mold upon a substrate, depositing a metalwhich fills the mold and covers the surface The surface is then polished so thatonly the material within the mold remains Then the mold material can optionally

be removed The damascene process like the lift-off process is used to patternmaterials that do not possess a reliable method of etching For MEMS andmicroelectronics, these processes are used for patterning metal layers (e.g.,copper, gold, etc.) The method frequently utilized for polishing the metal layerback to the mold is chemical mechanical polishing, which is discussed later inthis chapter

2.7 WAFER BONDING

Wafer bonding processes are used in packaging and to build up more complexstructures For example, bulk micromachined devices can be assembled into morecomplex structures by bonding multiple wafers together Also, microfluidic chan-nels can be formed by DRIE etching the channel in one wafer and bonding awafer to seal the channel The two categories of wafer bonding processes thatwill be discussed are silicon fusion bonding and anodic (electrostatic) bonding

FIGURE 2.29 Damascene process schematic.

The choice of bonding process will be influenced by the thermal budget of thedevices and materials involved.

At room temperature, two highly polished flat silicon wafers brought into contactwill bond The mechanism is believed to be hydrogen bonds between the surfaces.The bond can be converted into a stronger Si–O–Si bond at an elevated temper-ature (>800˚C) The main concern with this bonding technique is voids in thebonded wafer due to surface defects, residues, and particulate on the surface Theprocessing sequence for silicon fusion bonding will generally include the follow-ing steps:

• Polishing of the wafer surfaces to be bonded

• Wafer surface wet cleaning processes to make the bond surface philic, which will facilitate the bonding mechanism

hydro-• Wafer surface inspection

• Precise alignment of bond surfaces in a clean environment

• Annealing of the bonded wafers

Other silicon-based materials such as polycrystalline silicon (polysilicon),silicon dioxide, and silicon nitride can be similarly bonded However, yield ofthe bonded wafers due to voids will increase due to the different mechanicalproperties of the wafers

Anodic bonding is an electrostatic bonding technique for glass to silicon wafers

or silicon wafers with a thin silicon dioxide layer between the wafers Anodicbonding utilizes a heated chuck with an electrode capable of applying a DCvoltage of up to 200 V Pressure may be optionally applied to facilitate the bondingprocess Figure 2.30 is a schematic of an anodic bonding process

a high temperature for a length of time (e.g., polysilicon residual stresscan be reduced by annealing at >1100°C for several hours in an inertatmosphere, N2, which minimizes oxidation)

• Activation of dopants When dopants are implanted or diffused into amaterial to create active electronic devices or piezoresistors, the dopants

are activated by an anneal process This process facilitates the dopants’movement to an appropriate location within the material lattice struc-ture An anneal temperature of >600°C is typical for this application

• Healing of material damage Implantation of dopants into a materialwill cause physical damage to the material through dislocations of thematerial atoms The material damage is healed by annealing the mate-rial at an elevated temperature (e.g., >600°C)

• Annealing bonded wafers to modify the wafer bond mechanism con to silicon wafer bonds are initially hydrogen bonds that are trans-formed to a Si–O–Si bond through an annealing step that improvesthe wafer bond strength An anneal temperature of >800°C is typical

Sili-of this application

Several anneal process issues are of concern, depending upon the application:

• Thermal stresses, particularly when dissimilar materials are involved

• Doping profile perturbation at elevated temperatures

• Melting of metal layers, which generally occurs at greater than 450°CAnnealing can be accomplished via an isothermal process in which thematerial is exposed to the elevated temperature over a long period of time Theisothermal annealing processes generally require a thermal controlled volumewith a controlled atmosphere

Rapid thermal annealing processes that anneal only a small distance into thematerial exist This process will minimize doping profile perturbations and melt-ing of metal layers within a device This localized rapidly varying thermal cyclingcan be achieved within a fast ramp furnace, which can achieve thermal transients

on the order of 75°C/min A more rapid thermal transient can be achieved bymoving the wafer within a furnace that has thermal gradients designed into theequipment Figure 2.31 is a schematic of a rapid thermal anneal furnace in which

FIGURE 2.30 Anodic bonding schematic.

hydrated surfaces glass wafer

silicon wafer

heater

V

(a) Silicon wafers with hydrated surfaces.

(b) Silicon wafers in contact and anneal.

the wafer temperature is controlled via an elevator within the furnace Thermaltransients on the order of 100°C/sec can be achieved with this type of system.

2.9 CHEMICAL MECHANICAL POLISHING (CMP)

Chemical mechanical polishing (CMP) is a process originally developed in themicroelectronics industry to planarize the layers of interconnect CMP has alsobeen adapted to MEMS processing in surface micromachining (see Figure 2.32).CMP has become essential to MEMS fabrication to remove the topographyformed due to the repeated deposition, patterning, and etching of multiple thickfilm of material typical in MEMS surface micromachine processes The topog-raphy generated in the MEMS processes make patterning with lithographic meth-ods difficult due to depth of focus issues and poor photoresist coverage over theuneven surface The topography also makes the design difficult as well Figure2.32 shows a comparison of a MEMS layer in a surface micromachine processwith and without CMP in the process

In Figure 2.33, CMP utilizes a slurry of silica particles and a dilute etchingagent applied between the wafer and a pad that is mechanically moved (i.e., acombination of rotation and linear motion) The removal rate, typically on theorder of 1000s of angstroms per minute, is a function of the pad pressure, relativevelocity, and slurry chemistry For surface micromachining processes, CMP can

be applied to the sacrificial layers so that the structural layer deposited on topwill not have topography CMP can also be used in the damascene processdiscussed previously to polish the metal layer back to the mold

FIGURE 2.31 Rapid thermal anneal furnace utilizing a wafer elevator to control the

temperature transient.

Heater section

Cool gas inlet

Gas outlet

Figure 2.34 is a two-dimensional representation of a silicon lattice structurewith a doping material included in the lattice Silicon is in group IV of theperiodic table and has four electrons in its outer shell; it shares these with fouradjacent atoms to form a three-dimensional lattice structure Covalent bonding

is the sharing of electrons in the outer shell For pure single-crystal silicon, all

of the electrons in the outer shell of the silicon atoms are shared, thus producing

a silicon crystal with no free electrons If the silicon lattice has a small amount

of a dopant, a free electron or a hole can be produced Figure 2.34a showssilicon doped with phosphorus, a group V element with five electrons in the

FIGURE 2.32 SUMMiT  (Sandia ultraplanar multilevel MEMS technology)

polysili-con layer with and without CMP processing.

FIGURE 2.33 Schematic of a chemical mechanical polishing system.

Linkage arm

Overhang

(a) Example of a conformable Layer (b) Example of topography removed by

Chemical Mechanical Polishing Hub Gear

Planarized linkage arm