FPGA Implementation of Light Rail Transit Fare Card Controller Using VHDL ppsx

Section 3 discourses all the inner module I/O ports including top module, gate_in_chk module, Check_out module, Bal_add module and result module.. If the task controller is “oo” the gate

ISSN 1450-216X Vol.36 No.1 (2009), pp.30-40

© EuroJournals Publishing, Inc 2009

http://www.eurojournals.com/ejsr.htm

FPGA Implementation of Light Rail Transit Fare Card

Controller Using VHDL

M Habib Ullah

International Islamic University Malaysia

E-mail: habib_ctg@yahoo.com

A Unggul Priantoro

International Islamic University Malaysia

M Asraful Hasan

International Islamic University Malaysia

M Jasim Uddin

International Islamic University Malaysia

Abstract

In this paper a new and better fare system is introduced One part of the Light Rail Transit (LRT) system that needs to be upgraded is the fare card controller because smart card (similar to Touch & Go) will replace the existing paper ticket Altera Quartus II Web Edition software tool is used to synthesis of HDL designs, which enables the developer to compile their designs, perform timing analysis, examine RTL diagrams, simulate a design's reaction to different stimuli, and configure the target device with the programmer According to the result in simulation and implementation in the FPGA (Field Programmable Gate Array), it can be said that the designed model is working as expected

Keywords: LRT, FPGA, VHDL, RTL, Fair Card Controller

1 Introduction

The LRT (light rail transit) has become a popular choice for the people to commute throughout the city However, the current fare system of the LRT is said to be lacking efficiency due to the fact that the current fare system requires the payment to be made in the form of cash and using manual ticketing system which can be a hassle and cause inconvenience for its users (W Kim 2003 and H Chang 1999) Therefore, a better system or an improvement is needed to replace the current system

Figure 1: Flowchart of complete design

Fare cards have electrical contacts and a thin metallic plate just above center line on one side of the card Data stored in the Fare card's microchip can be accessed only through the chip operating system (COS), providing a high level of data security (K H Huh, 2003) This security takes the form

of passwords allowing a user to access parts of the IC chip's memory, or encryption/decryption measures which translate the bytes stored in memory into useful information (W Kim 2003) The proposed fare card design three different steps; they are validation, balance check and balance add Validation is performed by checking the 4 bit header After checking the header it will check the available balance, if there is sufficient balance then it will proceed further If there is insufficient balance then it will go on the balance add module

The rest of the paper is organized as follows Top module I/O is described in Section 2 Section

3 discourses all the inner module I/O ports including top module, gate_in_chk module, Check_out module, Bal_add module and result module Section 4 and 5 shows and discusses FPGA implementation and simulation results of the proposed design respectively At the end conclusion is drawn

2 Top Module Input-Output Description

As illustrated in Figure 2, in the top module 16 bit input (data_in) used In these 16 bit input it has 4 parts The first 4 bit used for header, the next 7 bit for balance, next 1 bit for time stamp and the last 4 bits used for station id Firstly when the input is given, the system will check the header (first 4-bit) The purpose of the “1010” header is to indicate that up to 12 more bits of information are to be read by the controller If the header match then will go forward to check the minimum balance otherwise, the process will be terminated In the next step the system will check the time stamp if this bit is 0 the system will be consider the off-peak hour; otherwise the fare will be charged as peak hour The balance indicates the remaining balance on the fare card in 25 cent increments, e.g., “0000100” corresponds to one dollar The one-bit time stamp indicates off-peak hour (“0”) and peak-hour (“1”), respectively In the last part, the system will check the station id of in and out The system will calculate the number of stations traveled to deduct the fare from balance If the previous balance will be enough then only the check out gate will open I used the task controller as 2 bit input to determine the module to process If the task controller is “oo” the gate_in_chk will be processed, if “01” check_out will be processed and if

“10” the bal_add module will be executed The time stamp and station identification fields must have been set to zero

When a passenger enters the station, the system will read the information from the smart card (only header and balance) and determine if the card has sufficient funds for a minimum one-way trip in accordance with the time of the day (K H Huh, 2003) If the amount is insufficient, the card controller

will generate an insufficient fund signal (Gate Open = 0) If the amount on the smart card is sufficient, the system will first reset/erase the card (by writing 16 zeroes) and then write the full 16-bit information, which now includes the time stamp and station ID information The system will return the card to the passenger, and open the gate (Gate Open=1) When a passenger is exiting the station, the system will read the 16-bit information from the card The system will then calculate the fare based on entry station ID, exit station ID and time stamp based on the above formulas If the amount is insufficient, the card controller will generate an insufficient fund signal (Gate Open = 0) If the amount

on the fare card is sufficient, the system will first reset/erase the card (by writing 16 zeroes) and then write the header, and update the balance It will then generate a gate open signal

The LRT system has 16 stations Each station needs controller modules to perform the following tasks:

0 Check-in (At entry – “00”)

1 Check-out (At exit – “01”)

2 Fare Adder before entry (if necessary – “10”)

3 Fare Adder before exit (if necessary – “11”)

Each station has a 4-bit station identification number, N, where, 0 < N <15 The cost of a one-way trip to any station is calculated as follows:

Off-peak hour cost (in ringgit) = 1.00 + |Nin-Nout|x0.25

Peak hour cost (in ringgit) = 1.50 + |Nin-Nout|x0.25

The information on the smart card is stored in 16 bits, according to the following format (W.Rankl, 1997):

Header(4-bits:"1010") Balance (7-bits: 25 cent increment) Time Stamp (1-bit) Nin (4-bits)

Figure 2: Block Diagram of LRT System Fare Card Controller

When a passenger needs to add new funds to the card, the fare adder function will update the balance based on added funds It will do so by first resetting the smart card to zero and then writing the new 16-bit field (which includes the updated balance) The whole operation of reading the input from card, processing the data, updating the card information and opening the gate must be less than 1 second Every bit duration is 10 milliseconds (D S Kim 2008)

3 Inner Module I/O Ports

RTL (register transfer level) is the one of the type of level of abstraction easily dealt with by synthesis tools In RTL design a circuit is described as a set of registers and a set of transfer functions describing the flow of data between the registers (B Gebremichael 2004 and S Moore, 2002) It is a hierarchy list that displays a representation of the project hierarchy and a schematic view that displays the components of the design element of the process

3.1 Top Module

The top module Figure 3 consists of inner modules They are: gate_in_chk, check_out, bal_add and result The first module gate_in_chk module has two inputs data_in and task_controller (header) and two output data_in to the result module Second module check_out has four inputs and two outputs Inputs are: data_in, task_controller (header), time stamp and station ID; outputs to the result module are: gate_open_check_out and data_out_check_out Third module bal_add module has three inputs and two outputs Inputs are: data_in, task_controller (header), and added_fund; outputs to the result module are: gate_open_bal and sum Finally, result module has 6 inputs for the above mention 3 modules and two outputs They are: gate_open and data_out

Figure 3: RTL design of top module

3.2 Gate_in_chk Module

In figure 4 Gate_in_chk module, the system will check the header If it is match then will go forward to check the minimum balance available for 1 station If it is available then the system will allow to gate open; otherwise the process will be cancelled

Figure 4: RTL design of Gate_in_chk module

3.3 Check_out Module

In this module Figure 5 the system will check the header If the header is ok, then will check the available balance for traveled station The check out gate will open if there is enough balance Finally it will deduct the balance for traveled station from available balance Otherwise the gate out will be 0

Figure 5: RTL design of Gate_in_chk module

3.4 Bal_add Module

In the Bal_add module as bellow Figure 6, the system will upgrade the balance according to the value given to task controller If the task controller is “10” then this module will be processed Balance will

be added before enter to station

Figure 6: RTL design of Bal_add module

3.5 Result Module

After check the balance, the instruction will go to the result as demonstrated in Figure 7 If there is no sufficient fund in the fare card then it will check the Bal_add module to find any new balance added After verifying that there is sufficient fund then the output will be activated otherwise the process will

be terminated

Figure 7: RTL design of result module

4 FPGA Download

Figure 8: Illustration of EP2S1F484C3device of Stratix II family FPGA

Figure 9: Nios Development Board JTAG Switch Configuration

4.1 FPGA PIN Configuration

The PINs are fixed for the FPGA while using the NIOS board Table 1 shows the PIN allocation of the APEX FPGA with few of the peripherals on this NIOS board:

LED1 T18

LED2 T19

SW1(8-bit, ordering 8 down to 1 in SW1) V9 U9 T10 U10 V10 P11 U12 Y10

SW4 Y9

SW5 T9

SW6 Y8

SW7 W9

Clock L6

2 Seven Segments(16-bit, 0 to 15) W17 U18 Y18 W18 U8 T11 R10 C18 V17 V18 Y17 V8 Y7 U11 R11 D18

4.2 PIN Assignment for the Design

According to table 1, using Pin Planner all required pins has been assigned Illustration of all required pin assignment as the following Figure 11

Figure 11: Illustration of pin assignment

4.3 PIN Assignment Description Table

Input Pin Output Pin Clock

A[5] V9

A[7] T10

B[0] V10

B[2] U12

L6

4.4 Top Module Compilation Report

After design the top module (named lrt) including sub modules, it has successfully compiled using

Quatrus-II Version-7.1 web edition EP2S1F484C3device of Stratix II family FPGA has been used

Figure 7: Compilation report of the top module

5 Simulation Result and Discussion

5.1 Simulation Result of Balance Add

From the simulation result in Figure 8 it is observed that, the balance field consists "0000111"(1.75 dollar) The station ID field shows "0110", it indicates 6 station travelled The 12th bit "0" indicates off-pick hour The balance field needs to have minimum 2.5 dollar However, in the data_out balance shows insufficient fund and the gate_open is "0"

Figure 8: Simulation result of the Balance add module

5.2 Simulation Result of Insufficient Fund

From the simulation result of Insufficient fund Figure 9 observed that, the balance field consists

"0000011" (50 cents) The time_stamp is "1" indicates pick hour The station id shows that it travelled

4 stations Because of insufficient fund the gate_open field is "0"

Figure 9: Simulation result of the Insufficient Fund

5.3 Simulation Result of Station Traveled

The simulation result of station travelled shown in Figure 8, balance field shows 4.25 dollar available The station id shows the number of station travelled are 6 which need minimum balance 2.5 dollar in off-pick hour The gate_open is "1" allows to go as it has the sufficient balance

Figure 8: Simulation result of the No of Station Travelled

Conclusion

The objective of this paper is to design and hardware implementation of automated LRT fare card controller Since the use of train increasing dramatically for our daily travelling, automated fare card control system is become vital for efficient operation An attempt is made to keep the design as simple

as possible to ease the implementation Automated card controller system will save users’ valuable time by avoiding the queue length in front of the ticket counter and it also ensure security It is designed using VHDL, simulated in Quartus II, downloaded in a FPGA chip and it’s functionality has been verified

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