ECE 574: Modeling and Synthesis of Digital Systems using Verilog and VHDL ppsx

It has a clock and an asynchronous active high reset signal, one input called sensor and one output called valve.. ECE574: VHDL and Verilog Modeling and Synthesis 3 12/08/10 Question 2 [

ECE574: VHDL and Verilog Modeling and Synthesis 1 12/08/10

ECE 574: Modeling and Synthesis of Digital Systems using Verilog

and VHDL - Fall 2010 Final Exam – Verilog (6.00 to 8.30)

SOLUTIONS

This exam is in two parts

• The first part is closed book (no books or notes allowed)

• The second part is open book (books and notes are allowed)

Read each question carefully

Use a standard and consistent coding style

Try and answer each question - if you consider any question to be ambiguous then state any assumptions you make

NAME: _

ECE Box:

Question 1 [25 marks]: A state machine used in a process control system has 3 states It has

a clock and an asynchronous (active high) reset signal, one input called sensor and one output called valve The valve output is high in state S1 or S2 The next state/output table is:

S*

Draw a state diagram of the state machine

Write a synthesizable description of this controller Use a standard two always statement

style Describe the output logic using a separate assign statement

ECE574: VHDL and Verilog Modeling and Synthesis 3 12/08/10

Question 2 [20 marks]: Write the Verilog synthesizable module description of a counter

with an asynchronous reset (active high) signal The counter should count from 7 to 77 on a negative edge of the clock and then restart at 7

to a GPS device in another system with its own clock The GPS device generates a 1PPS (one pulse per second) signal that is high for approximately 10us in duration that it sends to the FPGA

It is necessary for the FPGA to generate a single 10ns pulse each time it detects the 1PPS pulse

Write a synthesizable module for the FPGA that will convert the 10us pulse from the GPS device clock domain into the 10ns pulse inside the FPGA The start of the module description

is provided:

module gps_pps (

input clk,

input pps_long,

output pps_short

);

ECE574: VHDL and Verilog Modeling and Synthesis 5 12/08/10

Question 4 [35 marks]: Write a Verilog model of an SRAM memory device with the

following specifications:

Address bus - 9 bits

Data bus - 8 bits

Active low control signals: CE, OE, WE

Read operation (CE and OE valid):

In the model, output the correct data only after an access time of tacc from OE and CE

Write operation (CE and WE valid - write data on the rising edge of WE)

In the model check that the address bus is stable for taddr and the data bus is stable for tsetup

before the rising edge of WE

If they do not meet these requirements then issue appropriate error messages

Use parameters for the access, address, and setup times with default times of 50, 70, and 25

ns

Example solution shown on next page: minor variations are OK

ECE574: VHDL and Verilog Modeling and Synthesis 7 12/08/10

Part 2: Open Book (Text book and Notes allowed)

NAME: _

ECE Box:

Question 1 [30 marks]:

A linear feedback shift register (LFSR) is a shift register whose input bit is a linear function

of its previous state

The only linear function of single bits is xor, thus it is a shift register whose input bit is driven by the exclusive-or (xor) of some bits of the overall shift register value

The initial value of the LFSR is called the seed, and because the operation of the register is deterministic, the stream of values produced by the register is completely determined by its current (or previous) state Likewise, because the register has a finite number of possible states, it must eventually enter a repeating cycle However, an LFSR with a well-chosen feedback function can produce a sequence of bits which appears random and which has a very long cycle

Applications of LFSRs include generating pseudo-random numbers, pseudo-noise sequences, fast digital counters, and whitening sequences Both hardware and software implementations

of LFSRs are common

The bit positions that affect the next state are called the taps In the diagram the taps are [16,14,13,11] The rightmost bit of the LFSR is called the output bit The taps are XOR'd sequentially with the output bit and then fed back into the leftmost bit The sequence of bits

in the rightmost position is called the output stream

The state ACE1 hex shown will be followed by 5670 hex

Design a synthesizable module to implement the LFSR in the diagram

Assume it is driven by a positive edge triggered clk

Assume it has an asynchronous reset to load it with the initial seed value ACE1 hex

The output should be connected to the output of the 16th register

combination is entered then the state machine should go back to the first state after four

switches are pressed

If the correct 4 switch sequence is entered then the lock output should go high ‘1’ to open the safe for two seconds then back to the first state

Assume you have a one second system clock

Assume only one switch can be pressed at any time and every second a new switch is pressed Assume there is an asynchronous reset to start the controller in a first state

• Draw a state diagram of the state machine

Write a module description (that can be synthesized) of this state machine

Question 3 [35 marks]: Write a Verilog test bench to test the state machine from question 2

as follows:

Assume the numbers

o 0100

o 0001

o 1000

o 0010

are in a text file on four lines This represents the switches being pressed in the

sequence B, D, A, C

Use this text file to form the basis for your test bench to test the operation of your safe

controller You should verify the lock output opens after the 4 switch sequence and is

closed at other times

The test bench should send appropriate messages to the simulator console to show

what state it is in and to show what the expected and actual values for the lock output

are for each state