PRASHER Intel Corporation Chandler, Arizona 13.1 Introduction 13.1.1 Cooling requirements History Present and future 13.1.2 Thermal packaging goals Preventing catastrophic failure Achiev
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Antohe, B V., Lage, J L., Price, D C., and Weber, R M (1997) Experimental Determination
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Bejan, A (1988) Advanced Engineering Thermodynamics, Wiley, New York.
Coleman, H W., and Steel, W G (1989) Experimental Uncertainty Analysis for Engineers,
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Dally, J W., Riley, W F., and McConnell, K G (1993) Instrumentation for Engineering
Measurements, 2nd ed., Wiley, New York.
Davis, P A., Olague, N E., and Goodrich, M T (1992) Application of a Validation Strategy
to Darcy’s Experiment, Adv Water Resources, 15, 175–180
Figliola, R S., and Beasley, D E (1995) Theory and Design for Mechanical Measurements,
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Holman, J P (2001) Experimental Methods for Engineers, 7th ed., McGraw-Hill, New York.
Kline, S J., and McClintock, F A (1953) Uncertainty in Single Sample Experiments, Mech.
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Lage, J L., Antohe, B V., and Nield, D A (1997) Two Types of Nonlinear Pressure-Drop
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Moffat, R J (1982) Contributions to the Theory of Single-Sample Uncertainty Analysis, J.
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Moffat, R J (1990) Some Experimental Methods for Heat Transfer Studies, Exp Therm Fluid
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Wheeler, A J., and Ganji, A R (1996) Introduction to Engineering Experimentation, Prentice
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CHAPTER 13 Heat Transfer in Electronic Equipment
AVRAM BAR-COHEN
Department of Mechanical Engineering University of Minnesota
Minneapolis, Minnesota
ABHAYA WATWE and RAVI S PRASHER
Intel Corporation Chandler, Arizona
13.1 Introduction 13.1.1 Cooling requirements History
Present and future 13.1.2 Thermal packaging goals Preventing catastrophic failure Achieving reliable operations Life-cycle costs
13.1.3 Packaging levels 13.2 Thermal resistances 13.2.1 Introduction 13.2.2 Basic heat transfer modes Conduction
Convection Radiation 13.2.3 Chip package resistance Internal resistance External resistance Flow resistance Total resistance: single-chip packages 13.3 Length-scale effects on thermophysical properties 13.3.1 Spreading resistance
13.3.2 Heat flow across solid interfaces Thermal contact resistance Thermal boundary resistance Interstitial materials Thermal conductivity of particle-laden systems Effect of filler concentration on mechanical strength 13.3.3 First-order transient effects
Lumped heat capacity
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Thermal wave propagation Chip package transients 13.3.4 Heat flow in printed circuit boards Anisotropic conductivity
Thermal vias Effect of trace layers 13.4 Convective phenomena in packaging 13.4.1 Printed circuit boards in natural convection 13.4.2 Optimum spacing
13.4.3 Printed circuit boards in forced convection 13.5 Jet impingement cooling
13.5.1 Introduction 13.5.2 Correlation 13.5.3 First-order trends 13.5.4 Figures of merit 13.5.5 General considerations for thermal–fluid design 13.5.6 Impingement on heat sinks
13.6 Natural convection heat sinks 13.6.1 Empirical results 13.7 Phase-change phenomena 13.7.1 Heat pipes and vaporchambers Alternative designs
13.7.2 Immersion cooling 13.8 Thermoelectric coolers 13.9 Chip temperature measurement 13.10 Summary
Nomenclature References
13.1 INTRODUCTION 13.1.1 Cooling Requirements
History Despite the precipitous drop in transistor switching energy that has charac-terized the solid-state semiconductor revolution, the cooling requirements of micro-electronic components have not diminished As the twenty-first century begins, high-performance chip power dissipation exceeds 100 W, some three orders-of-magnitude above the SSI (small-scale integration) chips of the early 1960s, and informed opin-ion suggests that a 150-W chip will become reality within the first decade of the twenty-first century Thermal management is thus one of the key challenges in ad-vanced electronic packaging, and considerable improvement in thermal packaging will be needed to exploit successfully the Moore’s law acceleration in semiconductor technology
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In the early 1960s chip heat removal requirements for the 2- to 3-mm SSI silicon semiconductor devices were typically in the range 0.1 to 0.3 W By the mid-1980s, increased chip transistor counts and functional densities pushed LSI (large-scale integration) ECL (emitter-coupled logic) power dissipation to 5 W for5-mm chips (Bar-Cohen, 1987)
Although historical reliability data for silicon bipolar chips, based largely on military electronic sytems, had established a “traditional” upper limit of 110 to 125°C
on the junction temperature, in the 1980s reliability and performance considerations led to a lower standard, 65 to 85°C, in commercial applications, thus halving the allowable temperature rise of the chip above the ambient 45°C The resulting LSI chip heat fluxes, approaching 25×104W/m2(25 W/cm2), combined with the lowered chip temperatures, necessitated the development of high-performance cooling systems and posed a formidable challenge to the electronic packaging community
Mainframe computers of this era based on high-speed bipolar chips were charac-terized by water-cooled multichip modules, with an effective thermal resistance of
1 to 2 K/W· cm2 (Bar-Cohen, 1987) However, although slower, the lower-power CMOS (complementary metal oxide on silicon) VLSI (very large scale integration) chips, with powerdissipation often less than 1 W across a 10-mm chip, were becom-ing the technology of choice for workstations and desktop computers These chips, re-quiring effective thermal resistances some 25 times lower than the mainframe bipolar chips, could often be cooled passively (conduction spreading and air natural convec-tion) and rarely required more than modest forced-convection and simple air-cooled extended surface heat sinks
In the mid-1990s, the thirst of the marketplace for greater integrated-circuit speed and functionality, along with growing on-chip heating which accompanied lower operating voltages and higher currents, pushed CMOS microprocessor chip power dissipation to the range 15 to 30 W and forced the use of ever more aggressive air-cooling technology As the end of the decade approached, chips in high-performance workstations were routinely dissipating in excess of 75 W, with heat fluxes that were once again approaching 25× 104W/m2 To facilitate continued aircooling of these higher-power chips and in recognition of the vast reliability improvements in silicon devices, the allowable junction temperatures in the final years of the 1990s rose to values close to 100°C in desktop computers and workstations
Present and Future To understand the future trends in the cooling requirements for microelectronic components, it is helpful to examine the consensus emerging from industrywide “road-mapping” efforts, including the Semiconductor Industry
Association’s (SIA’s) National Technology Roadmap for Semiconductors: Technol-ogy Needs (1997) and National Electronics Manufacturing Institute’s (NEMI’s) Tech-nology Roadmap (1996) These trends are summarized in Table 13.1, where the
salient thermal and related parameters, starting with the 1999 state of the art and ex-tending to 2012, are classified by application categories In the low-cost or commod-ity product category, including disk drives, displays, microcontrollers, boom-boxes, and video cassette recorders, power dissipation is very modest, and only incidental cooling expenditures can be tolerated In this category, today and for the foreseeable
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future, thermal management rarely involves more than reliance on buoyancy-induced natural circulation of air, augmented perhaps by passive heat spreading Operation
at an elevated chip temperature of typically 125°C in an anticipated internal ambi-ent temperature of 55°C, resulting in a driving force of 70°C, provides some com-pensation for the relatively high chip-to-air thermal resistance associated with this approach
Similar constraints severely limit the options for today’s battery-operated hand-held products, including PDAs (personal digital assistants) and cellular phones, where clever use of heat spreaders generally makes it possible to maintain the 1 to 2 W inte-grated circuits (ICs) at temperatures at or below 115°C Significantly, in this category, thermal management capability is today in rough equilibrium with the battery power available for extended operation, but an anticipated doubling of the available battery power by the late years of the current decade may well necessitate more aggressive approaches
Natural convection cooling is also generally the rule for memory devices But when many such DRAMs and/orSRAMs, each typically dissipating 1 W, are stacked together or densely packed on a printed circuit board, forced convection is used to keep these devices from exceeding their allowable temperature of approximately 100°C Such techniques can be expected to be more broadly applied for thermal management of future memory devices, dissipating, perhaps, so much as 2.5 W, by the end of the decade
During the 1990s, the automotive category claimed the “harsh environment” man-tle previously worn by “mil-spec” components The elevated ambient temperatures under the hood and elsewhere in a vehicle, reaching as high as 165°C, make it neces-sary for automotive ICs, dissipating 10 to 15 W, to operate reliably at temperatures as high as 175°C This category also includes equipment used in mining and resource ex-ploration and in the upper spectrum of military applications The relatively small chip size of 53 mm2in 1999, projected to grow to just 77 mm2by 2012, and an anticipated constant power dissipation of 14 W, result in chip heat fluxes that are comparable to those encountered in the most demanding, high-performance category
However, due to the small allowable temperature difference for these components, the automotive category poses the most demanding of electronic cooling require-ments While a wide variety of heat-spreading and air-cooling strategies, for elevated chip temperature operation, have been implemented successfully in this product cat-egory, development efforts are also addressing conventional temperature operation based on the use of refrigerated cold plates Throughout the 1990s, heat-sink-assisted air cooling was the primary thermal packaging approach for the cost/performance cat-egory, which included both desktop and notebook computers Thermal management
of the microprocessors used in desktop computers often relied on clip-attached or adhesively bonded extruded aluminum heat sinks, cooled by remotely located fans
But as the chip power reached 50 W by the end of the decade, thermal packaging for this product category required progressively more refined designs as well as lower-thermal-resistance interface materials Returning to Table 13.1, it may be seen that cost/performance chip heat fluxes are forecasted to peak by 2006, at approximately 40% highervalues than in 1999
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Table 13.1 Thermal Characteristics of Current and Future Semiconductor Packages
Yearof Commercialization
Commodity
Handheld
Memory (DRAM)
Cost performance
High performance
Automotive
Source: Data from NEMI (1996) and SIA (1997).
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In an attempt to minimize the performance gap between notebook and desktop computers, fan-cooled heat sinks did begin to appear in notebook computers toward the end of the 1990s However, throughout much of this decade, battery power limi-tations made it necessary to harness naturally convecting air, circulating past low-fin heat sinks and heat pipes, as well as metal cases heated by spreading, to provide the requisite cooling for the 3- to 5-W chips In the coming years, advanced notebook computers using modified cost/performance chips will pose extreme challenges to the thermal management community
In the late 1990s, under the influence of market forces, thermal management of nearly all the products in the high-performance category devolved to the aggressive use of air cooling, exploiting technology that was a natural outgrowth of the air-cooled multichip modules of the 1980s By the end of the decade, a renaissance in thermal packaging produced heat sinks for high-end commercial workstations and servers that were routinely dissipating 60 to 70 W with chip heat fluxes of some 26
W/cm2 As may be seen in Table 13.1, the packaging community consensus suggests that early in the second decade of the twenty-first century, power dissipation will rise
to 175 W for chips operating at some 3 GHz However, it is anticipated that chip area, growing from 3.8 cm2to some 7.5 cm2, will keep pace with chip powerdissipation
in the coming years, yielding chip heat fluxes that increase only marginally above the present values to approximately 30 W/cm2by 2006, before beginning a slow decline
in lateryears
13.1.2 Thermal Packaging Goals
Preventing Catastrophic Failure In today’s high-performance microelectronic systems, catastrophic failure may be associated with an immediate and total loss
of electronic function and package integrity, or drastic, though reversible, deterio-ration in performance The prevention of permanent as well as intermittent catas-trophic failure is the primary and foremost goal of electronics thermal management and often requires the elimination of large temperature excursions Excessive tem-peratures, inducing large thermomechanical stresses, may lead to excessive strain and/orstress levels in the silicon, delamination of the die attach and heat sink or spreader bond layer, as well as broken wire, solder, or gold bonds Furthermore, ele-vated temperatures, which exceed the design specification of the package, may result
in melting, vaporization, or even combustion of low-temperature packaging mate-rials Alternatively, unanticipated chip and package temperature variations beyond the specified tolerance may lead to shifts in semiconductorbehavior(e.g., CMOS switching frequency) or that of adjacent photonic (e.g., emitted wavelength, conver-sion efficiency) or microwave components (e.g., phase shift), as well as to structural misalignment and signal delays that undermine the ability of the package to deliver the requisite performance A detailed understanding of the catastrophic vulnerability
of the specified component(s) provides the basis for establishing the thermal manage-ment strategy for a particular package or product, including selection of the appropri-ate fluid, heat transfer mode, and inlet coolant temperature required to meet design specifications
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Achieving Reliable Operations Following selection of the thermal packaging strategy, attention can be turned to meeting the desired level of reliability and the associated target failure rates of each component and subassembly Individual solid-state electronic devices are inherently reliable However, because a single microelec-tronic chip may include as many as 15 million transistors and 600 leads, and because many tens of such components may be used in a single system, achieving failure-free operation over the useful life of a product is a formidable challenge The suppression
of thermally induced failures often requires adherence to strict limits on the temper-ature rise or fall relative to the ambient tempertemper-ature and the minimization of spatial and temporal temperature variations in a package
The reliability of a system is the probability that the system will meet the required specifications for a given period of time As an individual electronic component contains no moving parts, it can often perform reliably for many years, especially when operating at or near room temperature In practice, integrated circuits operate
at temperatures substantially above ambient, and unfortunately, most electronic com-ponents are prone to failure from prolonged exposure to these elevated temperatures
This accelerated failure rate results from the interplay of numerous factors, includ-ing the consequences of thermal strain and stress in the bondinclud-ing and encapsulation materials, parasitic chemical reactions, dopant diffusion, and dielectric breakdown (Pecht et al., 1992) Although accurate failure rate predictions defy simple correla-tions, under some conditions a modest 10 to 20°C increase in chip temperature can double the component failure rate Consequently, for many package categories, tem-perature is the strongest contributor to the loss of reliability In such systems, thermal management is critical to success of the electronic system
Life-Cycle Costs In the final stages of thermal design of an electronic system, the reliability, availability, and maintainability of the proposed thermal control alterna-tives must be evaluated and used to guide the final technology and equipment choice
It is the role of the packaging engineer to assure that the enhanced reliability of the components, resulting from lower operating temperature as well as the minimization
of spatial and temporal temperature variations, is sufficient to compensate for the ad-ditional life-cycle cost and inherent failure rate of fans, pumps, heat pipes, interface materials, and other elements of the cooling system Successful thermal packaging requires a judicious and insightful combination of materials and heat transfer mech-anisms to stabilize the component temperatures at an acceptable level
13.1.3 Packaging Levels
To initiate the development of a thermal design for a specified electronic product, it is first necessary to define the relevant packaging level (see Fig 13.1) The commonly accepted categorization places the chip package, which houses and protects the chip,
at the bottom of the packaging hierarchy (level 1) The printed circuit board (PCB), which provides the means for chip-to-chip communication, constitutes level 2, while the backplane or motherboard, which interconnects the printed circuit boards, is termed level 3 packaging The box, rack, or cabinet, that houses the entire system
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Figure 13.1 Electronic packaging levels
is generally referred to as level 4 The primary thermal transport mechanisms and
commonly used heat removal techniques vary substantially from one packaging level
to the next as the scale of the thermal transport phenomena shifts from the microscale (or even nanoscale in future years) at level 1, to the mesoscale at level 2, and on to the macroscale in packaging levels 3 and 4
Level 1 thermal packaging is concerned primarily with conducting heat from the chip to the package surface and then into the printed circuit board At this pack-aging level, reduction in thermal resistance between the silicon die and the outer surface of the package is the most effective way to lower the chip temperature As shown in Table 13.2, a variety of passive cooling techniques are available to reduce the thermal resistance For example, improved thermal performance can be obtained
by using die-attach adhesives, with diamond, silver, orotherhigh-conductivity filler material, thermal greases, and phase-change materials, which soften at the operat-ing temperature to conform better to the surface of the chip Alternatively, attachoperat-ing metal-plate heat spreaders to the chip, and using thermally enhanced molding com-pounds and embedded heat slugs [for plastic ball grid array (PBGA) and lead frame packages], can also lead to beneficial results It is also quite common to attach heat sinks to the surface of a package to create additional surface area for heat removal by natural and/or forced convection In very high power applications, it may be neces-sary to cool the chip directly by attachment to a heat pipe, by direct attachment of a
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TABLE 13.2 Thermal Management Techniques for Distinct Packaging Levels
Packaging Level Passive Cooling Techniques Active Cooling Techniques Level 1: chip package High-conductivity adhesive Fans
Greases Air jet impingement Phase-change materials Dielectric liquid High-conductivity molding
compound
Thermoelectric cooler
Heat spreader Heat slug Heat sinks Dielectric liquid immersion Heat pipes
Level 2: PCB Thick powerand ground
planes
Fans Ducted air Insulated metal substrates Dielectric liquids Heat pipes Cold plates Natural convection
Levels 3 + 4: module and rack
Natural convection Ducted air Heat pipes Air-handling system
Cold plates Refrigeration systems
heat sink, by impingement of high-velocity airjets, orby immersion in a dielectric liquid
Heat removal at level 2 typically occurs both by conduction in the printed circuit board and by convection to the ambient air Use of printed circuit boards with thick, high-conductivity powerand ground planes and/orembedded heat pipes provides improved thermal spreading at this level of packaging Use of electrically insulated metal substrates can also be considered Often, heat sinks are attached to the back surface of the printed circuit board In many airborne systems or in systems designed for very harsh environments, convective cooling of the component is not possible;
instead, heat must be conducted to the edge of the printed circuit board Attachment
of a heat sink ora heat exchangerat this edge then serves to remove the heat dissipated
by the components populating the printed circuit board or substrate
As might be surmised from the frequent use of the term computer on a chip
or computer in a package, many of today’s electronic systems can be packaged
adequately at level 1 or 2 Heat sinks or finned surfaces protruding into the airstream are often used at levels 1 and 2 to aid in the transfer of heat to the ambient air
When levels 3 and 4 are present, thermal packaging generally invoves the use of active thermal control measures such as air-handling systems, refrigeration systems, orwaterpipes, heat exchangers, and pumps Often, however, it is possible to cool the module and/or rack by relying on natural circulation of the heated air