Handbook of algorithms for physical design automation part 64 docx

W., A solution to line routing problems on the continuous plane, Proceedings of the Design Automation Workshop, NY, pp.. and Marek-Sadowska, M., Congestion minimization during placement

Trang 1

Alpert/Handbook of Algorithms for Physical Design Automation AU7242_C030 Finals Page 612 19-9-2008 #15

In general, the accuracy of placement-based metrics decreases as the level of abstraction of the netlist increases Indeed, almost all the metrics proposed for use during logic synthesis to date are graph theoretic in nature With the problem of routing congestion getting worse because of the scaling

of design sizes and process technologies, a comprehensive congestion management strategy must target congestion through the entire design flow, relying on the appropriate congestion estimators at each stage

The interested reader can find further details on all the metrics discussed in this chapter in the corresponding papers, or in Ref [SSS07]

REFERENCES

[CZY+99] Chen, H -M., Zhou, H., Young, F Y., Wong, D F., Yang, H H., and Sherwani, N.,

Inte-grated floorplanning and interconnect planning, Proceedings of the International Conference on Computer-Aided Design, San Jose, CA, pp 354–357, 1999.

[Che94] Cheng, C -L E., RISA: Accurate and efficient placement routability modeling, Proceedings of the

International Conference on Computer-Aided Design, San Jose, CA, pp 690–695, 1994.

[CL00] Cong J and Lim, S., Edge separability based circuit clustering with application to circuit

partition-ing, Proceedings of the Asia and South Pacific Design Automation Conference, Yokohama, Japan,

pp 429–434, 2000

[Dai01] Dai, W., Hierarchial physical design methodology for multi-million gate chips, Proceedings of the

International Symposium on Physical Design, Sonoma, CA, pp 179–181, 2001.

[HNR68] Hart, P E., Nilsson, N J., and Raphael, B., A formal basis for the heuristic determination of minimum

cost paths, IEEE Transactions on System Science and Cybernetics SSC-4, pp 100–107, 1968.

[HB97] Hauck, S and Borriello, G., An evaluation of bipartitioning techniques, IEEE Transactions

on Computer-Aided Design of Integrated Circuits and Systems 16(8): 849–866, August 1997.

(ARVLSI 1995)

[Hig69] Hightower, D W., A solution to line routing problems on the continuous plane, Proceedings of the

Design Automation Workshop, NY, pp 1–24, 1969.

[HM02] Hu, B and Marek-Sadowska, M., Congestion minimization during placement without estimation,

Proceedings of the International Conference on Computer-Aided Design, San Jose, CA, pp 739–

745, 2002

[KR05] Kahng, A B and Reda, S., Intrinsic shortest path length: A new, accurate a priori wirelength

estimator, Proceedings of the International Conference on Computer-Aided Design, San Jose, CA,

pp 173–180, 2005

[KX03] Kahng, A B and Xu, X., Accurate pseudo-constructive wirelength and congestion estimation,

Proceedings of the International Workshop on System-Level Interconnect Prediction, Monterey,

CA, pp 61–68, 2003

[KK03] Kravets, V and Kudva, P., Understanding metrics in logic synthesis for routability enhancement,

Proceedings of the International Workshop on System-Level Interconnect Prediction, Monterey,

CA, pp 3–5, 2003

[KSD03] Kudva, P., Sullivan, A., and Dougherty, W., Measurements for structural logic synthesis

optimiza-tions, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 22(6):

665–674, June 2003 (ICCAD 2002)

[LR71] Landman, B S and Russo, R L., On a pin versus block relationship for partitions of logic graphs,

IEEE Transactions on Computers C-20(12): 1469–1479, December 1971.

[LAQ+07] Li, Z., Alpert, C J., Quay, S T., Sapatnekar, S., and Shi, W., Probabilistic congestion prediction

with partial blockages, Proceedings of the International Symposium on Quality Electronic Design,

San Jose, CA, pp 841–846, 2007

[LJC03] Lin, J., Jagannathan, A., and Cong, J., Placement-driven technology mapping for LUT-based

FPGAs, Proceedings of the International Symposium on Field Programmable Gate Arrays,

Monterey, CA, pp 121–126, 2003

[LM05] Liu, Q and Marek-Sadowska, M., Wire length prediction-based technology mapping and fanout

optimization, Proceedings of the International Symposium on Physical Design, San Francisco, CA,

pp 145–151, 2005

Trang 2

[LTK+02] Lou, J., Thakur, S., Krishnamoorthy, S., and Sheng, H S., Estimating routing congestion using

probabilistic analysis, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 21(1): pp 32–41, January 2002 (ISPD 2001).

[PC06] Pan, M and Chu, C., FastRoute: A step to integrate global routing into placement, Proceedings of

the International Conference on Computer-Aided Design, San Jose, CA, pp 464–471, 2006.

[PPS03] Pandini, D., Pileggi, L T., and Strojwas, A J., Global and local congestion optimization in

technology mapping, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 22(4): 498–505, April 2003 (ISPD 2002).

[PP89] Pedram, M and Preas, B., Interconnection length estimation for optimized standard cell

lay-outs, Proceedings of the International Conference on Computer-Aided Design, Santa Clara, CA,

pp 390–393, 1989

[SSS07] Saxena, P., Shelar, R S., and Sapatnekar, S S., Routing Congestion in VLSI Circuits: Estimation

and Optimization, New York: Springer, 2007.

[SPK03] Selvakkumaran, N., Parakh, P N., and Karypis, G., Perimeter-degree: A priori metric for directly

measuring and homogenizing interconnection complexity in multi-level placement, Proceedings

of the International Workshop on System-level Interconnect Prediction, Monterey, CA, pp 53–59,

2003

[SY05] Sham, C and Young, E F Y., Congestion prediction in early stages, Proceedings of the

Interna-tional Workshop on System-level Interconnect Prediction, San Francisco, CA, pp 91–98, 2005.

[SSS+05] Shelar, R., Sapatnekar, S., Saxena, P., and Wang, X., A predictive distributed congestion metric

with application to technology mapping, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 24(5): 696–710, May 2005 (ISPD 2004).

[SSS06] Shelar, R., Saxena, P., and Sapatnekar, S., Technology mapping algorithm targeting routing

congestion under delay constraints, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 25(4): 625–636, April 2006 (ISPD 2005).

[SK93] Shin, H and Kim, C., A simple yet effective technique for partitioning, IEEE Transactions on Very

Large Scale Integration Systems 1(3): 380–386, September 1993.

[SK01] Stok, L and Kutzschebauch, T., Congestion aware layout driven logic synthesis, Proceedings of

the International Conference on Computer-Aided Design, San Jose, CA, pp 216–223, 2001.

[VP95] Vaishnav, H and Pedram, M., Minimizing the routing cost during logic extraction, Proceedings of

the Design Automation Conference, San Francisco, CA, pp 70–75, 1995.

[WBG04] Westra, J., Bartels, C., and Groeneveld, P., Probabilistic congestion prediction, Proceedings of the

International Symposium on Physical Design, Phoenix, AZ, pp 204–209, 2004.

[WBG05] Westra, J., Bartels, C., and Groeneveld, P., Is probabilistic congestion estimation worthwhile?,

Proceedings of the International Workshop on System-Level Interconnect Prediction, San Francisco,

CA, pp 99–106, 2005

Trang 3

Trang 4

Jeffrey S Salowe

CONTENTS

31.1 Overview 615

31.1.1 Definition 615

31.2 Routing Formulation 616

31.2.1 Lagrangian Relaxation 616

31.2.2 Steiner Tree Construction 617

31.2.3 A∗Maze Search 617

31.2.4 Cost Functions and Constraints 618

31.3 Rip-Up-and-Reroute Schemas 618

31.3.1 Progressive Rerouting Schema 619

31.3.1.1 Issues 620

31.3.2 Iterative Improvement Schema 621

31.3.2.1 Issues 622

31.4 Rip-Up-and-Reroute Strategies 624

31.5 History 624

31.6 Engineering Practicality 625

References 625

31.1 OVERVIEW

In this chapter, we explain some of the intricacies of rip-up and reroute by focusing on one common routing formulation With respect to this routing formulation, we examine two rip-up-and-reroute schemas, which are basic techniques After examining the schemas and assessing their strengths and weaknesses, we show how strategies that combine the different schemas can be constructed The strategies attempt to counter the weaknesses of the schemas themselves These concepts are illustrated with some of the seminal papers in the field Rip-up and reroute has been successfully applied during all phases of routing, including global routing, detailed routing, track assignment, and layer assignment

31.1.1 DEFINITION

Rip-up and reroute is an iterative technique whose basic step is to remove one or more connections and replace them with new connections This idea can be applied in many ways For instance, suppose

as depicted in Figure 31.1a that connection r1 has been added, but connection r2 cannot be added without a violation because connection r1 uses a resource that r2 needs One can remove all or part

of r1, add connection r2, and then make a new connection for r1 as depicted in Figure 31.1b through

d, respectively Another possibility is to shift connection r1 away from the critical resource, and then to add r2 Yet another possibility is to place a tax, or congestion cost, on the common resource,

hoping that connection r1 or connection r2 will avoid the taxed region

615

Trang 5

(d) (c)

A

r1

A

r1

FIGURE 31.1 (a) Wire r1 blocks pin access to A A is on metal 1, A is surrounded by blockages (not depicted),

and r1 is on metal 2 (b) A portion of wire r1 is removed to allow access to A (c) Wire r2 on metal 3 can access pin A using a via stack from metal 3 to metal 1 (d) Wire r1 is rerouted on metal 2.

31.2 ROUTING FORMULATION

To illustrate rip-up and reroute, we simplify the routing problem using Lagrangian relaxation, ulti-mately transforming the problem into successive shortest-path problems This basic framework was outlined by Linsker (1984) Once the basic framework is established, we examine different rerouting strategies, pointing out their strengths and weaknesses

31.2.1 LAGRANGIANRELAXATION

A routing problem is an optimization problem of the form

minimize f (X)

subject to g i (X) ≤ 0, 1 ≤ i ≤ n

We separate the constraints into two classes, network constraints n i (X) ≤ 0, 1 ≤ i ≤ N, and design

constraints d i (X) ≤ 0, 1 ≤ i ≤ D.

minimize f (X)

subject to n i (X) ≤ 0, 1 ≤ i ≤ N

d i (X) ≤ 0, 1 ≤ i ≤ D

Network constraints state that the network topology must satisfy certain requirements, such as the net-work must connect all the pins without forming loops Except for special nets, the netnet-work constraints state that a Steiner tree implements each net Design constraints state that the network is designed

in a legal way, such as no two routes occupy the same spot, or no two shapes are too close together The global routing design constraints state that no area contains too many routing shapes If an area contains too many global routing shapes, it may not be possible to detail route the area without violating the detail routing design constraints

Trang 6

A routing problem is feasible if there is any solution that satisfies the constraints For any interesting routing problem, it is NP-hard to determine if there is a feasible solution

Chip designers, however, are not interested in abstract complexity issues: they typically try to make chips that have feasible routing (based on earlier experience) and then adjust the constraints to achieve their objectives The typical input is therefore likely to have a feasible solution Furthermore, some design constraints are soft, such as those given to a global router It may be possible to overcongest a few areas and still solve the resulting detailed routing problem This means that even if the result is infeasible for the original problem, it may still be useful

A general and powerful technique to solve hard optimizations problems is to apply Lagrangian relaxation (Ahuja et al 1993) In Lagrangian relaxation, one or more constraints are added to the objective function using Lagrangian multipliersλ i Under appropriate conditions, Lagrangian relax-ation can be used to solve optimizrelax-ation problems exactly; conditions for convergence are discussed in Ahuja et al (1993) In other cases, however, Lagrangian relaxation is used to simplify complicating constraints Routing falls into the second category: one applies Lagrangian multipliers to the design constraints, resulting in an optimization problem:

minimize f (X) + λ∗

subject to n i (X) ≤ 0

λ i≥ 0

In the Lagrangian relaxation of a routing problem, only the network constraints need to be satisfied This means that any set of Steiner trees is a feasible solution, which is a considerable simplification The design constraints are “taxed” by the Lagrangian multiplier The penalty for violating a design constraint is proportional to the Lagrangian tax

Global routing problems have some soft constraints, so the Lagrangian relaxation technique is natural Detailed routing problems can be phrased in exactly the same way, but the Lagrangian taxes are high because a violated design constraint may cause a chip to fail Sometimes, though, there are soft constraints in detailed routing, where a violation is unwelcome but not prohibited An example

is a wide spacing rule to minimize cross talk that can be violated in a congested region

31.2.2 STEINERTREECONSTRUCTION

A Steiner minimal tree is a shortest connection of a set of points Finding a Steiner minimal tree in the plane or in a graph is NP-hard, even if there are no obstructions To make matters even more complicated, there are usually several routing layers, routing obstructions, and congestion

Lagrangian relaxation simplifies the routing problem into simultaneous Steiner tree construction

of a set of nets Although the Steiner tree problem is itself hard, one may not need the absolutely shortest tree, and there are special cases that are solvable in polynomial time For instance, a Steiner minimal tree for a two-pin net is a shortest-path problem, which can be found efficiently Furthermore,

a properly embedded minimum spanning tree is an excellent heuristic for a Steiner minimal tree (Hwang et al 1992) The basic step in Prim’s minimum spanning tree is to find a vertex that is closest to the tree It is therefore reasonable to assume that the shortest-path problem is an important component in a routing problem

31.2.3 A∗MAZESEARCH

The Lee–Moore algorithm is described in Section 23.5 There are one or more sources and one or more targets; initially, the weight of a source is zero and the weight of a target is infinite Vertices

are considered in order of weight from the source; when a vertex u is visited, the graph edges (u, v)

incident to u are examined to see if they improve the smallest weight to v The search stops when a

target is to be considered

One can decrease the number of vertices visited in the search if one has a conservative estimate

of the distance from each node to the targets This value, the lower bound, reflects how close each

Trang 7

FIGURE 31.2 (a) Blockages on a routing grid graph and (b) pruned routing grid graph.

vertex is to a target In the A∗technique, invented by Nilsson (Hart et al 1968), the weight of the

path to u plus the estimated distance to a closest target form a new measure, the estimated weight of

a shortest path using the vertex u Instead of considering vertices in order of weight from the source,

A∗considers them in order of estimated shortest-path weight

The A∗technique can speed up the path search enormously if the estimated path length is close

to the actual path length Unfortunately, A∗becomes less effective when the lower bound is overly conservative This happens when obstructions are not accounted for in the lower bound, and it happens when congestion is present but not reflected in the lower bound Nevertheless, A∗has proven to be

of great practical use In our formulation, the general routing problem is transformed into a set of path problems in a weighted graph that are solved using A∗maze search

31.2.4 COSTFUNCTIONS ANDCONSTRAINTS

Using Lagrangian relaxation, the routing problem becomes a problem of finding shortest paths in

a weighted graph because the Lagrangian taxes are a cost function on the vertices and edges An alternative to a very high cost function on a vertex or edge is to remove that vertex or edge from the graph For instance, spacing rules in a gridded detailed routing problem can be handled by removing grid points that are in violation with existing objects This places a constraint on the graph, and it ensures that the vertex or edge is not used; it may speed up a graph search because the expensive edges or vertices need not be visited (Figure 31.2) The main factor in deciding how to represent the constraint is the complexity of the resulting subproblem If one uses A∗in a weighted graph, the removal of a graph vertex or edge does not substantially alter the strategy, though it may affect the running time

It is also possible to further constrain the path; for instance, one can prune paths that do not satisfy certain criteria, such as the number of bends in the path (this is done, for instance, in Shin and Sangiovanni-Vincentelli [1987]) Note that some pruning options are not compatible with an

A∗search

31.3 RIP-UP-AND-REROUTE SCHEMAS

Now that the general formulation is in place, we can examine different rip-up-and-reroute schemas

A schema reflects a basic methodology, though the actual implementation details may differ from one author to another Schemas can be separated based on

1 Identification of rip-up-and-reroute subproblems

2 Selection of routes that are removed when a subproblem is considered

3 Method used to solve these subproblems

Trang 8

We describe two important schemas, the progressive rerouting schema and the iterative improvement schema They appear in two key papers in the field, and their concepts have interesting parallels in network optimization They form a foundation for powerful routing strategies

31.3.1 PROGRESSIVEREROUTINGSCHEMA

An important rip-up-and-reroute schema can be illustrated with the global routing algorithm invented

by R Nair (1987) In Nair’s schema, each net forms a subproblem, and only that net is removed when the subproblem is considered

1 For pass =1 tok

2 For each netn

a Remover

b Rerouter

Nair tessellated the chip using vertical and horizontal lines into a two-dimensional “gcell grid” as described in Section 23.2.2 A gcell is defined as a smallest rectangle formed by the horizontal and vertical lines Nair’s routing graph is the dual of the grid graph: each gcell is a vertex, and an edge

is present between each pair of adjacent gcells

Nair placed a constraint on each line segment in the grid graph that reflected the number of wires that could cross that line segment These represent the design constraints in that area Using Lagrangian relaxation, the constraints became costs on the routing graph edges

Two-pin nets are routed using an A∗search Multipin nets are routed by successive A∗searches, where the source consists of all gcells that intersect the partially constructed net, and the targets are all pins that are not yet connected in the net

Nair’s key contribution was the overall routing strategy In the first pass, each net is routed subject to the congestion costs incurred from the nets already visited In each subsequent pass, a net

is removed and completely rerouted Note that after the first pass, each net will see the congestion from all the other nets

Nair justified his method, progressive rerouting, with the intuition that the second pass is better informed about congestion than the first pass because the second pass sees all the congestion, while the first pass only sees what was routed so far He discovered that the overall solution cost generated

by the rerouting process converged to equilibrium after several passes; in his case, he stated that fewer than five passes sufficed

Although it was not suggested in Nair’s paper, his algorithm can be understood in the context

of noncooperative games In a noncooperative game, each “agent” acts selfishly on its own behalf, without regard to the effect on the other agents An important notion in the theory of noncooperative games is the concept of a Nash equilibrium In a Nash equilibrium, no agent can change its behavior

to improve its own state In time, noncooperative games converge to a Nash equilibrium It is known, however, that a Nash equilibrium may not be a global optimum

Progressive routing can be seen to be a noncooperative game among the different nets Each net

is routed in a greedy fashion to minimize its own latency Progressive rerouting bears a remarkable similarity to the problem of making traffic assignments Recent results in traffic assignment theory shed some light on the efficacy of Nair’s technique The ratio of the cost of a Nash equilibrium to the overall minimum cost is called the price of anarchy Roughgarden and Tardos (2002) showed that for single commodity flows where the latency function is a linear function of the congestion, any Nash equilibrium has latency at most 4/3 times the minimum possible total latency Global routing, on the other hand, is a multicommodity flow where the commodity cannot be split; for general multicommodity flows, the price of anarchy can be exponential in the polynomial degree of the latency function (Lin et al 2005)

Trang 9

It is not clear that these negative results are immediately applicable to global routing Global routing problems are often well behaved; designers are interested in making chips, not confounding routers Perhaps one can show a positive result on the price of anarchy of a well-behaved global routing problem

Nair’s algorithm also has an interesting parallel to the multicommodity flow approximation tech-nique described in Chapter 32 (Albrecht 2001) The multicommodity flow approximation techtech-nique proceeds in a series of passes In each pass, a Steiner minimal tree is found for each net with respect

to a weighted graph The graph weights are successively modified due to the placement of the trees

At the end, a rounding technique is used to select the actual implementation of the net This can

be seen as identical to the structure of Nair’s algorithm; the main difference is in the choice of the graph weights and in the selection of the Steiner tree implementation In Nair’s approach, there is exactly one Steiner tree representation Steiner trees from prior passes are forgotten, except by how they affect the graph weights

31.3.1.1 Issues

The strength of progressive rerouting is simplicity of design The basic component is A∗search; it is repeated over several passes The schema converges rapidly to a reasonable equilibrium state (Nair 1987) However, it has several weaknesses, some of which are given below

31.3.1.1.1 Detouring

The key problem with successive rerouting is detouring This is where the length of the routed connection is much longer than the length of a connection if congestion is not considered The price

of anarchy refers to the total path length; a single connection, however, can have an arbitrarily long detour This is particularly undesirable when timing issues are considered A net with a weak driver cannot be detoured, so nets on timing-critical paths must be carefully constructed

31.3.1.1.2 Initialization

A second issue is establishing a good starting point At the time of the first pass, no nets are routed,

so these initial nets receive preferential treatment The nets routed at the end of the first pass will see the congestion of the preceding nets, and they may detour unnecessarily as a result Hadsell and Madden (2003) suggest that this initial routing phase can be seeded with a congestion estimation The congestion estimation affects the cost function by applying a tax to high-demand areas

31.3.1.1.3 Net Ordering

Refer to Figure 31.3 Assume that two wires each need to pass through one of two bottlenecks Wire

a is wide, and wire b is narrow; gap A can accommodate either wire a and wire b but not both, but

gap B can only accommodate wire b If wire b is assigned to gap A, it has no incentive to relinquish its position unless wire a is also assigned to gap A If the cost of putting wire a in gap A is less than the cost of putting wire a in gap B, wire b prevents an optimal assignment of wires to gaps This issue is typically dealt with using net ordering If the connection containing wire a is routed first, wire a will be placed in gap A rather than gap B because it does not fit in gap B The connection containing wire b will then be assigned to gap B Net ordering is an imperfect attempt to

add centralized control to the progressive rerouting process The task of assigning wires to bottleneck gaps is a packing problem; such a problem is NP-complete, and heuristics with good performance can be sophisticated

31.3.1.1.4 Determining Good Lagrangian Multipliers

Though there are some general techniques to find Lagrangian multipliers (Ahuja et al 1993), ad hoc techniques are often used in practice Users want fast convergence and few detours Also note that A∗ performs better when lower bounds and upper bounds match, so the use of a Lagrangian multiplier when the design is uncongested may slow down the algorithm, even if it is the theoretically correct

Trang 10

(c)

FIGURE 31.3 (a) Bottleneck gaps A and B Thin wire b can fit through either Thick wire a can only fit

through gap A (b) If wire b is routed first, it may take gap A or gap B If thin wire b takes a resource A that thick wire a needs, a cannot fit through (c) If wire a is routed first, it takes gap A Wire b can make it through gap b.

thing to do Several authors have investigated this issue Note that the multipliers may be affected

by how congestion is modeled and by the routing objectives

31.3.1.1.5 Divergence

Worse than detouring is divergence, where the design may be so congested that almost all connections detour In each successive pass, rerouted connections detour even more to avoid congestion, thereby increasing wirelength dramatically and inducing more congestion Although successive rerouting will converge to a Nash equilibrium, there is neither a statement that it must converge in a small number of passes (it diverges during these passes) nor is there a bound on the total wirelength increase per pass Divergence commonly happens when a design is infeasible

31.3.2 ITERATIVEIMPROVEMENTSCHEMA

This is the second major schema illustrated Suppose we have a routing solution that satisfies the network constraints but not the design constraints Suppose we select one violated design constraint and then attempt to resolve it by rip-up and reroute If no additional design constraints are violated, the resulting routing solution is deemed to be superior to the original one and therefore closer to the

Định dạng
Số trang	10
Dung lượng	248,66 KB