In: Proceedings of the International Conference on Computer-Aided Design ICCAD, Seiten 472–475, 1991.. In: Proceedings of the International Conference on Formal Me-thods in Computer-Aide
Trang 1228 HOWDEN, W E.: Theoretical and Empirical Studies of Program Testing In:
Procee-dings of the International Conference on Software Engineering (ICSE), Seiten 305–311,
1978
229 HU, A J.: High-Level vs RTL Combinational Equivalence: An Introduction In:
Pro-ceedings of the International Conference on Computer Design (ICCD), Seiten 274–279,
2007
230 HUANG, C.-Y und K.-T CHENG: Assertion Checking by Combined Word-Level ATPG
and Modular Arithmetic Constraint-Solving Techniques In: Proceedings of the Design Automation Conference (DAC), Seiten 118–123, 2000.
231 IBARRA, O H und S MORAN: Probabilistic Algorithms for Deciding Equivalence of
Straight-Line Programs Journal of the ACM, 30(1):217–228, 1983.
232 IEEE: IEEE Standard Glossary of Software Engineering Terminology. IEEE Std 610.12-1990, 1990
233 IEEE: IEEE Standard VHDL Language Reference Manual IEEE Std 1076-1993, 1993.
234 IEEE: IEEE Standard for Property Specification Language (PSL) IEEE Std 1850, 2005.
235 IEEE: IEEE Standard for SystemVerilog – Unified Hardware Design, Specification, and
Verification Language IEEE Std 1800, 2005.
236 IEEE: IEEE Standard SystemC Language Reference Manual IEEE Std 1666, 2006.
237 http://www.cadence.com/products/fv/design team simulator/
238 http://www.cadence.com/products/fv/formal verifier/
239 ISHIURA, N., H SAWADAund S YAJIMA: Minimization of Binary Decision Diagrams
based on Exchanges of Variables In: Proceedings of the International Conference on Computer-Aided Design (ICCAD), Seiten 472–475, 1991.
240 ITRS: International Technology Roadmap for Semiconductors – System Drivers
Tech-nischer Bericht, ITRS, 2007 http://www.itrs.net/
241 IVANCIˇ C, F., I SHLYAKHTER, A GUPTA, M K GANAI, V KAHLON, C WANG´ und
Z YANG: Model Checking C Programs using F-Soft In: Proceedings of the
Internatio-nal Conference on Computer Design (ICCD), Seiten 297–308, 2005.
242 IVANCIˇ C, F., Z YANG, M K GANAI, A GUPTA´ und P ASHAR: Efficient SAT-Based
Bounded Model Checking for Software Verification Theoretical Computer Science,
404(3):256–274, 2008
243 JACKSON, J R.: Scheduling a Production Line to Minimize Maximum Tardiness Tech-nischer Bericht 43, University of California, Los Angeles, 1955
244 JAIN, H., D KROENINGund E M CLARKE: Verification of SpecC Using Predicate
Abstraction In: Proceedings of the International Conference on Formal Methods and Models for Co-Design (MEMOCODE), Seiten 7–16, 2004.
245 JAIN, J., A NARAYAN, C COELHO, S P KHATRI, A L SANGIOVANNI-VINCEN-TELLI, R K BRAYTON und M FUJITA: Decomposition Techniques for Efficient
ROBDD Construction In: Proceedings of the International Conference on Formal Me-thods in Computer-Aided Design (FMCAD), Seiten 419–434, 1996.
246 JALOTE, P.: Fault Tolerance in Distributed Systems Prentice-Hall, Inc., Upper Saddle River, NJ, U.S.A., 1994
247 JERSAK, M.: Compositional Performance Analysis for Complex Embedded
Applicati-ons Doktorarbeit, Technische Universit¨at Braunschweig, Deutschland, 2005.
248 JONES, N D und S S MUCHNICK: Flow Analysis and Optimization of LISP-like
Structures In: Proceedings of the Symposium on Principles of Programming Languages (POPL), Seiten 244–256, 1979.
249 JOSEPH, M und P PANDYA: Finding Response Times in a Real-Time System The Computer Journal, 29(5):390–395, 1986
Trang 2250 KAHN, G.: The Semantics of a Simple Language for Parallel Programming In:
Procee-dings of the IFIP Congress, Seiten 471–475, Stockholm, Sweden, 1974.
251 KALLA, P., M CIESIELSKI, E BOUTILLONund E MARTIN: High-Level Design
Veri-fication Using Taylor Expansion Diagrams: First Results In: Proceedings of the High-Level Design Validation and Test Workshop (HLDVT), Seiten 13–17, 2002.
252 KATZ, S und D PELED: Verification of Distributed Programs Using Representative
Interleaving Sequences Journal of Distributed Computing, 6(2):107–120, 1992.
253 KEBSCHULL, U., E SCHUBERTund W ROSENSTIEL: Multilevel Logic Synthesis
ba-sed on Functional Decision Diagrams In: Proceedings of the European Conference on Design Automation (ECDA), Seiten 43–47, 1992.
254 KEINERT, J., M STREUBUHR, T SCHLICHTER, J FALK, J GLADIGAU, C HAU-¨ BELT, J TEICHund M MEREDITH: SystemCoDesigner - An Automatic ESL Synthesis
Approach by Design Space Exploration and Behavioral Synthesis for Streaming Appli-cations ACM Transactions on Design Automation of Electronic Systems (TODAES),
14(1):1–23, 2009
255 KELLY, J C und K KEMP: Formal Methods Specification and Verification
Guide-book for Software and Computer Systems, Volume I: Planning and Technology Insertion.
Technischer Bericht NASA-GB-002-95, NASA, Office of Safety and Mission
Assuran-ce, 1995
256 KEMPF, T., M DOERPER, R LEUPERS, G ASCHEID, H MEYR, T KOGEL und
B VANTHOURNOUT: A Modular Simulation Framework for Spatial and Temporal Task
Mapping onto Multi-Processor SoC Platforms In: Proceedings of the Design, Automa-tion and Test in Europe (DATE), Seiten 876–881, 2005.
257 KERNIGHAN, B W und D RITCHIE: The C Programming Language Prentice-Hall, Inc., Upper Saddle River, NJ, U.S.A., 1988 2 Auflage
258 KIENHUIS, B., E DEPRETTERE, K VISSERSund P.VAN DERWOLF: An Approach for
Quantitative Analysis of Application-Specific Dataflow Architectures In: Proceedings of the Conference on Application-Specific Systems, Architectures and Processors (ASAP),
Seiten 338–349, 1997
259 KINDLER, E und T VESPER: ESTL: A Temporal Logic for Events and States In:
Proceedings of the International Conference on Application and Theory of Petri Nets (ICATPN), Seiten 365–384, 1998.
260 KING, J C.: Symbolic Execution and Program Testing Communications of the ACM, 19(7):385–394, 1976
261 KIRCHNER, H., S RANISE, C RINGEISSENund D K TRAN: On
Superposition-Based Satisfiability Procedures and Their Combination In: Proceedings of the Inter-national Conference on Theoretical Aspects of Computing (ICTAC), Seiten 594–608,
2005
262 KLEIN, M.: A Practitioner’s Handbook for Real-Time Analysis Kluwer Academic Pu-blishers, Boston, MA, U.S.A., 1993
263 KLINGERMAN, E und A D STOYENKO: Real-Time Euclid: A Language for Reliable
Real-Time Systems IEEE Transactions on Software Engineering, SE-12(9):941–949,
1986
264 KOELBL, A., Y LU und A MATHUR: Embedded Tutorial: Formal Equivalence
Checking Between System-Level Models and RTL In: Proceedings of the Internatio-nal Conference on Computer-Aided Design (ICCAD), Seiten 965–971, 2005.
265 KONDRATYEV, A., M KISHINEVSKY, A TAUBINund S TEN: A Structural Approach
for the Analysis of Petri Nets by Reduced Unfoldings In: Proceedings of the Conference
on Application and Theory of Petri Nets, Seiten 346–365, 1996.
Trang 3266 KOPETZ, H.: Real-Time Systems – Design Principles for Distributed Embedded
Appli-cations Kluwer Academic Publishers, Boston, MA, U.S.A., 1997.
267 KOREN, I und C M KRISHNA: Fault Tolerant Systems Morgan Kaufmann Publishers Inc., San Francisco, CA, U.S.A., 2007
268 KRIPKE, S A.: A Completeness Theorem in Modal Logic The Journal of Symbolic Logic, 24(1):1–14, 1959
269 KRIPKE, S A.: Semantical Considerations on Modal Logic Acta Philosophica Fennica, 16:83–94, 1963
270 KROENING, D und E CLARKE: Checking Consistency of C and Verilog Using
Pre-dicate Abstraction and Induction In: Proceedings of the International Conference on Computer-Aided Design (ICCAD), Seiten 66–72, 2004.
271 KROENING, D und N SHARYGINA: Formal Verification of SystemC by Automatic
Hardware/Software Partitioning In: Proceedings of the International Conference on Formal Methods and Models for Co-Design (MEMOCODE), Seiten 101–110, 2005.
272 KROPF, THOMAS: Introduction to Formal Hardware Verification Springer, Berlin, Hei-delberg, 1999
273 KUEHLMANN, A und F KROHM: Equivalence Checking Using Cuts and Heaps In:
Proceedings of the Design Automation Conference (DAC), Seiten 263–268, 1997.
274 KUEHLMANN, A., V PARUTHI, F KROHMund M K GANAI: Robust Boolean
Rea-soning for Equivalence Checking and Functional Property Verification IEEE
Transacti-ons on Computer-Aided Design of Integrated Circuits and Systems, 21(12):1377–1394, 2002
275 KUNZ, W., D K PRADHANund S M REDDY: A Novel Framework for Logic
Veri-fication in a Synthesis Environment IEEE Transactions on Computer-Aided Design of
Integrated Circuits and Systems, 15(1):20–32, 1996
276 KUNZ, W und D STOFFEL: Reasoning in Boolean Networks Kluwer Academic Pu-blishers, Dordrecht, The Netherlands, 1997
277 K ¨UNZLI, S., F POLETTI, L BENINIund L THIELE: Combining Simulation and
For-mal Methods for System-Level Performance Analysis In: Proceedings of the Design, Automation and Test in Europe (DATE), Seiten 236–241, 2006.
278 LAHBIB, Y., A PERRIN, L MAILLET-CONTOZ, A CLOUARD, F GHENASSIAund
R TOURKI: Enriching the Boolean and the Modeling Layers of PSL with SystemC and
TLM Flavors In: Proceedings of the Forum on Design Languages (FDL), Seiten 273–
278, 2006
279 LAHIRI, K., A RAGHUNATHANund S DEY: System-Level Performance Analysis for
Designing On-Chip Communication Architectures IEEE Transactions on
Computer-Aided Design of Integrated Circuits and Systems, 20(6):768–783, Juni 2001
280 LAHIRI, S K und S A SESHIA: The UCLID Decision Procedure In: Proceedings
of the International Conference on Computer Aided Verification (CAV), Seiten 475–478,
2004
281 LAI, Y.-T und S SASTRY: Edge-Valued Binary Decision Diagrams for Multi-Level
Hierarchical Verification In: Proceedings of the Design Automation Conference (DAC),
Seiten 608–613, 1992
282 LALA, P K.: Fault Tolerant and Fault Testable Hardware Design Prentice-Hall, Inc., Upper Saddle River, NJ, U.S.A., 1985
283 LALA, P K (Herausgeber): Self-Checking and Fault-Tolerant Digital Design Morgan Kaufmann Publishers Inc., San Francisco, CA, U.S.A., 2001
284 LAM, W K.: Hardware Design Verification: Simulation and Formal Method-Based
Ap-proaches Pearson Studium, Deutschland, Upper Saddle River, NJ, U.S.A., 2005.
Trang 4285 LAMPKA, K., S PERATHONERund L THIELE: Analytic Real-Time Analysis and Timed
Automata: A Hybrid Method for Analyzing Embedded Real-Time Systems In: Procee-dings of the International Conference on Embedded Software (EMSOFT), Seiten 107–
116, 2009
286 LAMPORT, L.: ”Sometime” is Sometimes ”Not Never”: On the Temporal Logic of
Pro-grams In: Proceedings of the Symposium on Principles of Programming Languages (POPL), Seiten 174–185, 1980.
287 LAROUSSINIE, F., N MARKEYund P SCHNOEBELEN: On Model Checking
Duratio-nal Kripke Structures In: Proceedings of the InternatioDuratio-nal Conference on Foundations
of Software Science and Computation Structures (FoSSaCS), Seiten 264–279, 2002.
288 LAROUSSINIE, F., P SCHNOEBELEN, und M TURUANI: On the Expressivity and
Com-plexity of Quantitative Branching-Time Temporal Logics In: Proceedings of the Latin American Symposium on Theoretical Informatics (LATIN), Seiten 437–446, 2000.
289 LARRABEE, T.: Test Pattern Generation Using Boolean Satisfiability IEEE Transacti-ons on Computer-Aided Design of Integrated Circuits and Systems, 11(1):4–15, 1992
290 LASKI, J W.: On Data Flow Guided Program Testing ACM SIGPLAN Notices, 17(9):62–71, 1982
291 LASKI, J W und B KOREL: A Data Flow Oriented Program Testing Strategy IEEE Transactions on Software Engineering, SE-9(3):347–354, 1983
292 LAWLER, E L.: Optimal Sequencing of a Single Machine Subject to Precedence
Cons-traints Management Science, 19:544–546, 1973.
293 LE BOUDEC, J.Y und P THIRAN: Network Calculus: A Theory of Deterministic
Queuing Systems for the Internet Springer, New York, NY, U.S.A., 2001.
294 LEE, C Y.: Representation of Switching Circuits by Binary-Decision Programs Bell Systems Technical Journal, 38:985–999, 1959
295 LEE, E A.: Dataflow Process Networks Technischer Bericht UCB/ERL 94/53, Dept
of EECS, UC Berkeley, Berkeley, CA 94720, U.S.A., 1993
296 LEE, E A und D G MESSERSCHMITT: Synchronous Data Flow Proceedings of the IEEE, 75(9):1235–1245, 1987
297 LEE, E A., S NEUENDORFFERund M J WIRTHLIN: Actor-Oriented Design of
Em-bedded Hardware and Software Systems Journal of Circuits, Systems, and Computers,
12(3):231–260, 2003
298 LEE, E A und A L SANGIOVANNI-VINCENTELLI: A Framework for Comparing
Models of Computation IEEE Transactions on Computer-Aided Design of Integrated
Circuits and Systems, 17(12):1217–1229, 1998
299 LEHOCZKY, J.: Fixed Priority Scheduling of Periodic Task Sets with Arbitrary
Dead-lines In: Proceedings of the Real-Time Systems Symposium (RTSS), Seiten 201–209,
1990
300 LEHOCZKY, J P und L SHA: Performance of Real-Time Bus Scheduling Algorithms
In: International Conference on Measurement and Modeling of Computer Systems,
Sei-ten 44–53, 1986
301 LEUNG, J und J WHITEHEAD: On the Complexity of Fixed Priority Scheduling of
Periodic, Real-Time Tasks Performance Evaluation, 2(4):237–250, 1982.
302 LI, Y.-T S und S MALIK: Performance Analysis of Embedded Software Using Implicit
Path Enumeration ACM SIGPLAN Notices, 30(11):88–98, 1995.
303 LI, Y.-T S., S MALIKund A WOLFE: Efficient Microarchitecture Modeling and Path
Analysis for Real-Time Software In: Proceedings of the Real-Time Systems Symposium (RTSS), Seiten 298–307, 1995.
Trang 5304 LICHTENSTEIN, O und A PNUELI: Checking that Finite State Concurrent Programs
Satisfy their Linear Specification In: Proceedings of the Symposium on Principles of Programming Languages (POPL), Seiten 97–107, 1985.
305 LIGGESMEYER, P.: Software-Qualit¨at – Testen, Analysieren und Verifizieren von
Soft-ware Spektrum Akademischer Verlag, Heidelberg, Berlin, 2002.
306 LIGGESMEYER, P und D ROMBACH: Software Egineering eingebetteter Systeme –
Grundlagen - Methodik - Anwendungen Elsevier GmbH, M¨unchen, 2005.
307 LIU, C L und J W LAYLAND: Scheduling Algorithms for Multiprogramming in a
Hard-Real-Time Environment Journal of the ACM, 20(1):46–61, 1973.
308 LIU, J.: Real-Time Systems Prentice-Hall, Inc., Boston, MA, U.S.A., 2000
309 LU, R und C.-K KOH: Performance Analysis of Latency-Insensitive Systems IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 25(3):469–
483, 2006
310 MAHFOUDH, M., P NIEBERT, E ASARINund O MALER: A Satisfiability Checker
for Difference Logic In: Proceedings of the Symposium on Theory and Applications of Satisfiability Testing (SAT), Seiten 222–230, 2002.
311 MANO, M M und C R KIME: Logic and Computer Design Fundamentals Pearson Studium, Deutschland, Upper Saddle River, NJ, U.S.A., 2008 4 Auflage
312 MARKEY, N und P SCHNOEBELEN: Symbolic Model Checking of Simply-Timed
Sys-tems In: Proceedings of the International Conference on Formal Modeling and Analysis
of Timed Systmes (FORMATS), Seiten 102–117, 2004.
313 MARQUES-SILVA, J P.: The Impact of Branching Heuristics in Propositional
Satisfiabi-lity Algorithms In: Proceedings of the Portuguese Conference on Artificial Intelligence (EPIA), Seiten 62–74, 1999.
314 MARQUES-SILVA, J P und K A SAKALLAH: GRASP: A Search Algorithm for
Pro-positional Satisfiability IEEE Transactions on Computers, 48(5):506–521, 1999.
315 MATSUMOTO, T., H SAITOund M FUJITA: Equivalence Checking of C Programs
by Locally Performing Symbolic Simulation on Dependence Graphs In: Proceedings of the International Symposium on Quality of Electronic Design (ISQED), Seiten 370–375,
2006
316 MCMILLAN, K L.: Symbolic Model Checking: An Approach to the State Explosion
Problem Kluwer Academic Publishers, Norwell, MA, U.S.A., 1993.
317 MCMILLAN, K L.: Using Unfoldings to Avoid the State Explosion Problem in the
Verification of Asynchronous Circuits In: Proceedings of the International Conference
on Computer Aided Verification (CAV), Seiten 164–177, 1993.
318 MCMILLAN, K L.: Trace Theoretic Verification of Asynchronous Circuits Using
Unfol-dings In: Proceedings of the International Conference on Computer Aided Verification (CAV), Seiten 180–195, 1995.
319 MCMILLAN, K L.: Verification of an Implementation of Tomasulo’s Algorithm by
positional Model Checking In: Proceedings of the International Conference on Com-puter Aided Verification (CAV), Seiten 110–121, 1998.
320 MCMILLAN, K L.: Interpolation and SAT-Based Model Checking In: Proceedings of
the International Conference on Computer Aided Verification (CAV), Seiten 1–13, 2003.
321 MCMILLAN, K L und N AMLA: Automatic Abstraction without Counterexamples
In: Proceedings of the International Conference on Tools and Algorithms for the
Con-struction and Analysis of Systems (TACAS), Seiten 2–17, 2003.
322 MCNAUGHTON, R.: Testing and Generating Infinite Sequences by a Finite Automaton Information and Control, 9(5):521–530, 1966
323 MCNAUGHTON, R und H YAMADA: Regular Expressions and State Graphs for
Auto-mata IRE Transactions on Electronic Computers, EC-9(1):39–47, 1960.
Trang 6324 MEINEL, C und T THEOBALD: Algorithmen und Datenstrukturen im VLSI-Design –
OBDD-Grundlagen und -Anwendungen Springer, Berlin, Heidelberg, 1998.
325 MELHAM, T.: Abstraction Mechanisms for Hardware Verification In: VLSI
Specificati-on, Verification and Synthesis, Seiten 129–157, 1988.
326 MERLIN, P M.: A Study of the Recoverability of Computing Systems Doktorarbeit, University of California, Irvine, Irvine, CA, U.S.A., 1974
327 MIN´E, A.: The Octagon Abstract Domain Higher Order and Symbolic Computation, 19(1):31–100, 2006
328 http://www.model.com/
329 MOLITOR, P und J MOHNKE: Equivalence Checking of Digital Circuits Kluwer Aca-demic Publishers, Boston, 2004
330 M ¨OLLER, K.-H.: Ausgangsdaten f¨ur Qualit¨atsmetriken – Eine Fundgrube f¨ur Analysen. In: EBERT, C und R DUMKE(Herausgeber): Software-Metriken in der Praxis, Seiten
105 – 116 Springer, Berlin, 1996
331 MOON, I.-H., J.H KUKULA, K RAVIund F SOMENZI: To Split or to Conjoin: The
Question in Image Computation In: Proceedings of the Design Automation Conference (DAC), Seiten 23–28, 2000.
332 MOORE, G.: Cramming More Components onto Integrated Circuits Electronics, 38:114–117, 1965
333 MORIN-ALLORY, K und D BORRIONE: A Proof of Correctness for the Construction
of Property Monitors In: Proceedings of the High-Level Design Validation and Test Workshop (HLDVT), Seiten 237–244, 2005.
334 MORIN-ALLORY, K und D BORRIONE: On-Line Monitoring of Properties Built on
Regular Expressions In: Proceedings of the Forum on Design Languages (FDL), Seiten
249–254, 2006
335 MORIN-ALLORY, K und D BORRIONE: Proven Correct Monitors from PSL
Specifi-cations In: Proceedings of the Design, Automation and Test in Europe (DATE), Seiten
1246–1251, 2006
336 MOSKEWICZ, M W., C F MADIGAN, Y ZHAO, L ZHANGund S MALIK: Chaff:
Engineering an Efficient SAT Solver In: Proceedings of the Design Automation Confe-rence (DAC), Seiten 530–535, 2001.
337 MOY, M., F MARANINCHIund L MAILLET-CONTOZ: LusSy: A Toolbox for the
Ana-lysis of Systems-on-a-Chip at the Transactional Level In: Proceedings of the Internatio-nal Conference on Application of Concurrency to System Design (ACSD), Seiten 26–35,
2005
338 MURATA, T.: Petri Nets: Properties, Analysis, and Applications Proceedings of the IEEE, 77(4):541–580, 1989
339 MUSUVATHI, M., D Y W PARK, A CHOU, D R ENGLERund D L DILL: CMC: A
Pragmatic Approach to Model Checking Real Code ACM SIGOPS Operating Systems
Review, 36(SI):75–88, 2002
340 NADEL, ALEXANDER: Backtrack Search Algorithms for Propositional Logic
Satisfia-bility: Review and Innovations Master Thesis, The Hebrew University of Jerusalem,
Israel, 2002
341 NAUR, P.: Checking of Operand Types in ALGOL Compilers BIT Numerical Mathe-matics, 5(3):151–163, 1965
342 NELSON, C G und D C OPPEN: Simplification by Cooperating Decision Procedures ACM Transactions on Programming Languages and Systems (TOPLAS), 1(2):245–257, 1979
343 NIELSON, F., H R NIELSONund C HANKIN: Principles of Program Analysis Sprin-ger, Heidelberg, Berlin, New York, 2005 2 Auflage
Trang 7344 NIEMANN, B und C HAUBELT: Assertion-Based Verification of Transaction Level
Mo-dels In: Proceedings of Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), Seiten 232–236, 2006.
345 NIEMANN, B und C HAUBELT: Formalizing TLM with Communicating State
Machi-nes In: Proceedings of the Forum on Design Languages (FDL), Seiten 285–292, 2006.
346 NIEMANN, B und C HAUBELT: Towards a Unified Execution Model for Transactions
in TLM In: Proceedings of the International Conference on Formal Methods and Models for Co-Design (MEMOCODE), Seiten 103–112, 2007.
347 NIEMANN, B., C HAUBELT, M URIBEund J TEICH: Formalizing TLM with
Com-municating State Machines In: Advances in Design and Specification Languages for Embedded Systems, Seiten 225–242 Springer, 2007.
348 NIEUWENHUIS, R und A OLIVERAS: DPLL(T) with Exhaustive Theory Propagation
and Its Application to Difference Logic In: Proceedings of the International Conference
on Computer Aided Verification (CAV), Seiten 321–334, 2005.
349 NTAFOS, S C.: On Required Element Testing IEEE Transactions on Software Engi-neering, SE-10(6):795–803, 1984
350 NTAFOS, S C.: A Comparison of some Structural Testing Strategies IEEE Transactions
on Software Engineering, 14(6):868–874, 1988
351 http://www.accellera.org/
352 OSCI TLM WORKINGGROUP: OSCI TLM-2.0 Language Reference Manual, 2009 Version JA32, http://www.systemc.org
353 PARTHASARATHY, G., M K IYER, K.-T CHENGund L.-C WANG: An Efficient
Finite-Domain Constraint Solver for Circuits In: Proceedings of the Design Automation Conference (DAC), Seiten 212–217, 2004.
354 PASRICHA, S., N DUTT, E BOZORGZADEHund M BEN-ROMDHANE: FABSYN:
Floorplan-aware Bus Architecture Synthesis IEEE Transactions on Very Large Scale
Integrated Systems, 14(3):241–253, 2006
355 PATTERSON, D A und J L HENNESSY: Computer Organization & Design: The
Hardware/Software Interface Morgan Kaufmann Publishers Inc., San Francisco, CA,
U.S.A., 1997 2 Auflage
356 PCI SPECIALINTERESTGROUP: PCI Local Bus Specification, 1998 Version 2.2
357 PELED, D.: All from One, One for All: On Model Checking Using Representatives In:
Proceedings of the International Conference on Computer Aided Verification (CAV),
Seiten 409–423, 1993
358 PELED, D.: Combining Partial Order Reductions with On-the-Fly Model-Checking Journal of Formal Methods in System Design, 8(1):39–64, 1996
359 PETERSON, J L.: Petri Net Theory and Modeling of Systems Prentice-Hall, Inc., Rea-ding, MA, 1981
360 PETRI, C A.: Interpretations of a Net Theory Technischer Bericht 75–07, GMD, Bonn, Germany, 1975
361 PIERRE, L und L FERRO: A Tractable and Fast Method for Monitoring SystemC TLM
Specifications IEEE Transactions on Computers, 57(10):1346–1356, 2008.
362 PILARSKI, S und G HU: SAT with Partial Clauses and Back-Leaps In: Proceedings
of the Design Automation Conference (DAC), Seiten 743–746, 2002.
363 PIMENTEL, A D., C ERBASund S POLSTRA: A Systematic Approach to Exploring
Embedded System Architectures at Multiple Abstraction Levels IEEE Transactions on
Computers, 55(2):99–112, 2006
364 PNUELI, A.: The Temporal Logic of Programs In: Proceedings of the Symposium on
Foundations of Computer Science, Seiten 46–57, 1977.
Trang 8365 POP, T., P ELESund Z PENG: Holistic Scheduling and Analysis of Mixed
Time/Event-Triggered Distributed Embedded Systems In: Proceedings of the Conference on Hard-ware/Software Codesign (CODES), Seiten 187–192, 2002.
366 PRASAD, M., A BIEREund A GUPTA: A Survey of Recent Advances in SAT-Based
Formal Verification International Journal on Software Tools for Technology Transfer
(STTT), 7(2):156–173, 2005
367 PROSSER, PATRICK: Hybrid Algorithms for the Constraint Satisfaction Problem Com-putational Intelligence, 9(3):268–299, 1993
368 PUSCHNER, P und C KOZA: Calculating the Maximum, Execution Time of Real-Time
Programs Real-Time Systems, 1(2):159–176, 1989.
369 QUEILLE, J.-P und J SIFAKIS: Specification and Verification of Concurrent Systems in
CESAR In: Proceedings of the Symposium on Programming, Seiten 337–351, 1982.
370 RAMCHANDANI, C.: Analysis of Asynchronous Concurrent Systems by Timed Petri
Nets Doktorarbeit, Massachusetts Institute of Technology, Cambridge, MA, U.S.A.,
1974
371 RAVI, K und F SOMENZI: High-Density Reachability Analysis In: Proceedings of the
International Conference on Computer-Aided Design (ICCAD), Seiten 154–158, 1995.
372 REDA, S und A SALEM: Combinational Equivalence Checking Using Boolean
Satis-fiability and Binary Decision Diagrams In: Proceedings of the Design, Automation and Test in Europe (DATE), Seiten 122–126, 2001.
373 REISIG, W.: A Primer in Petri Net Design Springer, Berlin, Heidelberg, New York, Tokyo, 1992
374 REISIG, W.: Elements of Distributed Algorithms: Modeling and Analysis with Petri
Nets Springer, Berlin, 1998.
375 REITER, R.: Scheduling Parallel Computations Journal of the ACM, 15(4):590–599, 1968
376 REYNOLDS, J C.: Automatic Computation of Data Set Definitions In: Proceedings of
IFIP Congress, Band 1, Seiten 456–461, 1968.
377 RICHTER, K.: Compositional Scheduling Analysis Using Standard Event Models Dok-torarbeit, Technische Universit¨at Braunschweig, Deutschland, 2004
378 RICHTER, K und R ERNST: Event Model Interfaces for Heterogeneous System
Ana-lysis In: Proceedings of the Design, Automation and Test in Europe (DATE), Seiten
506–513, 2002
379 RICHTER, K., M JERSAKund R ERNST: A Formal Approach to MPSoC Performance
Verification IEEE Computer, 36(4):60–67, 2003.
380 RICHTER, K., D ZIEGENBEIN, M JERSAKund R ERNST: Model Composition for
Scheduling Analysis in Platform Design In: Proceedings of the Design Automation Conference (DAC), Seiten 287–292, 2002.
381 ROTH, J P.: Diagnosis of Automata Failures: A Calculus and a Method IBM Journal
of Research and Development, 10(4):278–291, 1966
382 RTCA: Software Considerations in Airborne Systems and Equipment Certification
DO-178B, 1992
383 RUDELL, R.: Dynamic Variable Ordering for Ordered Binary Decision Diagrams In:
Proceedings of the International Conference on Computer-Aided Design (ICCAD),
Sei-ten 42–47, 1993
384 http://www.haifa.ibm.com/projects/verification/RB Homepage/
385 SAFRA, S.: On the Complexity ofω-Automata In: Proceedings of the Symposium on Foundations of Computer Science, Seiten 319–327, 1988.
Trang 9386 SCHIRNER, G und R D ¨OMER: Quantitative Analysis of Transaction Level Models for
the AMBA Bus In: Proceedings of the Design, Automation and Test in Europe (DATE),
Seiten 230–235, 2006
387 SCHIRNER, G., A GERSTLAUERund R D ¨OMER: Abstract, Multifaceted Modeling of
Embedded Processors for System Level Design In: Proceedings of the Asia and South Pacific Design Automation Conference (ASPDAC), Seiten 384–389, 2007.
388 SCHLIECKER, S., S STEINund R ERNST: Performance Analysis of Complex Systems
by Integration of Dataflow Graphs and Compositional Performance Analysis In: Pro-ceedings of the Design, Automation and Test in Europe (DATE), Seiten 273–278, 2007.
389 SCHMIDT, D A.: Data Flow Analysis is Model Checking of Abstract Interpretations
In: Proceedings of the Symposium on Principles of Programming Languages (POPL),
Seiten 38–48, 1998
390 SCHNEIDER, K.: Verification of Reactive Systems – Formal Methods and Algorithms Springer, Berlin, Heidelberg, 2004
391 SCHNERR, J., O BRINGMANN, A VIEHLund W ROSENSTIEL: High-Performance
Timing Simulation of Embedded Software In: Proceedings of the Design Automation Conference (DAC), Seiten 290–295, 2008.
392 SEBASTIANI, ROBERTO: Lazy Satisfiability Modulo Theories Journal on Satisfiability, Boolean Modeling and Computation, 3:141–224, 2007
393 SHANNON, C E.: The Synthesis of Two-Terminal Switching Circuits Bell Systems Technical Journal, 28:59–98, 1949
394 SHASHIDHAR, K C., M BRUYNOOGHE, F CATTHOORund G JANSSENS: Automatic
Functional Verification of Memory Oriented Global Source Code Transformations In: Proceedings of the High-Level Design Validation and Test Workshop (HLDVT), Seiten
31–36, 2003
395 SHASHIDHAR, K C., M BRUYNOOGHE, F CATTHOORund G JANSSENS:
Func-tional Equivalence Checking for Verification of Algebraic Transformations on Array-Intensive Source Code In: Proceedings of the Design, Automation and Test in Europe (DATE), Seiten 1310–1315, 2005.
396 SHASHIDHAR, K C., M BRUYNOOGHE, F CATTHOORund G JANSSENS:
Verifica-tion of Source Code TransformaVerifica-tions by Program Equivalence Checking In: Compiler Construction, Seiten 221–236 Springer, 2005.
397 SHEINI, H M und K A SAKALLAH: A Scalable Method for Solving Satisfiability of
Integer Linear Arithmetic Logic In: Theory and Applications of Satisfiability Testing,
Seiten 241–256, 2005
398 SHEKHAR, N., P KALLAund F ENESCU: Equivalence Verification of Polynomial
Da-tapaths Using Ideal Membership Testing IEEE Transactions on Computer-Aided
De-sign of Integrated Circuits and Systems, 26(7):1320–1330, 2007
399 SHOSTAK, R E.: A Practical Decision Procedure for Arithmetic with Function
Sym-bols Journal of the ACM, 26(2):351–360, 1979.
400 SHOSTAK, R E.: Deciding Combinations of Theories Journal of the ACM, 31(1):1–12, 1984
401 SHTRICHMAN, O.: Pruning Techniques for the SAT-Based Bounded Model Checking
Problem In: Proceedings of Conference on Correct Hardware Design and Verification Methods (CHARME), Seiten 58–70, 2001.
402 SIEBENBORN, A., A VIEHL, O BRINGMANNund W ROSENSTIEL: Control-Flow
Aware Communication and Conflict Analysis of Parallel Processes In: Proceedings of the Asia and South Pacific Design Automation Conference (ASPDAC), Seiten 32–37,
2007
Trang 10403 SKAKKEBÆK, J U., R B JONESund D L DILL: Formal Verification of Out-of-Order
Execution Using Incremental Flushing In: Proceedings of the International Conference
on Computer Aided Verification (CAV), Seiten 98–109, 1998.
404 http://www.averant.com/products-solidify.html
405 SOMENZI, F und R BLOEM: Efficient B¨uchi Automata from LTL Formulae In:
Pro-ceedings of the International Conference on Computer Aided Verification (CAV), Seiten
248–263, 2000
406 SPURI, M.: Earliest Deadline Scheduled in Real-Time Systems Doktorarbeit, INRIA,
Le Chesnay, Cedex, France, 1995
407 SPURI, M.: Analysis of Deadline Scheduled Real-Time Tasks Technischer Bericht, IN-RIA, Le Chesnay, Cedex, France, 1996
408 STANKOVIC, J., M SPURI, K RAMAMRITHAMund G BUTTAZZO: Deadline
Schedu-ling for Real-Time Systems – EDF and Related Algorithms Kluwer Academic
Publis-hers, Boston, MA, U.S.A., 1998
409 STARKE, P H.: Analyse von Petri-Netz-Modellen Teubner, Stuttgart, 1990
410 STEFFEN, B.: Data Flow Analysis as Model Checking In: ’Proceedings of the
In-ternational Conference on Theoretical Aspects of Computer Software (TACS), Seiten
346–365, 1991
411 STOFFEL, D und W KUNZ: Record & Play: A Structural Fixed Point Iteration for
Sequential Circuit Verification In: Proceedings of the International Conference on Computer-Aided Design (ICCAD), Seiten 394–399, 1997.
412 STOFFEL, D., M WEDLER, P WARKENTINund W KUNZ: Structural FSM
traver-sal IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems,
23(5):598–619, 2004
413 STRAHM, T.: Logik in Informatik, Mathematik und Philosophie, 1999 Vortrag anl¨ass-lich der Veranstaltung Theodor-Kocher-Preis 1998 der Universit¨at Bern
414 STREHL, K.: Symbolic Methods Applied to Formal Verification and Synthesis in
Em-bedded Systems Design Doktorarbeit, Swiss Federal Institute of Technology Zurich,
Switzerland, 2000
415 STREHL, K und L THIELE: Symbolic Model Checking of Process Networks Using
Interval Diagram Techniques In: Proceedings of the International Conference on
Computer-Aided Design (ICCAD), Seiten 686–692, 1998.
416 STREHL, K und L THIELE: Interval Diagram Techniques for Symbolic Model
Checking of Petri Nets In: Proceedings of the Design, Automation and Test in
Euro-pe (DATE), Seiten 756–757, 1999.
417 STREHL, K., L THIELE, M GRIES, D ZIEGENBEIN, R ERNSTund J TEICH:
Fun-State – An Internal Design Representation for Codesign IEEE Transactions on Very
Large Scale Integrated Systems, 9(4):524–544, 2001
418 STREHL, K., L THIELE, D ZIEGENBEIN, R ERNSTund J TEICH: Scheduling
Hard-ware/Software Systems Using Symbolic Techniques In: Proceedings of the Conference
on Hardware/Software Codesign (CODES), Seiten 173–177, 1999.
419 STREUBUHR, M., J FALK, C HAUBELT, J TEICH, R DORSCH¨ und T SCHLIPF:
Task-Accurate Performance Modeling in SystemC for Real-Time Multi-Processor Archi-tectures In: Proceedings of the Design, Automation and Test in Europe (DATE), Seiten
480–481, 2006
420 STREUBUHR, M., J GLADIGAU, C HAUBELT¨ und J TEICH: Efficient
Approximately-Timed Performance Modeling for Architectural Exploration of MPSoCs In: Proceedings
of the Forum on Design Languages (FDL), 2009.
421 STROUSTRUP, B.: The C++ Programming Language: Language Library and Design
Tutorial Addison-Wesley, Amsterdam, 1997.