Activation
of architecture for verification
software, 95, 104–107
examples, 22–24
models, 97
standard variables, 23
of system, 51, 179
variables, 21–24, 35
in functional space, 44, 59–60
processor, 22–24
Active target, 24
Actual time variables, 29–30
Aesthetic evaluations, 36
Analysis, standard results for, 138
Arc convergence, 124
Architecture for verification software,
95–110
activation, 104–107
activation models, 97
context models, 97
coverage models, 98
CRV process, 102–104
deterministic generator, 97–98
expected results checkers, 98
flow for soft prototype, 99–100
functionality, 98–99
gate-level simulation, 109–110
halting individual tests, 108
ingredients, 97–98
initialization, 104–107
monitors, 98
production test vectors, 110
protocol checkers, 98
random value assignment, 101
sanity checking and other tests,
108–109
sockets for instances of verification
target, 97
static vs dynamic test
generation, 108 test generator, 97 transactors, 98 Arc transversability, in state machines, 143, 145 Assertions, 87–88 Associated synchronization logic, 21 Asynchronous digital systems, 10 Automated test program generation (ATPG), 110
Autonomous responses, 31 Basis variables, orthogonal system of, 38
Bugs, 2, 4–6, 13, 33–34, 38 count as function of complexity, 135–136
counts and severity, 115 discovery rate, 115–117 distribution in target, 71 driven testing, 77 fixing, 77–78 locality, 115
of omission, 74 tracking, 75 using Q to estimate risk of, 169–174 workarounds, 91, 114
Built-in self-test unit (BIST),
in processor, 22 Cadence Encounter Conformal CDC capability, 82 Clock domain, 10 Clock-domain crossings (CDCs), 89, 149–150
Trang 2verification plan, 81–83
Clocking, variables, 21, 38, 44
Code coverage, 24, 140–142, 144
standard specific measures, 148
Collision-detect multiple-access
algorithm, 37
Commercial IP, evaluation of,
174–176
Complexity
bug count as function of,
135–136, 174
cycles counts with, 133–134
estimate for, 129
gate count and, 128
size of functional space, 136
standard specific measures, 148
of targets, 121, 126–129
Compliance test, 36
Composition
of instruction, 32
variables of stimulus and response,
29–30
Condensation, in functional space,
47–50
Condensed functional space, 44, 47,
128
8-entry queue analysis, 53–59
Condition
coverage, 24
direct conditions, 24
examples, 25–27
external conditions, 25–26, 38
indirect conditions, 24–25, 27
internal conditions, 25–26, 38
and responses variables, 31–32,
35, 38
variables, 24–27, 35, 38
in functional space, 45
Connecting dots, in functional space,
50–53
Connectivity
external, 40–42, 44
internal, 40–42, 44
quadrants of subspace of, 147
time-invariant variables of, 44
Connectivity variables, 16–21, 35, 38
external, 16–19, 38 context of instance and, 17 specification and standard variables for, 17–19
in functional space, 40–44 internal, 16, 19–21, 38 instance of target and, 17 standard variables of, 20 Constrained pseudo-random functional verification, 5–6 Constrained random verification (CRV) technique, 5–7, 10, 33, 36–7, 50, 62, 64, 71–2, 89, 99–104
of architecture for verification software, 102–104 principles of, 5–6 saving initialized systems for, 105 using previously initialized system, 107
Context models, of architecture for verification software, 97 Contiguous ranges, of variables, 13 Control signal, synchronization, 81 Convergence
arc convergence, 125 determination against target, 125 expression convergence, 125 factors to consider in using, 124–126 gap, 123
line convergence, 125 power and, 122–124 scaling regression using, 129–132 state convergence, 125
stratification of, 124–125
of tests, 123
in verification projects, 122–126, 129–132
Corner cases, 94 Counting function points
in functional space, 40–47 activation variables, 44 condition variables, 45 connectivity variables, 40–44 error variables, 45–46
Trang 3response variables, 45
special cases variables, 46
stimulus variables, 45
time-variant variables, 44
upper bound, 46–47
Coverage
analysis, 21–22, 88
closure, see Functional closure
driven testing, 77
measures of, 139–140
models of architecture for
verification software, 98
and risk assessment, 166–167
CRV tests, 77, 79, 105, 124
Cybernetic properties, 36
Cycles counts with complexity,
133–134
Data-driven risk assessment, 4, 9,
165, 167
De-activation testing, 104
Debugging, 4
Decision making, and risk
assessment, 157–159
Default morph, 29
Deterministic generator, of
architecture for verification
software, 97–98
Deterministic tests, 35
Development costs, and verification,
2–3
Device Under Test (DUT), 9–10
Device Under Verification (DUV),
9–10
Diagnostic morph, 28
Digital system
analysis, 9
bases of analysis, 10
functionality, 10, 37
linear algebra for verification,
10–12
standard framework for
interpretation, 12
standardized approach to
verification, 6
variables related to functionality
activation, 11–12 condition, 11–12 connectivity, 11–12 stimuli and response, 11–12 Directed random verification, 5 Directed tests, 2, 77
D-MUX, 81 Drop dead date, 111 Dynamically generated tests, 102 Dynamic test generation, 108 Dynamic transition, 36 Energized target, 24 8-Entry queue, 183–185 analysis
condensed functional space, 54–56, 58, 185, 186–188 explicit representation of reset for, 59–60
functional closure, 68–69
of functional space, 53–59, 183 uncondensed functional space,
54, 57 with programmable HWM and LWM, 193
Enumerated ranges, of variables, 13–14
Error
of commission, 4
in composition of stimulus, 45
in functional space, 45–46 imposition, 33–35, 38
of omission, 4
in time of stimulus, 45 variables, 45–46 Ethernet
magic packet, 23 protocol, 23, 89 specifications for, 37 Excitation, 179 Excitation drives, 51 Excitement generation, 35 Expected results checkers, 98 Expression convergence, 125 External activity, 36
External condition variables, 45
Trang 4External connectivity
example, 17–19
standard variable for
verification, 18
systems in condensed space of,
49–50
variables, 16–19, 38, 40–42, 44
context of instance and, 17
specification and standard,
17–19
Failure analysis, 64, 78, 88, 103, 114
Fault coverage, 143–144
Faulty behavior, 75–76, 94–95, 103,
106, 114, 180
risk of, 5–6
Firewire devices, 24
Firm prototype, 78, 93
Floating-point unit (FPU), 22
Focused ion beam (FIB) measure, 91
Focused random verification, 5
FPGA, 78, 89, 93
FPGA-based prototype, 78
Functional bug, 6
Functional closure, 1–2, 39–40,
69, 163
8-entry queue analysis, 68
in functional space, 39–40, 68–69
and risk, 181
Functional coverage, 137–138
Functionality interpretation, 35
Functional shmoo testing, 114
Functional space, 39–69
arc transversability in state
machines, 143, 145, 148
budgeting for success, 162–163
code coverage, 140–142, 145, 148
complexity and size of, 136
condensation in, 47–50
connecting dots, 50–53
counting function points, 40–47
activation variables, 44
condition variables, 45
connectivity variables, 40–44
error variables, 45–46
response variables, 45
special cases variables, 46 stimulus variables, 45–46 time-variant variables, 44 upper bound, 46–47 8-entry queue analysis, 53–59 fault coverage, 143–144 functional closure, 39–40, 68–69 graph theory, 65–68
measures of coverage, 139–140 mediation by response variable, 59 modeling faulty behavior, 63–64 multiple clock domains, 149–150
of queue, 183–193 relations among values of variables
in, 51 reset in VTG, 59–63 hard reset, 61 soft reset, 62 soft origin of, 62–63 special cases variables, 46, 64–65 specific and general measures, 146–149
standard measures of, 145–146,
148 state reachability in state machines, 142–143, 145, 148
statistically sampling, 138–139 success and failure spaces, 161–162
values of variables in, 179 views of coverage, 150–155 1-dimensional views, 151 2-dimensional views, 153–154 indicators for, 150
Pareto views, 151–153 standard views, 155–156 time-based views, 153–155 VTG arc coverage, 144–145, 148 Functional trajectory, 50, 59,
63, 65, 179 Functional verification cost and risk, 1–2 CRV technique for, 5–7 development costs and, 2–3 effectiveness, 1
elements, 7
Trang 5lessons learned from, 3–4
objective of, 4
risk assessment for, see Risk
assessment
standardized approach, 6–8
terminology, 9
time to market and, 2
Function arcs, 50–51, 88
Gate-level simulation, in architecture
for verification software,
109–110
Graph theory, for functional space,
65–68
Halting individual tests, in
architecture for verification
software, 108
Hamming distance, 177
Hamming weight, 42, 177
Handshake protocol, 82–83, 89
Hard prototype, 78
instrumentation for, 88, 90
internal responses, 31
mechanisms for verification of, 90
Hard resets, 31, 35–36, 104
Holding a split lot at metal measure,
90–91
Human interaction, responsiveness
to, 36
Human programmers’ inefficiency,
and verification, 5
IC development projects
complexity of verification, 5
costs after first tape-out, 3
functional verification, 1–2
human programmers’
inefficiency, 5
multiple variables of internal
connectivity in, 21
programming habits and, 5
time from tape-out to shipping
product for revenue, 2–3
Incompleteness of verification,
indicator of, 140
Indirect conditions, 36 Inherent value boundaries of ranges, 13
Initialization
in architecture for verification software, 104–107 process, 25–26, 51, 59
of system, 179 Inspection, verification by, 61 Instruction, composition of, 32–33 Internal condition variables, 45 Internal connectivity, 27 examples, 19–21 variables, 16, 19–21, 38, 40–42, 44 instance of target and, 17 standard, 20
Inverse time variables, 30
IP evaluation of, 174–176 for single application, 176 Knowledge, and risk assessment, 164–166
Linear algebra loosely orthogonal system in, 11 for verification of digital system, 10–12
Line convergence, 125 Measures
code coverage, 140–142, 145
of coverage, 139–140 fault coverage, 143–144 functional space coverage, 137–138, 145–146 for quadrant, 148–149 relative strength of, 145 specific and general, 146–149 standard specific, 145–146, 148 strong and weak, 144–145 VTG coverage, 144–145 Mediation, by response variable in functional space, 51, 59 Metamorphosis, 27–29, 38
of target, 27–28
Trang 6values for variables that
determine, 28
Modeling faulty behavior, for
functional space, 63–64
Morphing target, 36
Morphs, see Metamorphosis
Multi-instance RTL, 19
Multiple clock domains, 149–150
MUX synchronizer, 81–82
Nearest neighbor analysis, 176–179
Normalized cycles, in risk
assess-ment, 134–135
Ordering errors, 33
Performance requirements, 14
Physical prototype, 78
Piece-wise contiguous ranges, of
variables, 13–14
Planning, of verification project, 76;
see also Verification plan
Post-silicon bugs, 169
Post tape-out bugs, 170
Power
and convergence, 122–124
saving circuitry in processor, 22
variables, 21, 38, 44
Processor
activation variables for, 22–24
built-in self-test unit, 22
internal connectivity in, 19
power-saving circuitry, 22
variable clock-speeds, 22
as verification target, 19
Production test vectors, for
architec-ture verification software, 110
Programmable logic array (PLA), 90
Programmers habits, 5
Programming habits, 5
Project resources estimation, 121–122
Protocol checkers, for architecture
verification software, 98
Prototype instrumentation
checking accommodated by, 88–90
expected results, 88–89
hard prototype, 88, 90 mechanisms for verification, 90 properties, 89
protocol, 89 soft prototype, 88 state coherency, 89 transformation of data, 89 transport, 89
for verification plan, 87–91 Pseudo-random excitation, 35 Pseudo-random sequence, 35 Pseudo-random test generators, 35 Pseudo-random testing, 4–5
Queue, see also 8-Entry queue
adding indirect condition, 186–189 basic 8-entry queue, 183–185 condensation in functional space, 191–192
functional space of, 183–193 programmable high-and low-water mark, 190
size of functional space for, 190–191
Random regression suite, 129 Random testing, 2–4
Random value assignment, in archi-tecture for verification software,
101 Random verification, principles
of, 5–6 Re-activation testing, 104 Regression suite, 72 fault coverage for, 143–144 standard specific measures, 145–146, 148
using convergence, 129–132 and verification plan, 72–73 Regression testing, 6
Relative time variables, 30 Reset
for explicit representation of 8-entry queue analysis, 59–60 variables, 21–22, 24, 31, 35–36, 38 assertion of, 21, 24, 35, 60, 62
Trang 7de-assertion of, 21, 24, 31, 35, 60
in VTG functional space, 59–63
hard reset, 59, 61–62
soft reset, 62
Response
autonomous, 31
composition variables, 29
conditions and, 31–32
example, 32–33
internal, 30–31
sequence abstraction, 30
time variables, 29
transactions abstraction, 30
variables, 29–33, 35
in functional space, 45
Result analysis, with standard views
and measures, 139
Risk assessment, 4
background on, 159–160
of bug, 169–174
coverage and, 166–167
data-driven, 165, 167
decision making and, 157–159
functional closure and, 181
knowledge and, 164–165
nearest neighbor analysis for,
176–179
normalized cycles in, 134–135
success and, 173
successful functional verification
project and, 160–164
VTG arc coverage, 168–169
RTL (register transfer level)
descrip-tion, 2, 4, 6, 10, 16, 19–20, 64,
71–72, 74
Rules and guidelines
examples, 14–16
performance objectives and, 14–15
from specification, 14–15
technical specifications, 14
for verification, 14
Sanity checking, for architecture
verification software, 108–109
Signal, with positive and negative
slack, 39
Sockets for instances of verification target, 97
Soft origin, of functional space, 62–63 Soft prototype, 78
architecture for software for verification of, 98 flow for, 99–100 instrumentation for, 88 Soft resets, 31, 35–36, 104 Spare gates, 90
Special cases, variables in functional space, 46, 64–65
Specification-driven testing, 77 Specifications, 14, 83–87 Standardized functional verification, 6–8
Standard measures, 91–93, 99, 137, 145–146, 148
result analysis with, 139 Standard results, for analysis, 138 Standard variables
of external connectivity, 18 variability, 13
for verification, 12–13 Standard views, 91–93, 99, 137 result analysis with, 139 State convergence, 125 State machines arc transversability in, 143,
145, 148 state reachability in, 142–143,
145, 148 State-of-the-art, verification tools, 51 State reachability, in state machines, 142–143, 145, 148
Statically generated tests, 102 Static test generation, 108 Stimulus
composition variables, 29 example, 32–33
internal stimuli, 30–31 sequence abstraction, 30 time variables, 29 transactions abstraction, 30 variables, 29–33, 38
in functional space, 45
Trang 8Stratification, of convergence, 124–125
Sweep testing, 114
Synchronization of control signal,
81–82
Synchronizer MUX, 81
Synchronous digital systems, 10, 22
System
activation of, 51
initialization of, 51
SystemVerilog, assertions in, 88
Target, 10
distribution of bugs in, 71
instantiation of, 51, 179
magical initialization of memory, 106
metamorphosis of, 27–28
morphing, 36
transcendental behaviors of, 36
value state of, 50
Technical specifications, 14
Temporal errors, 33
Test environment, architecture for, 96
Time checks, 88
Time to market, and verification, 2
Time variables
actual time, 29–30
inverse time, 30
relative time, 30
of stimulus and response, 29
Time-variant variables, in functional
space, 44
Timing closure, 39
Transactors, in architecture for
verification software, 98
Uncondensed functional space,
8-entry queue analysis, 54, 57
Upper bound, in functional
space, 46–47
Value checks, 88
Value errors, 33
Value transition graph (VTG), 45, 51,
53, 57–66, 68, 95, 114, 122,
128–129, 136, 138, 140, 144,
148, 152, 168–170, 179, 193
Variability, of standard variables, 13 Variable clock-speeds,
in processor, 22 Variables
of activation, 21–24, 35 boundary values, 47–48 composition of stimulus, 50
of condition, 24–27, 35
of connectivity, 16–21, 35, 50 external, 16–19
internal, 16, 19–21
of error in composition of stimulus, 45
external condition, 45 internal condition, 45 orthogonal system of, 38 ranges, 13–14
contiguous, 13 enumerated, 13–14 inherent value boundaries, 13 piece-wise contiguous, 13–14 relations among values of functional space, 51 special cases, 35–37 standard variables, 12–13
of stimulus and response, 29–33, 35 Verification
advantages inherent in, 3–4 challenges to, 5
complexity of, 5 development costs and, 2–3 human programmers’
inefficiency, 5 incompleteness of, 140
by inspection, 61 linear algebra for digital system, 10–12
process, 13 programming habits and, 5 ranges of variables, 13–14 rules and guidelines, 14–16 standard variable of external connectivity used for, 18 standard variables for, 12–13 terminology, 9
time to market and, 2
Trang 9Verification plan, 79–119
architecture, 80, 95–110
change from outside, 79
change management, 80, 110–111
clock domain crossings, 81–83
definition of target, 80–81
design, 80
documents, 80, 118
failure analysis, 114
goals, 80
incorporate discovery and
inven-tion, 79
instances and morphs for
opportun-istic inclusion, 81
instrumentation for prototype,
87–91
interpretation of specification,
83–87
learning, 79
matrix, 80
prevention measures, 90–91
regression suite and, 72–73
resources, 80, 118–119
results, 80, 91–94
scope and schedule, 80, 118–119
setting goals for coverage and
risks, 94–95
focusing resources, 94–95
making trade-offs, 94
standard measures, 91–93
teams organization, 111–114
tracking progress, 115–118
bug counts and severity,
115–116
bug discovery rate, 115–117
bug locality, 115
code coverage, 115–116
verifying changes to existing
device, 83
Verification process, 99
Verification projects
bug count as function of
complexity, 135–136
complexity of target and, 126–129
convergence
determination against target, 125
factors to consider in using, 124–126
gap, 123 power and, 122–124 stratification of, 124–125
of tests, 123 cycles counts with convergence, 133–134
execution, 74 goal, 72–73 management, 71 plan execution for results, 73–77 bug fixing, 77–78
code construction, 74–76 code revision, 76 final coding, 75–76 graduated testing, 76–77 initial coding, 75–76 preparation, 74 planning, 72 resource allocation, 122 scaling regression using convergence and, 129–132 size and complexity, 136 soft prototype and hard prototype, 78 successful functional verification, 160–164
using cycles in risk management, 134–135
verification plan, 83–123; see also
Verification plan Verification software architecture, 95–110
Verification tools, state-of-the-art, 51 Virtual prototype, 78
VTG arc coverage, 168–169 for 8-entry queue with programma-ble HWM and LWM, 193 for functional space, 144–145, 148 Warm resets, 104
Workarounds bug, 91, 114