Model-Based Design for Embedded Systems- P26 ppt

system-level modelsapplication model, 126 execution platform model, 127–129 illustration, 126 memory and power model, 129–130 task mapping, 129 Models of computation MoC, 522, 560–561 Mo

discrete functional category, 507

hybrid category, 509–510

multi-viewpoint composition,

512–515

safety/probabilistic categories,

510–512

semantic atoms, 507

system architecture, 512

timed category, 507–509

wrapper mechanism, 512

Hierarchical event streams (HESs)

inner and output event streams, 71–73

structure, 71

system analysis, 70–71

HRC, see Heterogeneous rich component

(HRC) state machines

Hybrid approach

advantages and disadvantages, 35–36

basic block

pipeline modeling, 40–43

principles, 39

static cycle calculation, 40

cycle prediction, dynamic correction

branch prediction, 43

cache analysis blocks, 44

cache model, 44

cycle calculation code, 45

instruction cache, 43

objectives, 35

software tasks, 46–47

SystemC code annotation, 38–40

task switches, 46

WCET/BCET value, back-annotation

advantages, 38

architecture, 36–37

instruction set, 37–38

Hybrid automata

exhaustive verification

abstraction, 403–404

autonomous linear systems, 398

finite syntactic representation,

397–398

linear inequalities, 397

linear systems, 398–401

nonlinear systems, 401–403

nontrivial differential equations,

396–397

piecewise constant derivatives (PCD), 396

time steps, 398 model-based design, 383–384 modeling

discrete dynamics, 389–390 Lipschitz continuous, 390 non-determinism, 391 trajectories, 390–391 rapidly-exploring random trees (RRTs)

algorithm, 408–409 hybrid distance, 410–411 iterations, 409–410 simulations, 409 test generation algorithm, steps, 425 cases and executions, 423–424 continuous inputs, 422 coverage-guided sampling, 425–426

discrete transitions, 422–423 state coverage strategies, 421–422

test coverage, 424–425 testing, 411–412

I

IBIS, see Interconnection bus for

integrated sensors

ICAP, see Internal configuration access

port

IContinu, see Continuous domain

interface, model

IDiscrete, see Discrete domain interface,

model Inertial measurement unit (IMU), 698,

702, 703, 716, 717 InitializeTA method, 469, 471 Input/output buffer (IOB), 368 Integrated multi-technology systems abstraction levels, 608, 609 application, 622–631 CMOS transistor, 603–604 design productivity gap, 606 ENIAC, 604–605

heterogeneous design methods, 639–640

integrated optical interconnect

delay analysis, 632–634

gate area analysis, 632, 633

link specification set, 631

optical point-to-point link

synthesis, 623, 626–630

performance metrics and

specification sets, 630–631

power analysis, 634–638

simulation and synthesis, 622–623,

624–625

simulation conditions, 632

synthesis procedures, 631

ITRS and design technology, 606–607

RuneIIproject

abstraction levels, 612–618

design technology, 608, 610

goals, 610–611

posteriori evaluation, 612

priori generation, 612

SoC/SiP design flow, 610–611

system-level and physical-level

phases, 611–612

UML/XML implementation,

618–622

several economic sectors, 604

silicon and system complexity, 604,

606

systems on chip (SoC), 603–604

Integrated optical interconnect

delay analysis, 632–634, 635

gate area analysis, 632, 633

link specification set, 631

optical point-to-point link synthesis

bit error rate (BER), 629

classes-definition, 626, 628

CMOS circuit, 623, 626

Morikuni formula, 627, 629

optical link sizing method,

626–627, 629

photonic devices, 630

physical implementation, 623, 627

scenarios, 628

schematic approach, 626

transistor-level synthesis method,

626–627

performance metrics and

specification sets, 630–631

power analysis

BPT, 634–636 link sizing method, 634

power vs interconnect length, 634,

636 static and dynamic power, 637–638

total power vs interconnect

length, 637 simulation and synthesis functional model, 622–623 optical device parameters, 623, 626 structural model, 622–623

UML class diagram, 623–625 Verilog-AMS, 623

simulation conditions, 632 synthesis procedures, 631 Interconnection bus for integrated

sensors (IBIS) communications, 699 drivers, 708–711 sensors, 714–715 structure, 711, 714 Internal configuration access port

(ICAP), 358, 370–372 International technology roadmap for

semiconductors (ITRS), 520 Inverse discrete cosine transformation

(IDCT) accelerator address map and interfacing code, 222–223

interfacing code and interrupt handler code, 223–224 macroblock decoding tasks, 221–222 types, 222

J

Just-in-time (JIT) compilation, 31

L

Linear electrical networks (LEN),

588–589 Linear multistep (LMS) methods, 575 Linear systems, hybrid automata autonomous, 398

convex polyhedron, 399 ellipsoids, 400

Minkowski sum, 400–401 reachability technique, 398–399 support functions, 399

zonotopes, 401

Linear temporal logic (LTL), 529

Linux

EDK designs

design constraints, 361–362

device trees, 362–363

managing partial reconfiguration

bitstreams, 372

ICAP device, 370

reconfiguration process, 371

LOC, see Logic of constraints

Logic of constraints (LOC) formula,

276–277

Lookup tables (LUTs), 355

Lower event-arrival function, η−, 61

M

MATLAB R, 22, 575

Memory-aware algorithms, 407

Message-passing interface (MPI), 208

Meta-variables, 99

METRO II design environment

academic approaches

BIP framework, 299–300

ForSyDe model, 298

FunState, 300

MILAN, 296

MoC/domains, 299

model-integrated computing

(MIC), 295–296

Ptolemy II and SystemC-H, 297

design elements

adaptors, 284

annotators and schedulers, 283

components, 280–282

constraint solvers, 282

mappers, 283–284

overview, 281

ports, 282

implementation, 280

industrial approaches, 294–295

intelligent buildings

electronic control units (ECUs),

315

function model and

OpenModelica, 314–315

goals, 313

room temperature control system,

313–314

origin, 292–293

overview behavior-performance orthogonalization, 278–279 heterogeneous IP import, 278 mapping specification, 279 semantics

mapping, 287–292 required/provided ports, 287 three-phase execution, 285–287 universal mobile telecommunications system (UMTS)

architectural modeling, 304–306 functional modeling, 301–303 mapped system, 306

results, 306–312 METROPOLIS design environment METROPOLIS meta-model (MMM) architecture modeling, 269–271 function modeling, 268–269 mapping, 271–273

recursive paradigm, platforms, 273–275

overview design activities, 267 syntactic and semantic mechanisms, 267–268 tools

formal property verification, 276

LOC-monitor technique, 276–277

quasi-static scheduling (QSS), 277 simulation, 275–276

Micro-electrical-mechanical (MEM)

systems 4f optoelectronic link, 666–667

BER vs frequency, 668–669

Chatoyant analysis, 667–668 CMOS drivers, 668

GLV system, 674–675 grating light valve (GLV), 674–679

insertion and crosstalk vs mechanical

tolerancing, 668–669 optical beam steering/alignment system, 668–674

vertical cavity surface emitting laser (VCSEL), 667–668

Micro-elevator by self assembly (MESA)

structure, 668–670

Microelectromechanical systems

(MEMS)

design methodology, 700–702

VHDL-AMS, 697–698

Microinstrument implementation, see

Smart sensors modeling

Mixed continuous and discrete systems

abstract semantics, 561

actor abstract semantics

communication operations,

565

postfire methods, 466,

564–465

prefire and fire, 564–465

Ptolemy II models, 564

setup, 564

Simulink S-function interface,

563–564

wrapup, 564

actor-oriented models

abstract syntax, 562

atomic actors, 562

communication, 562–563

composite actor and hierarchical

abstraction, 561–562

hierarchical abstraction, 562

priori configuration, 561–562

continuous-time (CT) dynamics

ContinuousStepSizeController

interface, 576

Euler methods, 575

first-order differential equations,

573

MATLAB R, 575

opaque composite actor, 576, 577

ordinary differential equations

(ODEs), 573

Runge-Kutta (RK) methods,

574–575

third-order nonlinear differential

equation, 573–574

discrete-event (DE) systems

approaches, 568–569

event queue, 571

functions, 570

mixed DE and SR model, 572–573

modal model, 573

setup phase/postfire method,

570–571

globally asynchronous/locally synchronous, 561 heterogeneous systems, 560 models of computation (MoCs), 560–561

software implementation, 576–578 synchronous/reactive models CountDown actor, 568 feedback system, 566 multiclock SR model, 568, 569 postfire, prefire and fire, 567 synchronous languages, 567 Mobile robots, sensor networks bus communication, 164 complete model, 165–167 evaluation, 167–168 hardware models, 161–163 physical scenario, 161 radio communication, 164–165 simulation model, 160–161 software components, 160 Model integrated computing (MIC),

295–296, 464, 465, 473 Modeling and analysis framework computation model

execution traces, 132 Huge State Space, 133–134 hyper-periods, 133 task characterization, 131 motivation

best-case and worst-case execution time, 124–125

cross-layer analysis, 124 multiprocessing timing anomaly, 124–125

MoVES analysis framework nondeterministic execution times, 140

overview, 122–123 simple multicore embedded system, 136–137

smart phones, 137–140 stopwatch model, 140–141 timed-automata model, 134 UPPAAL models

operating models, 123 support, 135–136 multiprocessor system-on-chip (MPSoC), 121

system-level models

application model, 126

execution platform model, 127–129

illustration, 126

memory and power model,

129–130

task mapping, 129

Models of computation (MoC), 522,

560–561

Modified nodal analysis (MNA), 650–652

Modular performance analysis, real-time

calculus

characteristics, 17

component model, 14–15

greedy shaper component (GSC), 16

modeling scheduling policies, 18

MPA framework, abstract

components, 15–16

system performance model, 16–17

transfer functions, 15–16

variability characterization curves

(VCCs)

arrival and service curves, 13–14

compact representation, 19–22

MONTIUM system-on-chip

average power consumption, 338

design methodology, 335–336

heterogeneous, 336–338

partial dynamic reconfiguration, 339

reconfigurable processing core

communication and configuration

unit (CCU), 333–334

tile processor (TP), 334–335

reference locality, 338–339

MoVES analysis framework

nondeterministic execution times, 140

overview, 122–123

simple multicore embedded system,

136–137

smart phones, 137–140

stopwatch model, 140–141

timed-automata model, 134

UPPAAL models

operating models, 123

support, 135–136

MPEG-2 video decoding tasks, 7

MPSoC platform mapping tools

3G application mapping experiments

block diagram, 198

load variance (LV) statistics, 200–201

manual and static mapping, 199 maximal communication (MC) statistics, 202

maximal load (ML) statistics, 201 total communication (TC) statistics, 200–201 versions, 199 causes, 180 MultiFlex mapping technology developments, 186

iterative mapping flow, 186–187 streaming programming model, 187–188

user-defined parallel applications, 185

MultiFlex streaming mapping flow abstraction levels, 189–190 application constraints, 191 functional capture, 190–191 high-level platform specification, 192

intermediate format, 192 model assumptions and distinctive features, 192–194

MultiFlex streaming mapping tools component back-end compilation, 197

MpAssign tool, 194–195 MpCompose tool, 195–197 runtime support components, 197–198

parallel multiprocessor characteristics heterogeneous composition, PE types, 185

RISC-style processors, 184 platform programming models advantages and drawbacks, 182–184

classes, 182 explicit capture of parallelism, 184 refinement and simulation, 202–203

MPSoCs, see Multiprocessor

system-on-chip Multi-domain systems on chips

(MDSoCs) Chatoyant multi-domain simulation, 646–679

HDL co-simulation environment,

680–689

system simulation, 644–645

Multi-viewpoint state machines

components and contracts

assumptions, 491

canonical form, 490, 492

implementation, 490

parallel composition, 491

synchronization, 492–495

contract-based specification, 489

extended state machines (ESMs)

continuous dynamics, 495–496

definition, 496–497

events and interactions, 495–496

input and outputs, 499

macrostates/locations, 501

openness, 500–501

product, 498

projection, 497–498

receptiveness, 499–500

runs, 497

union/disjunction, 498–499

variables and ports, 495–496

heterogeneous rich component (HRC)

definition, 501–503

labeling functions, 503–506

specialization, 507–515

original equipment manufacturers

(OEM), 488

system design, 489

Multicore architectures

advantages, 325–326

Aspex Linedancer

ASProCore architecture, 340–341

content addressable memory

(CAM), 339–340

design methodology, 342

hardware architecture, 341–342,

343

scalable architecture, 340–341

SIMD architectures, 340

classification

architectures, 332–333

building blocks, 332

flexibility vs performance, 330–331

interconnect structures, 332

multiprocessor system-on-chip

(MPSoC), 331–332

design criteria dependability, 330 energy efficiency, 328–329 predictable and composable, 327–328

programmability, 329–330 heterogenous SoC template, 325–326, 327

MONTIUM/ANNABELLE system-on-chip average power consumption, 338 design methodology, 335–336 heterogeneous, 336–338 partial dynamic reconfiguration, 339

reconfigurable processing core, 333–335

reference locality, 338–339 PACT-XPP

architecture, 343–344 design methodology, 344–345 streaming applications, 324–325 Tilera processor

design methodology, 346 features, 346

iMesh on-chip network, 346 tile64, 345

MultiFlex platform mapping technology developments, 186

iterative mapping flow, 186–187 streaming programming model, 187–188

user-defined parallel applications, 185 MultiFlex streaming mapping flow abstraction levels, 189–190 application constraints, 191 functional capture, 190–191 high-level platform specification, 192 intermediate format, 192

model assumptions and distinctive features, 192–194

stages, 188 MultiFlex streaming mapping tools component back-end compilation, 197 MpAssign tool, 194–195

MpCompose tool, 195–197 runtime support components, 197–198

MultiFlex toolset, 186–187

Multiprocessor system-on-chip

(MPSoC), 331–332

abstraction levels

system architecture level, 242–243

transaction accurate architecture

level, 244–245

virtual architecture level, 243

virtual prototype level, 245

aggregate busy time, 68–69

event models, 65–66

formal performance analysis

deriving aggregate busy time,

68–69

deriving output event models,

65–66

multicore component, 64

response time analysis, 66–68

hardware architecture, 235

hardware–software interface, 236–237

message passing organization, 234

modeling and analysis framework,

121

modern hardware systems, 121

performance analysis loop, 63

programming steps, 245–248

aspects, 245

description, 246–247

illustration, 246

response time analysis, 66–68

shared memory organization, 234

Simulink R- and SystemC-based

programming, 245–248

software architecture, 235–236

software development, 211–212

tasks, 64–65

N

Negation as failure (NAF), 448–449

Non-deterministic finite automaton

(NFA), 450

Noncausal methods, continuous

execution model, 526

ns-2 discrete-event simulator, 148

O

Open SystemC initiative (OSCI), 587

Optical beam steering/alignment system

Chatoyant, 670–671

MESA structures, 668–670

scanning mirror system, 669–670 scanning waveforms and diamond pattern, 670, 672

scratch drive actuator (SDA), 669 self-aligning system, 672–674 Ordinary differential equations (ODEs),

573, 652, 654 Original equipment manufacturers

(OEM), 488

P

PACT-XPP, 343–345 Parallel multiprocessor, SoC platform heterogeneous composition, PE types, 185

RISC-style processors, 184

PBD, see Platform-based design

PeaCE model, 220 Picture-in-picture (PiP) application, 7–9 Piecewise linear (PWL), 649

Platform-based design (PBD) and

frameworks design challenge, 261 METRO II design environment academic approaches, 295–300 design elements, 279–284 industrial approaches, 294–295 intelligent buildings, 313–315 origin, 292–293

overview, 278–279 semantics, 284–292 universal mobile telecommunications system (UMTS), 301–313

METROPOLIS design environment METROPOLIS meta-model (MMM), 268–275 overview, 267–268 tools, 275–277 principles definition, 262 design parameters, 266 flow concept, 263–264 fractal nature, 264–266 productivity, 262 system-level design (SLD), 260 Predictive technology model (PTM),

630–631 Preemption, 101–102

PriorityTA method, 470

Programming models, MPSoC

H.264 encoder

application and architecture

specification, 248–249

system architecture level, 249–250

transaction accurate architecture

level, 253–254

virtual architecture level, 250–252

virtual prototype level, 254–256

hardware architecture, 235

hardware–software interface,

236–237

heterogeneous

design flow, 232–233

processing units and

communication schemes, 231

requirements, 232

software development platform,

232–233

Simulink R- and SystemC-based

programming

abstraction levels, 241–245

MPSoC programming steps,

245–248

SoC design

models, 238

primitives, 239

programming levels, 238

software architecture, 235–236

Proportional/integral/derivative (PID)

controller, 462

Protothreads, 163

Ptolemy II design environment, 297

Pure scheduling simulator, 148

Q

Quality of service (QoS), 513–515

Quasi-static scheduling (QSS), 277

R

Rapidly-exploring random trees (RRTs)

algorithm, 408–409

hybrid distance, 410–411

iterations, 409–410

simulations, 409

Ray tracing techniques, 659

Rayleigh–Sommerfeld formulation, 663,

666

RBbots hardware architecture, 163

I2C bus, 164 types, 161–162 Retargetable, embedded software design

methodology CIC programming model architecture information file, 214–215

description, 209 program generation, 211 task code, 212–214 CIC translator generic API translation, 216–217 HW-interfacing code generation, 217

OpenMP translator, 217–218 scheduling code generation, 218–220

workflow, 215–216 experiments

architecture, 220 design space exploration, 220–221 HW-interfacing code generation, 221–223

productivity analysis, 224–227 scheduling code generation, 223–224

MPSoC software development, 211–212

parallel programming models characteristics, 210 design productivity, 208–209 message-passing model, 208 MultiFlex MPSoC programming environment, 209

shared address-space model, 208

SW architecture, 210 task-transaction-level (TTL) interface, 210

Rich component models, see

Multi-viewpoint state machines Robustness

data quality, 80 dynamic design robustness (DDR), 81–82

evaluation and optimization, 80–81 fault tolerance, 79

maintainability and extensibility, 80

reusability and modularity, 80

static design robustness (SDR), 81

RTC Toolbox

MATLAB libraries, 23

software architecture, 22

RunCS_TA method, 472

RuneIIproject

abstraction levels

AMS/MT hierarchy, 612–613,

614–615, 616

evaluation method, 617–618

functional level, 613–614

IP design process, 615, 617

modeling and structural

hierarchies, 613

single-level loop, 618

synthesis method, 617

design technology, 608, 610

goals, 610–611

posteriori evaluation, 612

priori generation, 612

SoC/SiP design flow, 610–611

system-level and physical-level

phases, 611–612

UML/XML implementation

AMS/MT IP blocks, 618–620, 622

class diagram, 620–621

GUI flowchart, 618–619

object management group (OMG),

618–619

Runge-Kutta (RK) methods, 574–575

S

Scalar diffractive models

computation time vs accuracy,

662–663

Helmholtz equation, 661

Maxwell equations, 659–660

modeling technique, 660

Rayleigh–Sommerfeld diffractive

formulation, 661–662

valid propagation, 661–662

wave equation, 661

Scenario-aware analysis

added and completed task, 74

compositional methodology, 75–76

echo effect, 74–75

unchanged task, 74

Schedulability analysis, UPPAAL

attributes, 100 framework model abstract task and resource models, 102–103

data structures, 103–104 resource template, 107–109 scheduling policies, 109–112 task template, 104–107 instantiation

schedulability problem, 114–115 schedulability query, 113 modeling language

features and stopwatches, 99 timed computation tree logic (TCTL), 99

train-gate model, 96–98 real-time model checking, 94 resources, 101–102

single-processor systems, 94 task dependencies, 100–101 time-triggered architecture (TTA), 94 Scratch drive actuator (SDA), 669

SDR, see Static design robustness

Self-reconfiguring platform (SRP),

358–359, 360, 361, 363, 364, 368, 372

Sensitivity analysis approach characterization, 76–77 performance slack modifications, 77 robustness optimization, 78 system dimensioning, 78 Shared address-space model, 208 SimEvents R 2 toolbox, 149 Simics system, 149

Simple multicore embedded system,

136–137 Simulation interfaces applications co-simulation framework, 549 distribution, 538–539

formalization and verification, 539–546

internal architecture, definition, 546–549

library elements, 550 methodology

co-simulation framework, 530–531 CTL and LTL, 529

distribution, 528

formalization, 529

internal architecture, 530

library elements, 531

verification, 528–529

Simulation-based approaches, 521–522

Simulink R model, mobile robots,

158, 167

Simulink R- and SystemC-based

programming environment

MPSoc abstraction levels

system architecture level, 242–243

transaction accurate architecture

level, 244–245

virtual architecture level, 243

virtual prototype level, 245

MPSoC programming steps

aspects, 245

description, 246–247

illustration, 246

Smart optical pixel transceiver (SPOT),

685–687, 688–689

Smart phones, 137–140

Smart sensors modeling

accelerometer

description, 704–706

IBIS drivers, 708, 710–711, 714

interface, 711

output circuitry, 706–708, 709, 710,

711, 712, 713, 714

application, 702–704

distributed architecture, 698–700

gyroscope, 711, 713

microelectromechanical systems

(MEMS), 697–698

design methodology, 700–702

simulation

and validation, 716, 717

gyroscope, 715–717

IBIS drivers, 714–715

VHDL-AMS models, 698

SoC, see System-on-chip

Software defined radio (SDR), 597–598

Static data flow (SDF), 646

Static design robustness (SDR), 81

Stochastic automata networks (SAN), 30

Stopwatch model, 99, 140–141

Streaming applications

characteristics, 324–325

dependability, 330 energy efficiency, 328–329 predictable and composable, 327–328 programmability, 329–330

Streaming programming model advantages and drawbacks, 182–183 data-dominated applications, 187 MultiFlex tool flow, 189

objectives, 188 Structural semantics specification,

DSMLs adding domain constraints derived functions, 456–458 NFA abstraction, 455 compositions and domains includes operator, 458–459 operators, 458–459 properties, 460–461 pseudo-coproduct operator, 460 pseudo-product operator, 459–460 renaming operator, 459

domains and models finite state machine (FSM), 449–450 non-deterministic finite automaton (NFA), 450

types, 451 expressive constraints definitions, 447 domain constraints, 449 expressions, 447

LP approaches, 446–447 negation as failure (NAF), 448–449 queries, 449

semantics, 448 logic programming (LP), 444–445 metamodeling language, 443 model contents

boolean composition, 454–455 negation as failure, 452–454 queries, 451–452

non-recursive and stratified, 445 operations, 444

signatures and terms, 445 syntax, 444

terms with types, 445–446 Symmetric multiprocessor (SMP) model,

182–183 System under test (SUT), 413–414,

420–421