CLAESSEN: SAT-Based Verification without State Space Traversal.In: Proceedings of the International Conference on Formal Methods in Computer-Aided Design FMCAD, Seiten 372–389, 2000.. In
Trang 152 BJESSE, P und K CLAESSEN: SAT-Based Verification without State Space Traversal.
In: Proceedings of the International Conference on Formal Methods in Computer-Aided
Design (FMCAD), Seiten 372–389, 2000.
53 BOULE, M und Z ZILIC: Efficient Automata-Based Assertion-Checker Synthesis of´
PSL Properties In: Proceedings of the High-Level Design Validation and Test Workshop (HLDVT), Seiten 69–76, 2006.
54 BOULE, M und Z ZILIC: Efficient Automata-Based Assertion-Checker Synthesis of´
SEREs for Hardware Emulation In: Proceedings of the Asia and South Pacific Design Automation Conference (ASPDAC), Seiten 324–329, 2007.
55 BOULE, M und Z ZILIC: Automata-Based Assertion-Checker Synthesis of PSL Pro-´
perties ACM Transactions on Design Automation of Electronic Systems (TODAES),
13(1):1–21, 2008
56 BOZZANO, M., R BRUTTOMESSO, A CIMATTI, T JUNTTILA, P VAN ROSSUM,
S SCHULZund R SEBASTIANI: An Incremental and Layered Procedure for the
Sa-tisfiability of Linear Arithmetic Logic In: Tools and Algorithms for the Construction and Analysis of Systems, Seiten 317–333 Springer, Berlin, Heidelberg, 2005.
57 BRACE, K S., R L RUDELLund R E BRYANT: Efficient Implementation of a BDD
Package In: Proceedings of the Design Automation Conference (DAC), Seiten 40–45,
1990
58 BRAND, D.: Verification of Large Synthesized Designs In: Proceedings of the
Interna-tional Conference on Computer-Aided Design (ICCAD), Seiten 534–537, 1993.
59 BRINKMANN, R und R DRECHSLER: RTL-Datapath Verification using Integer
Line-ar Programming In: Proceedings of the Asia and South Pacific Design Automation Conference (ASPDAC), Seiten 741–746, 2002.
60 BRYANT, R., D KROENING, J OUAKNINE, S A SESHIA, O STRICHMAN und
B BRADY: Deciding Bit-Vector Arithmetic with Abstraction In: Proceedings of the
International Conference on Tools and Algorithms for the Construction and Analysis of Systems (TACAS), Seiten 358–372, 2007.
61 BRYANT, R E.: Symbolic Verification of MOS Circuits In: Chapel Hill Conference on
VLSI, Seiten 419–438, 1985.
62 BRYANT, R E.: Graph-Based Algorithms for Boolean Function Manipulation IEEETransactions on Computers, 35(8):677–691, 1986
63 BRYANT, R E.: On the Complexity of VLSI Implementations and Graph
Representati-ons of Boolean FunctiRepresentati-ons with Application to Integer Multiplication IEEE TransactiRepresentati-ons
on Computers, 40(2):205–213, 1991
64 BRYANT, R E., D BEATTY, K BRACE, K CHO und T SHEFFLER: COSMOS: A
Compiled Simulator for MOS Circuits In: Proceedings of the Design Automation ference (DAC), Seiten 9–16, 1987.
Con-65 BRYANT, R E und Y.-A CHEN: Verification of Arithmetic Functions with Binary
Mo-ment Diagrams Technischer Bericht CS-94-160, Carnegie Mellon University, 1994.
66 BRYANT, R E und Y.-A CHEN: Verification of Arithmetic Circuits with Binary
Mo-ment Diagrams In: Proceedings of the Design Automation Conference (DAC), Seiten
535–541, 1995
67 BRYANT, R E., S GERMANund M N VELEV: Processor Verification Using
Effi-cient Reductions of the Logic of Uninterpreted Functions to Propositional Logic ACM
Transactions on Computational Logic (TOCL), 2(1):93–134, 2001
68 BRYANT, R E und M N VELEV: Verification of Pipelined Microprocessors by
Com-paring Memory Execution Sequences in Symbolic Simulation In: Proceedings of the Asian Computing Science Conference on Advances in Computing Science (ASIAN), Sei-
ten 18–31, 1997
Trang 269 BUCK, J., S HA, E A LEEund D G MESSERSCHMITT: Ptolemy: A Framework for
Simulating and Prototyping Heterogeneous Systems International Journal on Computer
Simulation, 4(2):155–182, 1994
70 BUCK, J T.: Scheduling Dynamic Dataflow Graphs with Bounded Memory Using the
Token Flow Model Doktorarbeit, Dept of EECS, UC Berkeley, Berkeley, CA 94720,
U.S.A., 1993
71 BURCH, J R.: Techniques for Verifying Superscalar Microprocessors In: Proceedings
of the Design Automation Conference (DAC), Seiten 552–557, 1996.
72 BURCH, J R., E M CLARKEund D E LONG: Symbolic Model Checking with
Par-titioned Transition Relations In: Proceedings of the International Conference on Very Large Scale Integration (VLSI), Seiten 49–58, 1991.
73 BURCH., J R., E M CLARKE, D E LONG, K L MCMILLANund D L DILL:
Symbolic Model Checking for Sequential Circuit Verification IEEE Transactions on
Computer-Aided Design of Integrated Circuits and Systems, 13(4):401–424, 1994
74 BURCH, J R., E M CLARKE, K L MCMILLAN, D L DILLund L J HWANG:
Symbolic Model Checking: 1020States and Beyond In: Proceedings of the Symposium
on Logic in Computer Science (LICS), Seiten 428–439, 1990.
75 BURCH, J R und D L DILL: Automatic Verification of Pipelined Microprocessor
Control In: Proceedings of the International Conference on Computer Aided
Verificati-on (CAV), Seiten 68–80, 1994.
76 BUSHNELL, M und V AGRAWAL: Essentials of Electronic Testing for Digital, Memory,
and Mixed-Signal VLSI Circuits Kluwer Academic Publishers, Norwell, Massachusetts,
U.S.A., 2000
77 BUSTAN, D., D FISMANund J HAVLICEK: Automata Construction for PSL scher Bericht, The Weizmann Institute of Science, 2005 Technical Report MCS05-04
Techni-78 BUTTAZZO, G.: Rate Monotonic vs EDF: Judgment Day In: Proceedings of the
Inter-national Conference on Embedded Software (EMSOFT), Seiten 67–83, 2003.
79 BUTTAZZO, G.: Hard Real-Time Computing Systems: Predictable Scheduling
Algo-rithms and Applications Springer, New York, NY, U.S.A., 2004.
80 CABODI, G., P CAMURATI, L LAVAGNOund S QUER: Disjunctive Partitioning and
Partial Iterative Squaring: An Effective Approach for Symbolic Traversal of Large cuits In: Proceedings of the Design Automation Conference (DAC), Seiten 728–733,
Cir-1997
81 CABODI, G., P CAMURATIund S QUER: Improved Reachability Analysis of Large
Finite State Machines In: Proceedings of the International Conference on Aided Design (ICCAD), Seiten 354–360, 1996.
Computer-82 CADAR, C., V GANESH, P M PAWLOWSKI, D L DILLund D R ENGLER: EXE:
Automatically Generating Inputs of Death In: Proceedings of the Conference on puter and Communications Security (CCS), Seiten 322–335, 2006.
Com-83 CARLONI, L P., K L MCMILLAN, A SALDANHA und A L VINCENTELLI: A Methodology for Correct-by-Construction Latency Insensitive Design
SANGIOVANNI-In: Proceedings of the International Conference on Computer-Aided Design (ICCAD),
Seiten 309–315, 1999
84 CARLONI, L P., K L MCMILLANund A L SANGIOVANNI-VINCENTELLI: Theory
of Latency-Insensitive Design IEEE Transactions on Computer-Aided Design of
Inte-grated Circuits and Systems, 20(9):1059–1076, 2001
85 CARLONI, L P und A L SANGIOVANNI-VINCENTELLI: Performance Analysis and
Optimization of Latency Insensitive Systems In: Proceedings of the Design Automation Conference (DAC), Seiten 361–367, 2000.
Trang 386 CARTER, W C., W H JOYNERund D BRAND: Symbolic simulation for correct
ma-chine design In: Proceedings of the Design Automation Conference (DAC), Seiten 280–
286, 1979
87 CASSANDRAS, C G und S LAFORTUNE: Introduction to Discrete Event Systems.Springer, New York, NY, U.S.A., 1999
88 CASSEZ, F und O.-H ROUX: Structural Translation from Time Petri Nets to Timed
Automata Electronic Notes in Theoretical Computer Science, 128(6):145–160, 2005.
89 CHAKI, S., E M CLARKE, J OUAKNINE, N SHARYGINAund N SINHA: State/
Event-Based Software Model Checking In: In Proceeding of the International rence on Integrated Formal Methods, Seiten 128–147, 2004.
Confe-90 CHETTO, H., M SILLY und T BOUCHENTOUF: Dynamic Scheduling of Real-Time
Tasks under Precedence Constraints Real-Time Systems, 2:325–346, 1990.
91 CHUSHO, T.: Test Data Selection and Quality Estimation Based on the Concept of
Es-sential Branches for Path Testing IEEE Transactions on Software Engineering,
SE-13(5):509–517, 1987
92 CIESIELSKI, M., P KALLAund S ASKAR: Taylor Expansion Diagrams: A Canonical
Representation for Verification of Data Flow Designs IEEE Transactions on Computers,
55(9):1188–1201, 2006
93 CIESIELSKI, M., P KALLA, Z ZENGund B ROUZEYRE: Taylor Expansion Diagrams:
A New Representation for RTL Verification In: Proceedings of the High-Level Design Validation and Test Workshop (HLDVT), Seiten 70–75, 2001.
94 CIESIELSKI, M., P KALLA, Z ZHENGund B ROUZEYRE: Taylor Expansion
Dia-grams: A Compact, Canonical Representation with Applications to Symbolic tion In: Proceedings of the Design, Automation and Test in Europe (DATE), Seiten
Verifica-285–289, 2002
95 CLAESSEN, K und J M ˚ARTENSSON: An Operational Semantics for Weak PSL In:
Proceedings of the International Conference on Formal Methods in Computer-Aided Design (FMCAD), Seiten 337–351, 2004.
96 CLARISO, R und J CORTADELLA: The Octahedron Abstract Domain Science of´Computer Programming, 64(1):115–139, 2006
97 CLARKE, E M und E A EMERSON: Design and Synthesis of Synchronization
Skele-tons Using Branching-Time Temporal Logic In: Processings of the Workshop on Logic
of Programs, Seiten 52–71, 1982.
98 CLARKE, E M., E A EMERSONund A P SISTLA: Automatic Verification of
Finite-State Concurrent Systems Using Temporal Logic Specifications ACM Transactions on
Programming Languages and Systems (TOPLAS), 8(2):244–263, 1986
99 CLARKE, E M., M FUJITA, P MCGEER, K L MCMILLAN, J YANGund X ZHAO:
Multi-Terminal Binary Decision Diagrams: An Efficient Data Structure for Matrix presentation In: Proceedings of the International Workshop on Logic Synthesis (IWLS),
Re-Seiten 1–15, 1993
100 CLARKE, E M., O GRUMBERG, S JHA, Y LU und H VEITH:
Counterexample-Guided Abstraction Refinement for Symbolic Model Checking Journal of the ACM,
50(5):752–794, 2003
101 CLARKE, E M., O GRUMBERGund D E LONG: Model Checking and Abstraction
In: Proceedings of the Symposium on Principles of Programming Languages (POPL),
Seiten 343–354, 1992
102 CLARKE, E M., D KROENINGund F LERDA: A Tool for Checking ANSI-C Programs
In: Proceedings of the International Conference on Tools and Algorithms for the
Con-struction and Analysis of Systems (TACAS), Seiten 168–176, 2004.
Trang 4103 CLARKE, E M., D KROENING, N SHARYGINAund K YORAV: Predicate
Abstrac-tion of ANSI-C Programs Using SAT Journal of Formal Methods in System Design,
25(2–3):105–127, 2004
104 CLARKE, E M., D KROENINGund K YORAV: Behavioral Consistency of C and
Verilog Programs Using Bounded Model Checking In: Proceedings of the Design tomation Conference (DAC), Seiten 368–371, 2003.
Au-105 CLARKE, E M., D KROENINGund K YORAV: Specifying and Verifying Systems with
Multiple Clocks In: Proceedings of the International Conference on Computer Design (ICCD), Seiten 48–55, 2003.
106 CLARKE, E M., K L MCMILLAN, X ZHAO, M FUJITAund J YANG: Spectral
Transforms for Large Boolean Functions with Applications to Technology Mapping In: Proceedings of the Design Automation Conference (DAC), Seiten 54–60, 1993.
107 CLARKE, E M., O.GRUMBERGund D A PELED: Model Checking MIT Press, bridge, MA, U.S.A., 1999
Cam-108 CLARKE, L A., J HASSELLund D J RICHARDSON: A Close Look at Domain Testing.IEEE Transactions on Software Engineering, 8(4):380–390, 1982
109 CLARKE, L A., A PODGURSKI, D J RICHARDSONund S J ZEIL: A Comparison
of Data Flow Path Selection Criteria In: Proceedings of the International Conference
on Software Engineering (ICSE), Seiten 28–30, 1985.
110 COCHET-TERRASSON, J., G COHEN, S GAUBERT, M MC GETTRICK und J.-P.QUADRAT: Numerical Computation of Spectral Elements in Max-Plus Algebra In: Pro-
ceedings of the Conference on System Structure and Control, Seiten 667–674, 1998.
111 COELHOJR., C N und H D FOSTER: Assertion-Based Verification – Property
Spe-cification In: Advanced Formal Verification, Seiten 167–204 Kluwer Academic
Publis-hers, Boston, 2004
112 COHEN, G., D DUBOIS, J QUADRATund M VIOT: A Linear-System-Theoretic View
of Discrete-Event Processes and its Use for Performance Evaluation in Manufacturing.
IEEE Transactions on Automatic Control, 30(3):210–220, 1985
113 COMMONER, F., A W HOLT, S EVENund A PNUELI: Marked Directed Graphs.Journal of Computer and System Sciences, 5:511–523, 1971
114 COOK, B., D KROENINGund N SHARYGINA: Cogent: Accurate Theorem Proving
for Program Verification In: Proceedings of the International Conference on Computer Aided Verification (CAV), Seiten 296–300, 2005.
115 COOK, B., D KROENINGund N SHARYGINA: Symbolic Model Checking for
Asyn-chronous Boolean Programs In: Proceedings of the International SPIN Workshop
(SPIN), Seiten 75–90, 2005.
116 COOK, S A.: The Complexity of Theorem-Proving Procedures In: Proceedings of the
Symposium on Theory of Computing (STOC), Seiten 151–158, 1971.
117 COUDERT, O., C BERTHETund J C MADRE: Verification of Synchronous Sequential
Machines Based on Symbolic Execution In: Proceedings of the International Workshop
on Automatic Verification Methods for Finite State Systems, Seiten 365–373, 1990.
118 COUSOT, P und R COUSOT: Abstract Interpretation: A Unified Lattice Model for Static
Analysis of Programs by Construction or Approximation of Fixpoints In: Proceedings
of the Symposium on Principles of Programming Languages (POPL), Seiten 238–252,
1977
119 COUSOT, P und R COUSOT: Systematic Design of Program Analysis Frameworks
In: Proceedings of the Symposium on Principles of Programming Languages (POPL),
Seiten 269–282, 1979
Trang 5120 COUSOT, P und N HALBWACHS: Automatic Discovery of Linear Restraints Among
Va-riables of a Program In: Proceedings of the Symposium on Principles of Programming Languages (POPL), Seiten 84–96, 1978.
121 CRUZ, R L.: A Calculus for Network Delay, Part I: Network Elements in Isolation.IEEE Transactions on Information Theory, 37(1):114–131, 1991
122 CURRIE, D W., X FENG, M FUJITA, A J HU, M KWANund S RAJAN: Embedded
Software Verification Using Symbolic Execution and Uninterpreted Functions
Interna-tional Journal of Parallel Programming, 34(1):61–91, 2006
123 CURRIE, D W., A J HU, S RAJANund M FUJITA: Automatic Formal Verification
of DSP Software In: Proceedings of the Design Automation Conference (DAC), Seiten
130–135, 2000
124 CYRLUK, D., O M ¨OLLER und H RUESS: An Efficient Decision Procedure for the
Theory of Fixed-Sized Bit-Vectors In: Proceedings of the International Conference on Computer Aided Verification (CAV), Seiten 60–71, 1997.
125 CYTRON, R., J FERRANTE, B K ROSEN, M N WEGMANund F K ZADECK:
Effi-ciently Computing Static Single Assignment Form and the Control Dependence Graph.
ACM Transactions on Programming Languages and Systems (TOPLAS), 13(4):451–
490, 1991
126 DAHAN, A., D GEIST, L GLUHOVSKY, D PIDAN, G SHAPIR, Y WOLFSTHAL,
L BENALYCHERIF, R KAMIDEMund Y LAHBIB: Combining System Level Modeling
with Assertion Based Verification In: Proceedings of the International Symposium on Quality of Electronic Design (ISQED), Seiten 310–315, 2005.
127 DANIELE, M., F GIUNCHIGLIAund M Y VARDI: Improved Automata Generation for
Linear Temporal Logic In: Proceedings of the International Conference on Computer Aided Verification (CAV), Seiten 249–260, 1999.
128 DAVIS, M., G LOGEMANN und D LOVELAND: A Machine Program for
Theorem-Proving Communications of the ACM, 5(7):394–397, 1962.
129 DAVIS, M und H PUTNAM: A Computing Procedure for Quantification Theory nal of the ACM, 7(3):201–215, 1960
Jour-130 DEHARBE, D und S RANISE: Light-Weight Theorem Proving for Debugging and
Ve-rifying Units of Code In: Proceedings of the Conference on Software Engineering and Formal Methods, Seiten 220–228, 2003.
131 DETLEFS, D., G NELSONund J B SAXE: Simplify: A Theorem Prover for Program
Checking Journal of the ACM, 52(3):365–473, 2005.
132 DILL, D L.: Timing Assumptions and Verification of Finite-State Concurrent Systems
In: Proceedings of the International Workshop on Automatic Verification Methods for
Finite State Systems, Seiten 197–212, 1990.
133 DONLIN, A.: Transaction Level Modeling: Flows and Use Models In: Proceedings of
the Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS),
Seiten 75–80, 2004
134 DRECHSLER, R und B BECKER: Overview of Decision Diagrams IEE Proceedings
on Computers and Digital Techniques, 144(3):187–193, 1997
135 DRECHSLER, R und B BECKER: Binary Decision Diagrams – Theory and
Implemen-tation Kluwer Academic Publishers, Dordrecht, The Netherlands, 1998.
136 DRECHSLER, R., B BECKERund S RUPPERTZ: K*BMDs: A New Data Structure for
Verification In: Proceedings of the European Conference on Design and Test (EDTC),
Seiten 2–8, 1996
137 DRECHSLER, R., S EGGERSGLUSS, G FEY, J SCHL¨ OFFEL¨ und D TILLE: Effiziente
Erf¨ullbarkeitsalgorithmen f¨ur die Generierung von Testmustern it – information
tech-nology, 51(2):102–111, 2009
Trang 6138 DRECHSLER, R., A SARABI, M THEOBALD, B BECKERund M A PERKOWSKI:
Efficient Representation and Manipulation of Switching Functions Based on Ordered Kronecker Functional Decision Diagrams In: Proceedings of the Design Automation Conference (DAC), Seiten 415–419, 1994.
139 DRECHSLER, R., M THEOBALDund B BECKER: Fast OFDD based Minimization of
Fixed Polarity Reed-Muller Expressions In: Proceedings of the European Conference
on Design Automation (ECDA), Seiten 2–7, 1994.
140 D’SILVA, V., D KROENINGund G WEISSENBACHER: A Survey of Automated
Tech-niques for Formal Software Verification IEEE Transactions on Computer-Aided Design
of Integrated Circuits and Systems, 27(7):1165–1178, 2008
141 DUBOIS, O., P ANDRE, Y BOUFKHADund J CARLIER: SAT versus UNSAT In:JOHNSON, D S und M A TRICK(Herausgeber): Second DIMACS Implementation
Challenge, Band 26 der Reihe Series in Discrete Mathematics and Theoretical Computer Science (DIMACS), Seiten 415–434 American Mathematical Society, 1996.
142 DUTERTRE, B und L.DEMOURA: A Fast Linear-Arithmetic Solver for DPLL(T) In:
Proceedings of the International Conference on Computer Aided Verification (CAV),
Seiten 81–94, 2006
143 ECKER, W., V ESEN, T STEININGER, M VELTENund M HULL: Execution
Seman-tics and Formalisms for Multi-Abstraction TLM Assertions In: Proceedings of the ternational Conference on Formal Methods and Models for Co-Design (MEMOCODE),
In-Seiten 93–102, 2006
144 ECKER, W., V ESEN, T STEININGER, M VELTENund M HULL: Implementation of
a Transaction Level Assertion Framework in SystemC In: Proceedings of the Design, Automation and Test in Europe (DATE), Seiten 1–6, 2007.
145 EIJK, C A J.VAN: Formal Methods for the Verification of Digital Circuits beit, Eindhoven University of Technology, The Netherlands, 1997
Doktorar-146 EIJK, C A J VAN: Sequential Equivalence Checking based on Structural
Similari-ties IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems,
19(7):814–819, 2000
147 EKER, J., J W JANNECK, E A LEE, J LIU, X LIU, J LUDVIG, S NEUENDORFFER,
S SACHSund Y XIONG: Taming Heterogeneity – the Ptolemy Approach Proceedings
of the IEEE, 91(1):127–144, 2003
148 EMERSON, E A.: Temporal and Modal Logic In: Formal Models and Semantics,
Band B der Reihe Handbook of Theoretical Computer Science, Seiten 995–1072 MIT
Press, Cambridge, MA, U.S.A., 1990
149 EMERSON, E A und E M CLARKE: Characterizing Correctness Properties of
Par-allel Programs Using Fixpoints In: Proceedings of the Colloquium on Automata, guages and Programming, Seiten 169–181, 1980.
Lan-150 EMERSON, E A und J Y HALPERN: ”Sometimes” and ”Not Never” Revisited: On
Branching versus Linear Time In: Proceedings of the Symposium on Principles of gramming Languages (POPL), Seiten 127–140, 1983.
Pro-151 EMERSON, E A., A K MOK, A P SISTLAund J SRINIVASAN: Quantitative
Tem-poral Reasoning In: Proceedings of the International Conference on Computer Aided Verification (CAV), Seiten 136–145, 1990.
152 EMERSON, E A und R J TREFLER: Parametric Quantitative Temporal Reasoning
In: Proceedings of the Symposium on Logic in Computer Science (LICS), Seiten 336–
343, 1999
153 ENGELS, M., G BILSEN, R LAUWEREINSund J PEPERSTRAETE: Cyclo-Static
Da-ta Flow: Model and ImplemenDa-tation In: Proceedings of the Asilomar Conference on Signals, Systems, and Computers, Seiten 503–507, 1994.
Trang 7154 ERNST, R und W YE: Embedded Program Timing Analysis Based on Path Clustering
and Architecture Classification In: Proceedings of the International Conference on Computer-Aided Design (ICCAD), Seiten 598–604, 1997.
155 ESPARZA, J.: Model Checking Using Net Unfoldings In: Proceedings of the Conference
on Theory and Practice of Software Development (TAPSOFT), Seiten 613–628, 1993.
156 EVANS, A., A SILBURT, G VRCKOVNIK, T BROWN, M DUFRESNE, G HALL,
T HOund Y LIU: Functional Verification of Large ASICs In: Proceedings of the
Design Automation Conference (DAC), Seiten 650–655, 1998.
157 FALK, J., C HAUBELT und J TEICH: Efficient Representation and Simulation of
Model-Based Designs in SystemC In: Proceedings of the Forum on Design ges (FDL), Seiten 129–134, 2006.
Langua-158 FEAUTRIER, P.: Array Expansion In: Proceedings of the International Conference on
Supercomputing (ICS), Seiten 429–441, 1988.
159 FENG, X und A J HU: Automatic Formal Verification for Scheduled VLIW Code
In: Proceedings of the Conference on Languages, Compilers and Tools for Embedded
Systems (SCOPES), Seiten 85–92, 2002.
160 FENG, X und A J HU: Cutpoints for Formal Equivalence Verification of Embedded
Software In: Proceedings of the International Conference on Embedded Software SOFT), Seiten 307–316, 2005.
(EM-161 FENG, X und A J HU: Early Cutpoint Insertion for High-Level Software vs RTL
For-mal Combinational Equivalence Verification In: Proceedings of the Design Automation Conference (DAC), Seiten 1063–1068, 2006.
162 FETTWEIS, A.: Realizability of Digital Filter Networks Archiv Elek ¨Ubertragung,30(2):90–96, 1976
163 FEY, G., R DRECHSLERund M CIESIELSKI: Algorithms for Taylor Expansion
Dia-grams In: Proceedings of the International Symposium on Multiple-Valued Logic
(ISMVL), Seiten 235–240, 2004.
164 FLANAGAN, C., R JOSHI, X OUund J B SAXE: Theorem Proving Using Lazy Proof
Explication In: Proceedings of the International Conference on Computer Aided cation (CAV), Seiten 355–367, 2003.
Verifi-165 http://www.flexray.com
166 FLOYD, R W.: Assigning Meaning to Programs In: Proceedings of the Symposium of
Applied Mathematics, Seiten 19–32, 1967.
167 http://www.haifa.ibm.com/projects/verification/focs/
168 FOSTER, H D., A C KROLNIKund D J LACEY: Assertion-Based Design KluwerAcademic Publishers, Dordrecht, The Netherlands, 2004 2 Auflage
169 FOWLER, M und K SCOTT: UML Distilled: Applying the Standard Object Modeling
Language Addison-Wesley, Reading, MA, U.S.A., 1997.
170 GAJSKI, D D und R H KUHN: New VLSI Tools IEEE Computer, 16(12):11–14,1983
171 GAJSKI, D D., F VAHID, S NARAYANund J GONG: Specification and Design of
Embedded Systems Prentice-Hall, Inc., Upper Saddle River, NJ, U.S.A., 1994.
172 GAJSKI, D D., J ZHU, R D ¨OMER, A GERSTLAUERund S ZHAO: SpecC:
Specifi-cation Language and Design Methodology Kluwer Academic Publishers, 2000.
173 GANAI, M K und A AZIZ: Improved SAT-Based Bounded Reachability Analysis In:
Proceedings of the Asia and South Pacific Design Automation Conference (ASPDAC),
Seiten 729–734, 2002
174 GANAI, M K und A GUPTA: SAT-based Scalable Formal Verification Solutions.Springer, New York, NY, U.S.A., 2007
Trang 8175 GANAI, M K., A GUPTAund P ASHAR: Efficient Modeling of Embedded Memories in
Bounded Model Checking In: Proceedings of the International Conference on Computer Aided Verification (CAV), Seiten 440–452, 2004.
176 GANAI, M K., A GUPTAund P ASHAR: Beyond Safety: Customized SAT-Based
Mo-del Checking In: Proceedings of the Design Automation Conference (DAC), Seiten
738–743, 2005
177 GANAI, M K., A GUPTAund P ASHAR: Verification of Embedded Memory Systems
using Efficient Memory Modeling In: Proceedings of the Design, Automation and Test
in Europe (DATE), Seiten 1096–1101, 2005.
178 GANAI, M K., M TALUPURund A GUPTA: SDSAT: Tight Integration of Small
Do-main Encoding and Lazy Approaches in a Separation Logic Solver In: Tools and rithms for the Construction and Analysis of Systems, Seiten 135–150 Springer, Berlin,
Algo-Heidelberg, 2006
179 GANESH, V und D L DILL: A Decision Procedure for Bit-Vectors and Arrays In:
Proceedings of the International Conference on Computer Aided Verification (CAV),
Seiten 524–536, 2007
180 GAREY, M R und D S JOHNSON: Computers and Intractability: A Guide to the
Theory of NP-Completeness Freeman, New York, NY, U.S.A., 1979.
181 GASTIN, P und D ODDOUX: Fast LTL to B¨uchi Automata Translation In: Proceedings
of the International Conference on Computer Aided Verification (CAV), Seiten 53–65,
2001
182 GERSTLAUER, A., C HAUBELT, A D PIMENTEL, T P STEFANOV, D D GAJSKIund J TEICH: Electronic System-Level Synthesis Methodologies IEEE Transactions onComputer-Aided Design of Integrated Circuits and Systems, 28(10):1517–1530, 2009
183 GERTH, R., D PELED, M Y VARDIund P WOLPER: Simple On-the-Fly Automatic
Verification of Linear Temporal Logic In: Proceedings of the International Symposium
on Protocol Specification, Testing and Verification, Seiten 3–18, 1996.
184 GHAMARIAN, A H.: Timing Analysis of Synchronous Data Flow Graphs Doktorarbeit,Eindhoven University of Technology, The Netherlands, 2008
185 GHAMARIAN, A H., M C W GEILEN, S STUIJK, T BASTEN, A J M MOONEN,
M J G BEKOOIJ, B D THEELENund M R MOUSAVI: Throughput Analysis of
Synchronous Data Flow Graphs In: Proceedings of the International Conference on Application of Concurrency to System Design (ACSD), Seiten 25–36, 2006.
186 GHAMARIAN, A H., S STUIJK, T BASTEN, M C W GEILENund B D THEELEN:
Latency Minimization for Synchronous Data Flow Graphs In: Proceedings of the romicro Conference on Digital System Design Architectures, Methods and Tools (DSD),
Eu-Seiten 189–196, 2007
187 GHEORGHITA, S V und R GRIGORE: Constructing Checkers from PSL Properties
In: In Proceedings of the International Conference on Control Systems and Computer
Science, Seiten 757–762, 2005.
188 GIANNAKOPOULOU, D und F LERDA: From States to Transitions: Improving
Trans-lation of LTL Formulae to B¨uchi Automata In: Proceedings of the International ference on Formal Techniques for Networked and Distributed Systems (FORTE), Seiten
Con-308–326, 2002
189 GIRAULT, C und R VALK: Petri Nets for Systems Engineering – A Guide to Modeling,
Verification, and Application Springer, Berlin, Heidelberg, New York, 2003.
190 GIRGIS, M und M WOODWARD: An Experimental Comparison of the Error
Expo-sing Ability of Program Testing Criteria In: Proceedings of the Workshop on Software Testing, Seiten 64–73, 1986.
Trang 9191 GLADIGAU, J., F BLENDINGER, C HAUBELT und J TEICH: Symbolische
Modell-pr¨ufung Aktor-orientierter High-level SystemC-Modelle mit Intervalldiagrammen In: Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltun- gen und Systemen, Seiten 109–118, 2008.
192 GLADIGAU, J., C HAUBELTund J TEICH: Symbolic Scheduling of SystemC Dataflow
Designs In: Languages for Embedded Systems and their Applications, Band 36 der
Reihe Lecture Notes in Electrical Engineering, Seiten 183–199 Springer, 2009.
193 GLADIGAU, JENS: Symbolische Ablaufplanung von SysteMoC-Beschreibungen plomarbeit, Department of Computer Science, University of Erlangen-Nuremberg, 2006
Di-194 GODEFROID, P.: Partial-Order Methods for the Verification of Concurrent Systems: An
Approach to the State-Explosion Problem Springer, New York, NY, U.S.A., 1996.
195 GODEFROID, P.: Model Checking for Programming Languages Using VeriSoft In:
Pro-ceedings of the Symposium on Principles of Programming Languages (POPL), Seiten
174–186, 1997
196 GODEFROID, P und P WOLPER: A Partial Approach to Model Checking In:
Procee-dings of the Symposium on Logic in Computer Science (LICS), Seiten 406–415, 1991.
197 GODEFROID, P und P WOLPER: Using Partial Orders for the Efficient Verification of
Deadlock Freedom and Safety Properties Journal of Formal Methods in System Design,
2(2):149–164, 1993
198 G ¨ODEL, KURT: ¨Uber formal unentscheidbare S¨atze der Principia Mathematica und verwandter Systeme I Monatshefte f¨ur Mathematik und Physik, 38:173–198, 1931.
199 GOEL, A und R E BRYANT: Set Manipulation with Boolean Functional Vectors for
Symbolic Reachability Analysis In: Proceedings of the Design, Automation and Test in Europe (DATE), Seiten 10816–10821, 2003.
200 GOEL, A., K SAJID, H ZHOU, A AZIZund V SINGHAL: BDD Based Procedures
for a Theory of Equality with Uninterpreted Functions Journal of Formal Methods in
System Design, 22(3):205–224, 2003
201 GOLDBERG, E und Y NOVIKOV: BerkMin: A Fast and Robust SAT-solver In:
Procee-dings of the Design, Automation and Test in Europe (DATE), Seiten 142–149, 2002.
202 GOMEZ-PRADO, D., Q REN, S ASKAR, M CIESIELSKIund E BOUTILLON:
Varia-ble Ordering for Taylor Expansion Diagrams In: Proceedings of the High-Level Design Validation and Test Workshop (HLDVT), Seiten 55–59, 2004.
203 GORDON, M., JOEHURDund K SLIND: Executing the Formal Semantics of the
Accel-lera Property Specification Language by Mechanised Theorem Proving In: Proceedings
of the Conference on Correct Hardware Design and Verification Methods, Seiten 200–
215, 2003
204 GOVINDARAJAN, R und G R GAO: Rate-Optimal Schedule for Multi-Rate DSP
Com-putations Journal of VLSI Signal Processing Systems, 9(3):211–232, 1995.
205 GRAF, S und H SA¨IDI: Construction of Abstract State Graphs with PVS In:
Pro-ceedings of the International Conference on Computer Aided Verification (CAV), Seiten
72–83, 1997
206 GROSSE, D und R DRECHSLER: Ein Ansatz zur formalen Verifikation von
Schaltungs-beschreibungen in SystemC it - Information Technology, 45(4):219–226, 2003.
207 GROTKER, T., S LIAO, G MARTIN¨ und S SWAN: System Design with SystemC wer Academic Publishers, Norwell, Massachusetts, Dordrecht, 2002
Klu-208 GUPTA, A und P ASHAR: Integrating a Boolean Satisfiability Checker and BDDs for
Combinational Equivalence Checking In: Proceedings of the International Conference
on VLSI Design (VLSID), Seiten 222–225, 1998.
Trang 10209 GUPTA, A., M GANAI, Z YANGund P ASHAR: Iterative Abstraction using
SAT-based BMC with Proof Analysis In: Proceedings of the International Conference on Computer-Aided Design (ICCAD), Seiten 416–423, 2003.
210 HABIBI, A und S TAHAR: Design and Verification of SystemC Transaction-Level
Mo-dels IEEE Transactions on Very Large Scale Integrated Systems, 14(1):57–68, 2006.
211 HACHTEL, G D und F SOMENZI: Logic Synthesis and Verification Algorithms wer Academic Publishers, Norwell, Massachusetts 02061 U.S.A., 1996
Klu-212 HALBWACHS, N., P CASPI, P RAYMONDund D PILAUD: The Synchronous Data
Flow Programming Language LUSTRE Proceedings of the IEEE, 79(9):1305–1320,
1991
213 HALBWACHS, N., Y.-E PROY und P ROUMANOFF: Verification of Real-Time
Sys-tems using Linear Relation Analysis Journal of Formal Methods in System Design,
11(2):157–185, 1997
214 HAMAGUCHI, K., A MORITAund S YAJIMA: Efficient Construction of Binary
Mo-ment Diagrams for Verifying Arithmetic Circuits In: Proceedings of the International Conference on Computer-Aided Design (ICCAD), Seiten 78–82, 1995.
215 HAUBELT, C., J FALK, J KEINERT, T SCHLICHTER, M STREUBUHR, A DEYHLE,¨
A HADERTund J TEICH: A SystemC-based Design Methodology for Digital Signal
Processing Systems EURASIP Journal on Embedded Systems, Special Issue on
Em-bedded Digital Signal Processing Systems, 2007
216 HAUBELT, C., M MEREDITH, T SCHLICHTERund J KEINERT: SystemCoDesigner:
Automatic Design Space Exploration and Rapid Prototyping from Behavioral Models.
In: Proceedings of the Design Automation Conference (DAC), Seiten 580–585, 2008.
217 HENIA, R., A HAMANN, M JERSAK, R RACU, K RICHTERund R ERNST: System
Level Performance Analysis – The SymTA/S Approach IEE Proceedings on Computers
and Digital Techniques, 152(2):148–166, 2005
218 HENZINGER, T A., X NICOLLIN, J SIFAKIS und S YOVINE: Symbolic Model
Checking for Real-Time Systems Information and Computation, 111(2):193–244, 1994.
219 HERBER, P., J FELLMUTHund S GLESNER: Model Checking SystemC Designs Using
Timed Automata In: Proceedings of the Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), Seiten 131–136, 2008.
220 HIND, M.: Pointer Analysis: Haven’t We Solved this Problem Yet? In: Proceedings of
the Workshop on Program Analysis for Software Tools and Engineering (PASTE), Seiten
Engi-223 HOPCROFT, J E., R MOTWANIund J D ULLMAN: Einf¨uhrung in die
Automaten-theorie, Formale Sprachen und Komplexit¨atstheorie Pearson Studium, Deutschland,
M¨unchen, 2002 2 Auflage
224 H ¨ORETH, S und R DRECHSLER: Formal Verification of Word-Level Specifications In:
Proceedings of the Design, Automation and Test in Europe (DATE), Seiten 52–58, 1999.
225 HORN, W A.: Some Simple Scheduling Algorithms Naval Research Logistics
Quarter-ly, 21:177–185, 1974
226 HORWITZ, S., T REPSund D BINKLEY: Interprocedural Slicing Using Dependence
Graphs In: Proceedings of the Conference on Programming Language Design and Implementation (PLDI), Seiten 35–46, 1988.
227 HOWDEN, W E.: Theoretical and Empirical Studies of Program Testing IEEE sactions on Software Engineering, SE-4(4):293–298, 1978
Trang 11Tran-228 HOWDEN, W E.: Theoretical and Empirical Studies of Program Testing In:
Procee-dings of the International Conference on Software Engineering (ICSE), Seiten 305–311,
1978
229 HU, A J.: High-Level vs RTL Combinational Equivalence: An Introduction In:
Pro-ceedings of the International Conference on Computer Design (ICCD), Seiten 274–279,
2007
230 HUANG, C.-Y und K.-T CHENG: Assertion Checking by Combined Word-Level ATPG
and Modular Arithmetic Constraint-Solving Techniques In: Proceedings of the Design Automation Conference (DAC), Seiten 118–123, 2000.
231 IBARRA, O H und S MORAN: Probabilistic Algorithms for Deciding Equivalence of
Straight-Line Programs Journal of the ACM, 30(1):217–228, 1983.
232 IEEE: IEEE Standard Glossary of Software Engineering Terminology. IEEE Std610.12-1990, 1990
233 IEEE: IEEE Standard VHDL Language Reference Manual IEEE Std 1076-1993, 1993.
234 IEEE: IEEE Standard for Property Specification Language (PSL) IEEE Std 1850, 2005.
235 IEEE: IEEE Standard for SystemVerilog – Unified Hardware Design, Specification, and
Verification Language IEEE Std 1800, 2005.
236 IEEE: IEEE Standard SystemC Language Reference Manual IEEE Std 1666, 2006.
237 http://www.cadence.com/products/fv/design team simulator/
238 http://www.cadence.com/products/fv/formal verifier/
239 ISHIURA, N., H SAWADAund S YAJIMA: Minimization of Binary Decision Diagrams
based on Exchanges of Variables In: Proceedings of the International Conference on Computer-Aided Design (ICCAD), Seiten 472–475, 1991.
240 ITRS: International Technology Roadmap for Semiconductors – System Drivers
Tech-nischer Bericht, ITRS, 2007 http://www.itrs.net/
241 IVANCIˇ C, F., I SHLYAKHTER, A GUPTA, M K GANAI, V KAHLON, C WANG´ und
Z YANG: Model Checking C Programs using F-Soft In: Proceedings of the
Internatio-nal Conference on Computer Design (ICCD), Seiten 297–308, 2005.
242 IVANCIˇ C, F., Z YANG, M K GANAI, A GUPTA´ und P ASHAR: Efficient SAT-Based
Bounded Model Checking for Software Verification Theoretical Computer Science,
404(3):256–274, 2008
243 JACKSON, J R.: Scheduling a Production Line to Minimize Maximum Tardiness nischer Bericht 43, University of California, Los Angeles, 1955
Tech-244 JAIN, H., D KROENINGund E M CLARKE: Verification of SpecC Using Predicate
Abstraction In: Proceedings of the International Conference on Formal Methods and Models for Co-Design (MEMOCODE), Seiten 7–16, 2004.
245 JAIN, J., A NARAYAN, C COELHO, S P KHATRI, A L TELLI, R K BRAYTON und M FUJITA: Decomposition Techniques for Efficient
SANGIOVANNI-VINCEN-ROBDD Construction In: Proceedings of the International Conference on Formal thods in Computer-Aided Design (FMCAD), Seiten 419–434, 1996.
Me-246 JALOTE, P.: Fault Tolerance in Distributed Systems Prentice-Hall, Inc., Upper SaddleRiver, NJ, U.S.A., 1994
247 JERSAK, M.: Compositional Performance Analysis for Complex Embedded
Applicati-ons Doktorarbeit, Technische Universit¨at Braunschweig, Deutschland, 2005.
248 JONES, N D und S S MUCHNICK: Flow Analysis and Optimization of LISP-like
Structures In: Proceedings of the Symposium on Principles of Programming Languages (POPL), Seiten 244–256, 1979.
249 JOSEPH, M und P PANDYA: Finding Response Times in a Real-Time System TheComputer Journal, 29(5):390–395, 1986
Trang 12250 KAHN, G.: The Semantics of a Simple Language for Parallel Programming In:
Procee-dings of the IFIP Congress, Seiten 471–475, Stockholm, Sweden, 1974.
251 KALLA, P., M CIESIELSKI, E BOUTILLONund E MARTIN: High-Level Design
Veri-fication Using Taylor Expansion Diagrams: First Results In: Proceedings of the Level Design Validation and Test Workshop (HLDVT), Seiten 13–17, 2002.
High-252 KATZ, S und D PELED: Verification of Distributed Programs Using Representative
Interleaving Sequences Journal of Distributed Computing, 6(2):107–120, 1992.
253 KEBSCHULL, U., E SCHUBERTund W ROSENSTIEL: Multilevel Logic Synthesis
ba-sed on Functional Decision Diagrams In: Proceedings of the European Conference on Design Automation (ECDA), Seiten 43–47, 1992.
254 KEINERT, J., M STREUBUHR, T SCHLICHTER, J FALK, J GLADIGAU, C HAU-¨BELT, J TEICHund M MEREDITH: SystemCoDesigner - An Automatic ESL Synthesis
Approach by Design Space Exploration and Behavioral Synthesis for Streaming cations ACM Transactions on Design Automation of Electronic Systems (TODAES),
Appli-14(1):1–23, 2009
255 KELLY, J C und K KEMP: Formal Methods Specification and Verification
Guide-book for Software and Computer Systems, Volume I: Planning and Technology Insertion.
Technischer Bericht NASA-GB-002-95, NASA, Office of Safety and Mission
Assuran-ce, 1995
256 KEMPF, T., M DOERPER, R LEUPERS, G ASCHEID, H MEYR, T KOGEL und
B VANTHOURNOUT: A Modular Simulation Framework for Spatial and Temporal Task
Mapping onto Multi-Processor SoC Platforms In: Proceedings of the Design, tion and Test in Europe (DATE), Seiten 876–881, 2005.
Automa-257 KERNIGHAN, B W und D RITCHIE: The C Programming Language Prentice-Hall,Inc., Upper Saddle River, NJ, U.S.A., 1988 2 Auflage
258 KIENHUIS, B., E DEPRETTERE, K VISSERSund P.VAN DERWOLF: An Approach for
Quantitative Analysis of Application-Specific Dataflow Architectures In: Proceedings of the Conference on Application-Specific Systems, Architectures and Processors (ASAP),
Seiten 338–349, 1997
259 KINDLER, E und T VESPER: ESTL: A Temporal Logic for Events and States In:
Proceedings of the International Conference on Application and Theory of Petri Nets (ICATPN), Seiten 365–384, 1998.
260 KING, J C.: Symbolic Execution and Program Testing Communications of the ACM,19(7):385–394, 1976
261 KIRCHNER, H., S RANISE, C RINGEISSENund D K TRAN: On
Superposition-Based Satisfiability Procedures and Their Combination In: Proceedings of the national Conference on Theoretical Aspects of Computing (ICTAC), Seiten 594–608,
Inter-2005
262 KLEIN, M.: A Practitioner’s Handbook for Real-Time Analysis Kluwer Academic blishers, Boston, MA, U.S.A., 1993
Pu-263 KLINGERMAN, E und A D STOYENKO: Real-Time Euclid: A Language for Reliable
Real-Time Systems IEEE Transactions on Software Engineering, SE-12(9):941–949,
1986
264 KOELBL, A., Y LU und A MATHUR: Embedded Tutorial: Formal Equivalence
Checking Between System-Level Models and RTL In: Proceedings of the nal Conference on Computer-Aided Design (ICCAD), Seiten 965–971, 2005.
Internatio-265 KONDRATYEV, A., M KISHINEVSKY, A TAUBINund S TEN: A Structural Approach
for the Analysis of Petri Nets by Reduced Unfoldings In: Proceedings of the Conference
on Application and Theory of Petri Nets, Seiten 346–365, 1996.
Trang 13266 KOPETZ, H.: Real-Time Systems – Design Principles for Distributed Embedded
Appli-cations Kluwer Academic Publishers, Boston, MA, U.S.A., 1997.
267 KOREN, I und C M KRISHNA: Fault Tolerant Systems Morgan Kaufmann PublishersInc., San Francisco, CA, U.S.A., 2007
268 KRIPKE, S A.: A Completeness Theorem in Modal Logic The Journal of SymbolicLogic, 24(1):1–14, 1959
269 KRIPKE, S A.: Semantical Considerations on Modal Logic Acta Philosophica Fennica,16:83–94, 1963
270 KROENING, D und E CLARKE: Checking Consistency of C and Verilog Using
Pre-dicate Abstraction and Induction In: Proceedings of the International Conference on Computer-Aided Design (ICCAD), Seiten 66–72, 2004.
271 KROENING, D und N SHARYGINA: Formal Verification of SystemC by Automatic
Hardware/Software Partitioning In: Proceedings of the International Conference on Formal Methods and Models for Co-Design (MEMOCODE), Seiten 101–110, 2005.
272 KROPF, THOMAS: Introduction to Formal Hardware Verification Springer, Berlin, delberg, 1999
Hei-273 KUEHLMANN, A und F KROHM: Equivalence Checking Using Cuts and Heaps In:
Proceedings of the Design Automation Conference (DAC), Seiten 263–268, 1997.
274 KUEHLMANN, A., V PARUTHI, F KROHMund M K GANAI: Robust Boolean
Rea-soning for Equivalence Checking and Functional Property Verification IEEE
Transacti-ons on Computer-Aided Design of Integrated Circuits and Systems, 21(12):1377–1394,2002
275 KUNZ, W., D K PRADHANund S M REDDY: A Novel Framework for Logic
Veri-fication in a Synthesis Environment IEEE Transactions on Computer-Aided Design of
Integrated Circuits and Systems, 15(1):20–32, 1996
276 KUNZ, W und D STOFFEL: Reasoning in Boolean Networks Kluwer Academic blishers, Dordrecht, The Netherlands, 1997
Pu-277 K ¨UNZLI, S., F POLETTI, L BENINIund L THIELE: Combining Simulation and
For-mal Methods for System-Level Performance Analysis In: Proceedings of the Design, Automation and Test in Europe (DATE), Seiten 236–241, 2006.
278 LAHBIB, Y., A PERRIN, L MAILLET-CONTOZ, A CLOUARD, F GHENASSIAund
R TOURKI: Enriching the Boolean and the Modeling Layers of PSL with SystemC and
TLM Flavors In: Proceedings of the Forum on Design Languages (FDL), Seiten 273–
278, 2006
279 LAHIRI, K., A RAGHUNATHANund S DEY: System-Level Performance Analysis for
Designing On-Chip Communication Architectures IEEE Transactions on
Computer-Aided Design of Integrated Circuits and Systems, 20(6):768–783, Juni 2001
280 LAHIRI, S K und S A SESHIA: The UCLID Decision Procedure In: Proceedings
of the International Conference on Computer Aided Verification (CAV), Seiten 475–478,
2004
281 LAI, Y.-T und S SASTRY: Edge-Valued Binary Decision Diagrams for Multi-Level
Hierarchical Verification In: Proceedings of the Design Automation Conference (DAC),
284 LAM, W K.: Hardware Design Verification: Simulation and Formal Method-Based
Ap-proaches Pearson Studium, Deutschland, Upper Saddle River, NJ, U.S.A., 2005.
Trang 14285 LAMPKA, K., S PERATHONERund L THIELE: Analytic Real-Time Analysis and Timed
Automata: A Hybrid Method for Analyzing Embedded Real-Time Systems In: dings of the International Conference on Embedded Software (EMSOFT), Seiten 107–
Procee-116, 2009
286 LAMPORT, L.: ”Sometime” is Sometimes ”Not Never”: On the Temporal Logic of
Pro-grams In: Proceedings of the Symposium on Principles of Programming Languages (POPL), Seiten 174–185, 1980.
287 LAROUSSINIE, F., N MARKEYund P SCHNOEBELEN: On Model Checking
Duratio-nal Kripke Structures In: Proceedings of the InternatioDuratio-nal Conference on Foundations
of Software Science and Computation Structures (FoSSaCS), Seiten 264–279, 2002.
288 LAROUSSINIE, F., P SCHNOEBELEN, und M TURUANI: On the Expressivity and
Com-plexity of Quantitative Branching-Time Temporal Logics In: Proceedings of the Latin American Symposium on Theoretical Informatics (LATIN), Seiten 437–446, 2000.
289 LARRABEE, T.: Test Pattern Generation Using Boolean Satisfiability IEEE ons on Computer-Aided Design of Integrated Circuits and Systems, 11(1):4–15, 1992
Transacti-290 LASKI, J W.: On Data Flow Guided Program Testing ACM SIGPLAN Notices,17(9):62–71, 1982
291 LASKI, J W und B KOREL: A Data Flow Oriented Program Testing Strategy IEEETransactions on Software Engineering, SE-9(3):347–354, 1983
292 LAWLER, E L.: Optimal Sequencing of a Single Machine Subject to Precedence
Cons-traints Management Science, 19:544–546, 1973.
293 LE BOUDEC, J.Y und P THIRAN: Network Calculus: A Theory of Deterministic
Queuing Systems for the Internet Springer, New York, NY, U.S.A., 2001.
294 LEE, C Y.: Representation of Switching Circuits by Binary-Decision Programs BellSystems Technical Journal, 38:985–999, 1959
295 LEE, E A.: Dataflow Process Networks Technischer Bericht UCB/ERL 94/53, Dept
of EECS, UC Berkeley, Berkeley, CA 94720, U.S.A., 1993
296 LEE, E A und D G MESSERSCHMITT: Synchronous Data Flow Proceedings of theIEEE, 75(9):1235–1245, 1987
297 LEE, E A., S NEUENDORFFERund M J WIRTHLIN: Actor-Oriented Design of
Em-bedded Hardware and Software Systems Journal of Circuits, Systems, and Computers,
12(3):231–260, 2003
298 LEE, E A und A L SANGIOVANNI-VINCENTELLI: A Framework for Comparing
Models of Computation IEEE Transactions on Computer-Aided Design of Integrated
Circuits and Systems, 17(12):1217–1229, 1998
299 LEHOCZKY, J.: Fixed Priority Scheduling of Periodic Task Sets with Arbitrary
Dead-lines In: Proceedings of the Real-Time Systems Symposium (RTSS), Seiten 201–209,
1990
300 LEHOCZKY, J P und L SHA: Performance of Real-Time Bus Scheduling Algorithms
In: International Conference on Measurement and Modeling of Computer Systems,
Sei-ten 44–53, 1986
301 LEUNG, J und J WHITEHEAD: On the Complexity of Fixed Priority Scheduling of
Periodic, Real-Time Tasks Performance Evaluation, 2(4):237–250, 1982.
302 LI, Y.-T S und S MALIK: Performance Analysis of Embedded Software Using Implicit
Path Enumeration ACM SIGPLAN Notices, 30(11):88–98, 1995.
303 LI, Y.-T S., S MALIKund A WOLFE: Efficient Microarchitecture Modeling and Path
Analysis for Real-Time Software In: Proceedings of the Real-Time Systems Symposium (RTSS), Seiten 298–307, 1995.
Trang 15304 LICHTENSTEIN, O und A PNUELI: Checking that Finite State Concurrent Programs
Satisfy their Linear Specification In: Proceedings of the Symposium on Principles of Programming Languages (POPL), Seiten 97–107, 1985.
305 LIGGESMEYER, P.: Software-Qualit¨at – Testen, Analysieren und Verifizieren von
Soft-ware Spektrum Akademischer Verlag, Heidelberg, Berlin, 2002.
306 LIGGESMEYER, P und D ROMBACH: Software Egineering eingebetteter Systeme –
Grundlagen - Methodik - Anwendungen Elsevier GmbH, M¨unchen, 2005.
307 LIU, C L und J W LAYLAND: Scheduling Algorithms for Multiprogramming in a
Hard-Real-Time Environment Journal of the ACM, 20(1):46–61, 1973.
308 LIU, J.: Real-Time Systems Prentice-Hall, Inc., Boston, MA, U.S.A., 2000
309 LU, R und C.-K KOH: Performance Analysis of Latency-Insensitive Systems IEEETransactions on Computer-Aided Design of Integrated Circuits and Systems, 25(3):469–
483, 2006
310 MAHFOUDH, M., P NIEBERT, E ASARINund O MALER: A Satisfiability Checker
for Difference Logic In: Proceedings of the Symposium on Theory and Applications of Satisfiability Testing (SAT), Seiten 222–230, 2002.
311 MANO, M M und C R KIME: Logic and Computer Design Fundamentals PearsonStudium, Deutschland, Upper Saddle River, NJ, U.S.A., 2008 4 Auflage
312 MARKEY, N und P SCHNOEBELEN: Symbolic Model Checking of Simply-Timed
Sys-tems In: Proceedings of the International Conference on Formal Modeling and Analysis
of Timed Systmes (FORMATS), Seiten 102–117, 2004.
313 MARQUES-SILVA, J P.: The Impact of Branching Heuristics in Propositional
Satisfiabi-lity Algorithms In: Proceedings of the Portuguese Conference on Artificial Intelligence (EPIA), Seiten 62–74, 1999.
314 MARQUES-SILVA, J P und K A SAKALLAH: GRASP: A Search Algorithm for
Pro-positional Satisfiability IEEE Transactions on Computers, 48(5):506–521, 1999.
315 MATSUMOTO, T., H SAITOund M FUJITA: Equivalence Checking of C Programs
by Locally Performing Symbolic Simulation on Dependence Graphs In: Proceedings of the International Symposium on Quality of Electronic Design (ISQED), Seiten 370–375,
2006
316 MCMILLAN, K L.: Symbolic Model Checking: An Approach to the State Explosion
Problem Kluwer Academic Publishers, Norwell, MA, U.S.A., 1993.
317 MCMILLAN, K L.: Using Unfoldings to Avoid the State Explosion Problem in the
Verification of Asynchronous Circuits In: Proceedings of the International Conference
on Computer Aided Verification (CAV), Seiten 164–177, 1993.
318 MCMILLAN, K L.: Trace Theoretic Verification of Asynchronous Circuits Using
Unfol-dings In: Proceedings of the International Conference on Computer Aided Verification (CAV), Seiten 180–195, 1995.
319 MCMILLAN, K L.: Verification of an Implementation of Tomasulo’s Algorithm by
positional Model Checking In: Proceedings of the International Conference on puter Aided Verification (CAV), Seiten 110–121, 1998.
Com-320 MCMILLAN, K L.: Interpolation and SAT-Based Model Checking In: Proceedings of
the International Conference on Computer Aided Verification (CAV), Seiten 1–13, 2003.
321 MCMILLAN, K L und N AMLA: Automatic Abstraction without Counterexamples
In: Proceedings of the International Conference on Tools and Algorithms for the
Con-struction and Analysis of Systems (TACAS), Seiten 2–17, 2003.
322 MCNAUGHTON, R.: Testing and Generating Infinite Sequences by a Finite Automaton.Information and Control, 9(5):521–530, 1966
323 MCNAUGHTON, R und H YAMADA: Regular Expressions and State Graphs for
Auto-mata IRE Transactions on Electronic Computers, EC-9(1):39–47, 1960.