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56 Interconnection Networksthis research is building multistage networks, with each stage including switching matrices eachbeing a non-blocking crossbar network.. Nevertheless, a specifi

Chapter 2 Interconnection Networks

This chapter is the first of three chapters devoted to the study of network theory The basicconcepts of the interconnection networks are briefly outlined here The aim is to introduce theterminology and define the properties that characterize an interconnection network Thesenetworks will be described independently from the context in which they could be used, that

is either a circuit switch or a packet switch The classes of rearrangeable networks investigated

in Chapter 3 and that of non-blocking networks studied in Chapter 4 will complete the work theory

net-The basic classification of interconnection network with respect to the blocking property isgiven in Section 2.1 where the basic crossbar network and EGS pattern are introduced beforedefining classes of equivalences between networks Networks with full interstage connectionpatterns are briefly described in Section 2.2, whereas partially connected networks are investi-gated in Section 2.3 In this last section a detailed description is given for two classes ofnetworks, namely banyan networks and sorting networks, that will play a very important role

in the building of multistage networks having specific properties in terms of blocking.Section 2.4 reports the proofs of some properties of sorting networks exploited in Section 2.3

2.1 Basic Network Concepts

The study of networks has been pursued in the last decades by researchers operating in twodifferent fields: communication scientists and computer scientists The former have beenstudying structures initially referred to as connecting networks for use in switching systems andthus characterized in general by a very large size, say with thousands of inlets and outlets Thelatter have been considering structures called interconnection networks for use in multiprocessorsystems for the mutual connection of memory and processing units and so characterized by areasonably small number of inlets and outlets, say at most a few tens In principle we could say

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54 Interconnection Networks

that connecting networks are characterized by a centralized control that sets up the tion required, whereas the interconnection networks have been conceived as based on adistributed processing capability enabling the set-up of the permutation in a distributed fash-ion Interestingly enough the expertise of these two streams of studies have converged into aunique objective: the development of large interconnection networks for switching systems inwhich a distributed processing capability is available to set up the required permutations Thetwo main driving forces for this scenario have been the request for switching fabrics capable ofcarrying aggregate traffic on the order of hundreds of Gbit/s, as typical of a medium-sizebroadband packet switch, and the tremendous progress achieved in CMOS VLSI technologythat makes the distributed processing of interconnection networks feasible also for very largenetworks

permuta-The connection capability of a network is usually expressed by two indices referring to theabsence or presence of traffic carried by the network: accessibility and blocking A network has

full accessibility when each inlet can be connected to each outlet when no other I/O tion is established in the network, whereas it has limited accessibility when such property doesnot hold Full accessibility is a feature usually required today in all interconnection networkssince electronic technology, unlike the old mechanical and electromechanical technology,makes it very easy to be accomplished On the other hand, the blocking property refers to thenetwork connection capability between idle inlets and outlets in a network with an arbitrarycurrent permutation, that is when the other inlets and outlets are either busy or idle and arbi-trarily connected to each other

connec-An interconnection network, whose taxonomy is shown in Table 2.1, is said to be:

• Non-blocking, if an I/O connection between an arbitrary idle inlet and an arbitrary idle let can be always established by the network independent of the network state at set-uptime

out-• Blocking, if at least one I/O connection between an arbitrary idle inlet and an arbitrary idleoutlet cannot be established by the network owing to internal congestion due to thealready established I/O connections

Depending on the technique used by the network to set up connections, non-blocking works can be of three different types:

net-• Strict-sense non-blocking (SNB), if the network can always connect each idle inlet to an trary idle outlet independent of the current network permutation, that is independent ofthe already established set of I/O connections and of the policy of connection allocation

arbi-• Wide-sense non-blocking (WNB), if the network can always connect each idle inlet to anarbitrary idle outlet by preventing blocking network states through a proper policy of allo-cating the connections

• Rearrangeable non-blocking (RNB), if the network can always connect each idle inlet to anarbitrary idle outlet by applying, if necessary, a suitable internal rearrangement of the I/Oconnections already established

Therefore, only SNB networks are free from blocking states, whereas WNB and RNB works are not (see Table 2.1) Blocking states are never entered in WNB networks due to asuitable policy at connection set-up time Blocking states can be encountered in RNB net-

net-Basic Network Concepts 55

works during the dynamic network evolution but new connections can always be established

by possibly rearranging the connections already set up

It is intuitively clear that a SNB network satisfies at the same time the definition of WNBand RNB networks, but not vice versa We will not develop here the subject of WNB net-works and will only focus on SNB networks, simply denoted in the following as non-blocking networks, and on RNB networks, referred to as rearrangeable networks Note that an RNB net-work is also SNB if all the connections are set up and torn down at the same time

We can intuitively assume that the above three non-blocking network types are ized by a decreasing cost index, starting from strict-sense non-blocking and ending withrearrangeable non-blocking Traditionally the cost index of the network has always assumed to

character-be the numcharacter-ber of crosspoints in the network, as reasonable in the space-division switching tems of the sixties and seventies Nowadays such a performance index alone does notcharacterize the cost of an interconnection network for broadband applications, owing to theextreme degree of integration of the electronic components in a single chip enabled by VLSItechnologies Consider for example the other cost indices: the gates per chip, the chips perboard, the crosspoints per board, etc Nevertheless, since it is very hard to find a unique, evencomposite, cost index for a network, we will continue to refer to the number of crosspoints inthe network as the cost index for the network, by always bearing in mind its limitedsignificance

sys-The reference network is necessarily the well-known crossbar network (Figure 2.1)with N inlets, M outlets.The cost index of such a network, that is the number of its cross-points, referred to a squared structure , is

Since each crosspoint is dedicated to a specific I/O connection, the crossbar network isimplicitly non-blocking A squared crossbar network is able to set up an arbitrary

network permutation, that is an arbitrary set of N I/O connections; if P denotes the set of all thepermutations set up by a generic network, in general , whereas in a crossbarnetwork

Research activities have been undertaken for decades to identify network structures fallinginto one of the non-blocking classes, but cheaper than the crossbar network The guideline for

Table 2.1 Network taxonomy

Network class Network type Network states

Non-blocking

Strict-sense non-blocking

Without blocking states Wide-sense

non-blocking With

blocking states

Rearrangeable non-blocking Blocking Others

56 Interconnection Networks

this research is building multistage networks, with each stage including switching matrices eachbeing a (non-blocking) crossbar network The general model of an multistage networkincludes s stages with matrices at stage i , so that ,

The matrix of the generic stage i, which is the basic building block of amultistage network, is assumed to be non-blocking (i.e a crossbar network)

The key feature that enables us to classify multistage networks is the type of tion pattern between (adjacent) stages The apparent condition

always applies, that is the number of outlets of stage i equals the number ofinlets of stage As we will see later, a different type of interconnection pattern will beconsidered that cannot be classified according to a single taxonomy Nevertheless, a specificclass of connection pattern can be defined, the extended generalized shuffle (EGS) [Ric93],which includes as subcases a significant number of the patterns we will use in the following.Let the couple represent the generic inlet (outlet) j of the matrix k of the generic stage

that the outlet of matrix , that is outlet , is connected to inlet with

In other words, we connect the outlets of stage i starting from outlet (0,1) sequentially tothe inlets of stage as

An example is represented in Figure 2.2 for A network built out of stages nected by means of EGS patterns is said to be an EGS network

intercon-Figure 2.1 Crossbar network

0 1

N-2 N-1

Basic Network Concepts 57

Multistage networks including s stages will now be described according to the following

type of interstage pattern configuration:

• full connection (FC), if each matrix in stage is connected to all thematrices in stages and ;

• partial connection (PC), if each matrix in stage is not connected to allthe matrices in stages and

It is worth noting that an EGS network with is a FC network,

2.1.1 Equivalence between networks

We refer now to a squared network and number the network inlets and outlets 0through sequentially from the top to the bottom If the network includes more than

one stage and the generic matrix includes b outlets, each outlet matrix being labelled from 0 to

, an underlying graph can be identified for the network: each matrix is mapped onto agraph node and each interstage link onto a graph edge Graph nodes and edges are notlabelled, so that network inlets and outlets need not be mapped onto edges, since they carry

no information Therefore the most external graph elements are the nodes representing thematrices of the first and last network stage

Figure 2.2 EGS interconnection pattern

1

ni-10

mi+1-10

mi+1-10

Two graphs A and B are said to be isomorphic if, after relabelling the nodes of graph Awith the node labels of graph B, graph A can be made identical to graph B by moving its nodesand hence the attached edges The mapping so established between nodes in the same position

in the two original graphs expresses the “graph isomorphism” A network is a more complexstructure than a graph, since an I/O path is in general described not only by a sequence ofnodes (matrices) but also by means of a series of labels each identifying the outlet of a matrix(it will be clear in the following the importance of such a more complete path description forthe routing of messages within the network) Therefore an isomorphism between networkscan also be defined that now takes into account the output matrix labelling

Two networks A ad B are said to be isomorphic if, after relabelling the inlets, outlets andthe matrices of network A with the respective labels of network B, network A can be madeidentical to network B by moving its matrices, and correspondingly its attached links It isworth noting that relabelling the inlets and outlets of network A means adding a proper inletand outlet permutation to network A Note that the network isomorphism requires the modi-fied network A topology to have the same matrix output labels as network B for matrices inthe same position and is therefore a label-preserving isomorphism The mapping so establishedbetween inlets, outlets and matrices in these two networks expresses the “network isomor-phism” In practice, since the external permutations to be added are arbitrary, networkisomorphism can be proven by just moving the matrices, together with the attached links, sothat the topologies of the two networks between the first and last stage are made identical

By relying on the network properties defined in [Kru86], three kinds of relations betweennetworks can now be stated:

• Isomorphism: two networks are isomorphic if a label-preserving isomorphism holds between

them

• Topological equivalence: two networks are topologically equivalent if an isomorphism holds

between the underlying graphs of the two networks

• Functional equivalence: two networks A and B are functionally equivalent if they perform the

same permutations, that is if

Two isomorphic networks are also topologically equivalent, whereas the converse is not alwaystrue In general two isomorphic or topologically equivalent networks are not functionallyequivalent Nevertheless, if the two networks (isomorphic or not, topologically equivalent ornot) are also non-blocking, they must also be functionally equivalent since both of them per-form the same permutations (all the permutations) Note that the same number ofnetwork components are required in two isomorphic networks, not in two functionally equiv-alent networks

For example, consider the two networks A and B of Figure 2.3: they are topologicallyequivalent since their underlying graph is the same (it is shown in the same Figure 2.3) Nev-ertheless, they are not isomorphic since the above-defined mapping showing a label-preserving isomorphism between A and B cannot be found In fact, if matrices in network Aare moved, the two networks A' and A" of Figure 2.3 can be obtained, which are close to Bbut not the same A' has nodes with the same label but the links outgoing from H exchangedcompared to the analogous outgoing from Y, whereas A" has the same topology as B but with

P A = P B

N!

Basic Network Concepts 59

the labels in H exchanged compared to Y On the other hand both networks A' and A" are morphic to network B in Figure 2.4 and the required mappings are also given in the figure

iso-Note that the two networks A and B of both examples above are not functionally lent, since, e.g., the two connections (0,0) and (1,1) can belong to the same permutation innetwork A, whereas this is not true for network B (remember that inlets and outlets are num-bered 0 through 3 top to bottom of the network) The example of Figure 2.5 shows twoisomorphic and functionally equivalent networks (it will be shown in Section 3.2.1.1 that bothnetworks are rearrangeable)

equiva-A useful tool for the analysis of multistage networks is the channel graph equiva-A channel graph is

associated with each inlet/outlet pair and is given by the sequence of network elements thatare crossed to reach the selected outlet from the selected input In the channel graph, matrices

Figure 2.3 Example of topologically equivalent non-isomorphic networks

Figure 2.4 Example of isomorphic networks

Graph of A and B

H

a b c

d I

J

e f g h

0 1 0 1

0 1

A

s t u v

w x y z

X

Y

0 1 0 1

Z01B

c d a b

f g h e

I

H

0 1 0 1

J01A'

c d a b

f g h e

I

H

0 1 1 0

J01A"

H

a b c

d I

J

e f g h

0 1 0 1

0 1

A'

s t u v

w x y z

X

Y

0 1 0 1

Z01B

d I

J

e f g h

1 0 0 1

0 1

A''

are represented as nodes and interstage links as edges Therefore the number of I/O paths inthe channel graph represents the number of different modes in which the network outlet can

be reached from the network inlet Two I/O paths in the channel graph represent two I/Onetwork connections differing in at least one of the crossed matrices A network in which a

single channel graph is associated with all the inlet/outlet pairs is a regular network In a regular

channel graph all the nodes belonging to the same stage have the same number of incoming

edges and the same number of outgoing edges Two isomorphic networks have the same nel graph

chan-The channel graphs associated with the two isomorphic networks of Figure 2.4 are shown

in Figure 2.6 In particular, the graph of Figure 2.6a is associated with the inlet/outlet pairsterminating on outlets e or f in network A (y or z in network B), whereas the graph ofFigure 2.6b represents the I/O path leading to the outlets g or h in network A (w or x in net-work B) In fact three matrices are crossed in the former case engaging either of the twomiddle-stage matrices, while a single path connects the inlet to the outlet, crossing only twomatrices in the latter case

2.1.2 Crossbar network based on splitters and combiners

In general it is worth examining how a crossbar network can be built by means of smaller

building blocks relying on the use of special asymmetric connection elements called splitters and combiners, whose size is respectively and with a cost index

Note that a splitter, as well as a combiner, is able to set up one connection

at a time The crossbar tree network (Figure 2.7) is an interconnection network functionally

Figure 2.5 Example of isomorphic and functionally equivalent networks

Figure 2.6 Channel graphs of the networks in Figure 2.4

a b c d

e f g h

H

I

0 1 0 1

J

K

0 1 0 1

L01A

a' b' c' d'

w x y z

H'

I'

0 1 0 1

J'

K'

1 0 1

Basic Network Concepts 61

equivalent to the crossbar network: it includes N splitters and N combiners

interconnected by means of an EGS pattern and its cost is

The crossbar tree can be built also by using multistage splitting and combining structuresbased on the use of elementary splitters and combiners, as shown in Figure 2.8for The cost index of such structure, referred to as a crossbar binary tree network, is

It is interesting to note how the basic crossbar tree network of Figure 2.7 can be built usingsmaller splitters and combiners by means of a central switching stage Our aim is a central stagewith the smallest cost that still guarantees full input/output accessibility, thus suggesting a set ofcrossbar matrices each with the smallest possible size In general if we have an expansion stagewith size with , each inlet has access to K switching matrices from which all the N outlets must be reached, so that each switching matrix must

have a number of outlets (and inlets) at least equal to (each matrix in the switching stage

is connected to splitters and combiners with at most one link) By adopting for the two stage connections the EGS pattern, which provides a cyclic connection to the elements of thefollowing stage, it follows that such matrix size is sufficient to give full accessibility, as is shown

inter-in Figure 2.9 for and Since the number of these matrices is

Figure 2.7 Crossbar tree

C = 2N2

1 0

N-1

1 0

- = K2

the cost function of such a network is given by

Figure 2.8 Crossbar binary tree

Figure 2.9 Crossbar tree with one switching stage

1 0

7

1 0

7

0 1 2 3 4 5 6 7

0 1 2 3 4 5 6 7

Full-connection Multistage Networks 63

2.2 Full-connection Multistage Networks

The description of FC networks assumes as a general rule, unless stated otherwise, that ces in adjacent stages are always connected by a single link Thus the general model of an full-connection (FC) multistage network is given by Figure 2.10, in which ,

and the matrix of the generic stage i is a crossbar network.

Note that such network is a subcase of an EGS network with

We examine here the two cases of two- and three-stage networks as they providethe basic concepts for understanding the properties of full-connection multistage networks In

the following n and m will denote the inlets to each first-stage matrix and the outlets from

each last-stage matrix

The model of a two-stage FC network is represented in Figure 2.11 This network clearlyhas full accessibility, but is blocking at the same time In fact, no more than one connectionbetween two matrices of different stages can be established Only the equipment of multiplelinks between each couple of matrices in different stages can provide absence of blocking The scheme of a three-stage FC network is given in Figure 2.12 Adopting three stages in amultistage network, compared to a two-stage arrangement, introduces a new important con-cept: different I/O paths are available between any couple of matrices in the first and thirdstage, each engaging a different matrix in the second stage Full accessibility is implicitly guar-

anteed by the full connection feature of the two interstage patterns Given N and M, the

three-stage network has to be engineered so as to minimize its cost In particular the number of ond-stage matrices is the parameter determining the network non-blocking condition The control of multistage FC networks requires in general a centralized storage devicewhich keeps the information about the busy/idle state of all the network terminations andinterstage links So a new connection between an idle inlet and an idle outlet of a non-block-

sec-Figure 2.10 FC network with s stages

ing network can easily be found by properly visiting the network connection map, whereasmore complex algorithms are in general required in rearrangeable networks to select the con-nections to be moved and their new path.

2.3 Partial-connection Multistage Networks

The class of partial-connection (PC) networks, in which each matrix of the intermediatestages is connected only to a subset of the matrices in the two adjacent stages, is becomingmore and more important in today’s high-speed communication networks based on packetswitching The interconnection networks of these scenarios are expected to carry very largeamounts of traffic and the network permutation must be changed at a very high rate, e.g thestate duration is on the order of a few microseconds Thus a mandatory requirement to build

Figure 2.11 FC two-stage network

Figure 2.12 FC three-stage network

Partial-connection Multistage Networks 65

such interconnection networks with a significant size seems to be the availability of a highdegree of parallel processing in the network This result is accomplished by designing multi-stage PC networks in which the matrices of all stages are in general very small, usually all ofthe same size, and are provided with an autonomous processing capability These matrices,

referred to as switching elements (SEs), have in general sizes that are powers of two, that is with k typically in the range [1,5] In the following, unless stated otherwise, we

assume the SEs to have size

By relying on its processing capability, each SE becomes capable of routing autonomously

the received packets to their respective destinations Such feature is known as packet self-routing property The networks accomplishing this task are blocking structures referred to as banyan

networks These networks, which provide a single path per each inlet/outlet pair, can be

suit-ably “upgraded” so as to obtain RNB and SNB networks Sorting networks play a key role as

well in high-speed packet switching, since the RNB network class includes also those tures obtained by cascading a sorting network and a banyan network All these topics areinvestigated next

struc-2.3.1 Banyan networks

We first define four basic permutations, that is one-to-one mappings between inlets and lets of a generic network , that will be used as the basic building blocks of self-routingnetworks Let represent a generic address with base-2 digits ,where is the most significant bit

out-Four basic network permutations are now defined that will be needed in the definition of

the basic banyan networks; the network outlet connected to the generic inlet a is specified by

one of the following functions:

(right) shift by one position of the least significant bits of the inlet address In the case of

the circular shift is on the full inlet address and the two permutations are referred to

as perfect shuffle and perfect unshuffle Moreover, is called the butterfly tion and j the identity permutation Note that It can be verified that apermutation corresponds to perfect shuffle permutationseach applied to adjacent network inlets/outlets (only the least significant bits arerotated in ) It is interesting to express the perfect shuffle and unshuffle permutations byusing addresses in base 10 They are

In the perfect shuffle the input address i is doubled modulo N, which corresponds to a left shift

of the least significant bits, whereas the last term of accounts for the value of (inlets larger than are mapped onto odd outlets so that a unity is added to the first

term) Analogously, in the perfect unshuffle the input address i is halved and the integer part is

taken, which corresponds to a right shift of the most significant bits, whereas the lastterm of accounts for the value of (even and odd addresses are mapped onto the firstand last outlets respectively)

Two other permutations are also defined which will be useful in stating relations betweenbanyan networks

•

•

The permutation δ, called bit switch, and ρ, called bit reversal, are shown in Figure 2.13 for

2.3.1.1 Banyan network topologies

Banyan networks are multistage arrangements of very simple switching elements whoseinlets and outlets are labelled 0 through The interstage connection patterns are such thatonly one path exists between any network inlet and network outlet, and different I/O pathscan share one or more interstage links SEs in a banyan network are organized in

stages each comprising SEs As is usually the case with banyan networks, we assume N, as well as b, to be a power of 2.

A general construction rule is now given to build a banyan network that, as explained later,provides the nice feature of a very simple distributed routing of packets through the network

Figure 2.13 Examples of network permutations

Partial-connection Multistage Networks 67

to their own destination The rule consists in connecting each network outlet to all the inlets

in such a way that at each step of this backward tree construction the inlets of the SEs of the

stage i are connected to outlets of the same index in the SEs of stage In the case of this corresponds to connecting the inlets of the SEs in a stage to all top or bottom out-lets of upstream SEs An example for a network with is given in Figure 2.14 Thebuilding of the whole network is split into four steps, each devoted to the connection of acouple of network outlets, terminated onto the same SE of the last stage, to the eight networkinlets The process is started from a network without interstage links The new interstage linksadded at each step to provide connection of a network outlet to all the network inlets aredrawn in bold Given the construction process being used, it follows that a single path descrip-

tor including n outlet indices (one per stage) identifies all the I/O paths leading to the same network outlet The class of banyan networks built using this rule is such that all the N paths

leading to a given network outlet are characterized by the same path descriptor, given by thesequence of outlet indices selected in the path stage by stage The banyan networks in whichsuch a path descriptor is a permutation of the path network outlet are also called “delta” net-works [Pat81] Only this kind of banyan network will be considered in the following

For simplicity we consider now SEs, but the following description of banyan works can be easily extended to SEs A SE, with top and bottom inlets

net-(and outlets) labelled 0 and 1, respectively, can assume only two states, straight giving the I/O paths 0-0 and 1-1 in the SE, and cross giving the I/O paths 0-1 and 1-0 (Figure 2.15)

Figure 2.14 Construction of a banyan network

i–1

b = 2

N = 8

000 001 010 011 100 101 110 111

(a)

000 001 010 011 100 101 110 111

(b)

000 001 010 011 100 101 110 111

(c)

000 001 010 011 100 101 110 111

(d)

2×2

b×b (b>2) 2×2

Several topologies of banyan networks have been described in the technical literature thatdiffer in the way of interconnecting SEs in adjacent stages and network inlets (outlets) to theSEs of the first (last) stage Figure 2.16 shows the structure of four of these networks for

: Omega [Law75], SW-banyan [Gok73], n-cube [Sie81], Baseline [Wu80a] The reverse

topology of each of these networks is easily obtained as the mirror image of the network itself:

the topology of a reverse Baseline network (or Baseline -1) is shown at the end of this section

when the routing property of a banyan network is described The reverse n-cube is also known as

indirect binary n-cube [Pea77] Figure 2.16 also shows how the SW-banyan and Baseline network

can be built by applying times a recursive construction In fact an Baselinenetwork includes a first stage of SEs interconnected through a perfectunshuffle permutation to two Baseline networks of half size An analogousrecursive construction is applied in the SW-banyan network : two SW-banyan networks are connected through a butterfly permutation to a last stage of SEs

In our representation stages are numbered 1 through n with stage 1 (n) interfacing the work inlets (outlets) The permutation set up by the N links following the switching stage h is

net-denoted by , whereas indicates the input permutation of the network (that is themapping between network inlets and the inlets of the first stage)

Thus the four networks of Figure 2.16 and their reverse structures are formally described

by the first three columns of Table 2.2 It is worth noting that the interstage pattern of theOmega network is a subcase of an EGS pattern with Functional equivalences between the different banyan topologies have been found[Wu80b], in the sense that one topology can be obtained from another by applying on theinlets and/or on the outlets one of the two permutations δ and ρ Table 2.3 shows functionalequivalence between networks starting from each the four basic topologies of Figure 2.16, theOmega (Ω), the SW-banyan (Σ), the n-cube (Γ) and the Baseline (Φ) A sequence of permu-tations αβγ means a sequence of networks applying on an input sequence the permutation α,followed by β and ending with γ For example, a Baseline network preceded by a bit reversalpermutation of the inlets is functionally equivalent to the Omega network Note that theoperation of network reversing does not affect the Baseline network as this network and its

reverse perform the same permutations Furthermore, since Figure 2.16 shows that a reverse

n-cube is obtained by an SW-banyan followed by a perfect unshuffle permutation, it follows fromthe correspondence in the Table 2.3 that , that is a bit switch permutation followed

by a bit reversal is equivalent to a perfect unshuffle (it can be immediately verified by simplyapplying the permutation definitions)

Figure 2.15 SE states

straight cross

0 1

0 1

0 1

0 1

Partial-connection Multistage Networks 69

(c) - 4-cube

According to Table 2.3, Figure 2.16 includes in reality only three basic networks that are

not functionally equivalent, since the Omega and n-cube networks are functionally equivalent.

In fact it can be easily verified that one topology can be obtained from the other by suitableposition exchange of SEs in the intermediate stages

2.3.1.2 Banyan network properties

All the four topologies of banyan networks defined here are based on interstage patterns

satis-fying two properties, called the buddy property [Dia81] and the constrained reachability property.

Table 2.2 Topology and routing rule in banyan networks

Self-routing bit

Self-routing bit

SW-banyan-1

n-cube n-cube-1

σn– 1 1 – d n–h d h–1

Partial-connection Multistage Networks 71

Buddy property. If SE at stage i is connected to SEs and , then these two SEsare connected also to the same SE in stage i.

In other words, switching elements in adjacent stages are always interconnected in couples toeach other By applying the buddy property across several contiguous stages, it turns out that

certain subsets of SEs at stage i reach specific subsets of SEs at stage of the same size, asstated by the following property

Constrained reachability property The SEs reached at stage by an SE at stage i

are also reached by exactly other SEs at stage i.

The explanation of this property relies on the application of the buddy property stage by stage

to find out the set of reciprocally connected SEs An SE is selected in stage i as the root of a

forward tree crossing 2 SEs in stage , 4 SEs in stage , …, SEs in stage

so that SEs are reached in stage By selecting any of these SEs as the root of

a tree reaching backwards stage i, it is easily seen that exactly SEs in stage i are reached

including the root of the previous forward tree If all the forward and backward subtrees aretraced starting from the SEs already reached in stages , exactly SEs perstage will have been crossed in total Apparently, the buddy property will be verified as holdingbetween couples of SEs in adjacent stages between i and An example of these twoproperties can be found in Figure 2.17, where two couples of buddy SEs in stages 1 and 2 areshown together with the constrained reachability between sets of 4 SEs in stages 1 through 3

Since the constrained reachability property holds in all the banyan topologies definedabove, the four basic banyan networks are isomorphic to each other In fact, a banyan network

B can be obtained from another banyan network A by properly moving the SEs of A so that

Figure 2.17 Buddy and constrained reachability property