Solid State Circuits Technologies Part 1 pot

1 CMOS Voltage and Current Reference Circuits consisting of Subthreshold MOSFETs — Micropower Circuit Components for Power-aware LSI Applications —... Subthreshold region or weak inver

Solid State Circuits Technologies

Solid State Circuits Technologies

Edited by Jacobus W Swart

Intech

IV

Published by Intech

Intech

Olajnica 19/2, 32000 Vukovar, Croatia

Abstracting and non-profit use of the material is permitted with credit to the source Statements and opinions expressed in the chapters are these of the individual contributors and not necessarily those of the editors or publisher No responsibility is accepted for the accuracy of information contained in the published articles Publisher assumes no responsibility liability for any damage or injury to persons or property arising out of the use of any materials, instructions, methods or ideas contained inside After this work has been published by the Intech, authors have the right to republish it, in whole or part, in any publication of which they are an author or editor, and the make other personal use of the work

© 2010 Intech

Free online edition of this book you can find under www.sciyo.com

Additional copies can be obtained from:

publication@sciyo.com

First published January 2010

Printed in India

Technical Editor: Teodora Smiljanic

Solid State Circuits Technologies, Edited by Jacobus W Swart

p cm

ISBN 978-953-307-045-2

Preface

The evolution of solid-state circuit technology has a long history within a relatively short period of time This technology has leaded to: the modern information society that connects us and tools; a large market; and, many types of products and applications The solid-state circuit technology continuously evolves via breakthroughs and improvements every year This book is devoted to review and present novel approaches for some of the main issues involved in this exciting and vigorous technology

The book is composed of 22 chapters, written by authors coming from 30 different institutions located in12 different countries throughout the Americas, Asia and Europe Thus, reflecting the wide international contribution to the book

Low power consumption is becoming a paramount issue for modern integrated circuits, motivated by the huge integration level of modern electronics In addition, the need for power-aware applications such as mobile electronics, RFIDs, implantable medical devices and smart sensor network motivates the development of low power consumption hardware Circuit design techniques that aim for reduced power consumption are treated in the first two chapters Accurate device modeling is essential for IC design and the models are constantly adapted to take into account smaller dimension effects This subject is treated in chapter 3, focusing on the saturation mechanisms Thermal noise and process variations affect the performance, yield and minimum bias voltage or power consumption of the circuits These issues are the subjects of chapters 6 to 8

The new and future CMOS technologies with constantly decreasing dimensions require new solutions to: reduce gate leakage; increase gate capacitance per area; reduce the sub-threshold slope; and increase transconductance, among other issues These solutions have lead to new transistor structures, high-k dielectrics and metal gates Critical technological innovations covering these solutions are presented in chapters 7 to 9

Interconnects represents another critical issue in IC technology A large part of the total die area is represented by interconnects having a large effect on the performance and reliability of the circuits Carbon nanotubes are considered a promising material for interconnects The modeling of interconnects as transmission lines and, in addition, the use

of inductive-coupling links between chips are considered Chapters 11 to 15 cover such important issues

Microelectromechanical systems (MEMS) is a complementary field to integrated circuits MEMS use similar materials and the same technology platforms Furthermore, MEMS can be integrated in the same die of the electronic circuit for the case of smart sensors

VI

and actuators or MEMS can be integrated in the same package, as in a system in package approach MEMS are essential for many existing applications Moreover they are going through progressive evolution leading to new devices and new applications for all kind of automatization and sensor networks Progress in materials, techniques, devices, interface circuits and packaging for MEMS are presented in the final 7 chapters of the book

The broad range of subject presented in the book offers a general overview of the main issues in modern solid-state circuit technology Furthermore, the book offers an in dept analysis on specific subjects for specialists We believe the book is of great scientific and educational value for many readers

I am profoundly indebted to the support provided by all of those involved in the work First and foremost I would like to acknowledge and thank the authors that worked hard and generously agreed to share their results and knowledge Second I would like to express my gratitude to the Intech team, that invited me to edit the book and give me their full support and a fruitful experience while working together to combine this book

Editor

Jacobus W Swart

Center of Technology for Information Renato Archer– CTI, Campinas, SP,

Brazil

2 Low-Power Analog Associative Processors Employing

Trong Tu Bui and Tadashi Shibata

3 The Evolution of Theory on Drain Current Saturation Mechanism

Peizhen Yang, W.S Lau, Seow Wei Lai, V.L Lo, S.Y Siah and L Chan

Chih-Hung Chen

5 Statistical Prediction of Circuit Aging under Process Variations 101

Wenping Wang, Vijay Reddy, Varsha Balakrishnan, Srikanth Krishnan and Yu Cao

6 Standby Supply Voltage Minimization for Reliable Nanoscale SRAMs 123

Jiajing Wang and Benton H Calhoun

7 Ultralow-power LSI Technology with Silicon on Thin Buried Oxide

Takashi Ishigaki, Ryuta Tsuchiya, Yusuke Morita,

Nobuyuki Sugii and Shin’ichiro Kimura

8 The Progress and Challenges of Applying High-k/Metal-Gated Devices

Hsing-Huang Tseng, Ph.D

VIII

9 Metal Gate Electrode and High-κ Dielectrics for Sub-32nm Bulk

CMOS Technology: Integrating Lanthanum Oxide Capping Layer

for Low Threshold-Voltage Devices Application

189

HongYu Yu

10 Computational Study of the Effects of Channel Materials

& Channel Orientations and Dimensional Effects

on the Performance of Nanowire FETs

203

Chee Shin Koong and Gengchiau Liang

11 Integration of Carbon Nanotubes in Microelectronics 215

Stanislav A Moshkalev, Carla Veríssimo,

Rogério V Gelamo, Leonardo R C Fonseca,

Ettore Baldini-Neto and Jacobus W Swart

12 Carbon Nanotube Interconnect Technologies for Future LSIs 227

Mizuhisa Nihei, Akio Kawabata, Motonobu Sato,

Tatsuhiro Nozue, Takashi Hyakushima, Daiyu Kondo,

Mari Ohfuti, Shintaro Sato and Yuji Awano

Xiaomeng Shi and Kiat Seng Yeo

14 Highly Energy-Efficient On-Chip Pulsed-Current-Mode

Tomoaki Maekawa, Shuhei Amakawa, Hiroyuki Ito,

Noboru Ishihara, and Kazuya Masu

15 An Inductive-Coupling Inter-Chip Link for High-Performance

Kiichi Niitsu and Tadahiro Kuroda

16 Polycrystalline Silicon Piezoresistive

Xiaowei Liu, Changzhi Shi and Rongyan Chuai

17 Sputtered AlN Thin Films for Piezoelectric MEMS Devices

Friedel Gerfers, Peter M Kohlstadt, Eyal Ginsburg,

Ming Yuan He, Dean Samara-Rubio,

Yiannos Manoli and Li-PengWang

18 Micromachined Arrayed Capacitive Ultrasonic Sensor/Transmitter

Seiji Aoyagi

IX

19 Application of Microsystems Technology in the Fabrication

L.M Goncalves and J.G Rocha

20 Ppt-level Detection of Aqueous Benzene with a Portable Sensor

Serge Camou, Akira Shimizu, Tsutomu Horiuchi and Tsuneyuki Haga

21 CMOS Readout Circuit Developments for Ion Sensitive Field Effect

Wen-Yaw Chung, Febus Reidj G Cruz, Chung-Huang Yang,

Fu-Shun He, Tai-Tsun Liu, Dorota G Pijanowska, Wladyslaw Torbicz,

Piotr B Grabiec and Bohdan Jarosewicz

22 Low-temperature Polymer Bonding Using Surface

Hidetoshi Shinohara, Jun Mizuno and Shuichi Shoji

1

CMOS Voltage and Current Reference Circuits

consisting of Subthreshold MOSFETs

— Micropower Circuit Components for Power-aware LSI Applications —

Solid State Circuits Technologies

2

The following sections provide overviews of previous reported low-power reference circuits

and a detailed explanation of our circuits Section 2 describes the subthreshold current of

MOSFETs and shows the temperature and process sensitivity of the current with a SPICE

simulation Section 3 describes the principle of conventional voltage and current reference

circuits based on bandgap reference circuits Sections 4 and 5 explain the operation principle

of the reported voltage and current reference circuits and show the characteristics of

prototype devices we made using 0.35-μm standard CMOS process technology Finally,

concluding remarks are presented in Sect 6

2 Subthreshold region (or weak inversion region) of MOSFETs

When the gate-source voltage of a MOSFET is lower than the threshold voltage,

subthreshold current can be obtained The subthreshold current through a MOSFET is an

increasing exponential function of the gate-source voltage, and the current value is on the

order of nanoamperes Moreover, the subthreshold current is sensitive to temperature and

process variations The temperature and process characteristics of the subthreshold current

are analyzed as follows

Figure 1 shows the measured transfer curves of an nMOSFET in 0.35-μm CMOS process at

different temperatures from –20 to 100°C The drain-source voltage was set to 1 V The

threshold voltage is about 0.5 V in this device The subthreshold drain current IDS of a

MOSFET is an exponential function of the gate-source voltage VGS and the drain-source

voltage VDS and is given by

CMOS Voltage and Current Reference Circuits consisting of Subthreshold MOSFETs 3

where K is the aspect ratio (=W/L) of the transistor, μ is the carrier mobility, COX is the

gate-oxide capacitance, VT(=kB T/q) is the thermal voltage, k B is the Boltzmann constant, T is the

absolute temperature, and q is the elementary charge, VTH is the threshold voltage of a

MOSFET, and η is the subthreshold slope factor [3], [19] For VDS > 0.1 V, current IDS is

independent of VDS and is given by

where μ(T0) is the carrier mobility at room temperature T0, m is the mobility temperature

exponent, VTH0 is the threshold voltage at 0 K, and κ is the temperature coefficient of VTH

Process variations can be classified into two categories: i.e., within-die (WID) (intra-die)

variation and die-to-die (D2D) (inter-die) variation [21]-[23] The WID variation is caused by

mismatches between transistor parameters within a chip and affects the relative accuracy of

the parameters In contrast, the D2D variation affects the absolute accuracy of transistor

parameters between chips

The process dependence of the subthreshold current can be expressed by

The mobility variation Δμ is generally smaller than the threshold voltage variation ΔVTH, so

the current depends mainly on ΔVTH

Figure 2 shows the simulated subthreshold current with fixed gate-source voltages, obtained

with a SPICE simulation with a set of 0.35-μm standard CMOS process Current operating in

the strong inversion region is also plotted for comparison Fixed gate-source voltages were

set to VTH–0.2 V (weak inversion), and VTH+0.2 V (strong inversion), respectively Although

Solid State Circuits Technologies

4

I DS : Weak inversion (VBias =V TH 0.2)

I DS : Strong inversion (VBias =V TH+0.2)

3%/ C T.C.

0.1 0.01

Fig 2 (A) Simulated drain currents as a function of temperature Fixed gate biases were set

to VTH–0.2 V (weak inversion), and VTH+0.2 V (strong inversion) (B) Drain currents as a function of D2D threshold voltage variation ΔVTH, as obtained from Monte Carlo simulation

of 300 runs

the current in the strong inversion region has a small temperature dependence (0.5%/°C), the subthreshold current has a large temperature dependence (3%/°C), as shown in Fig 2-(A) Figure 2-(B) shows the simulated subthreshold current as a function of the threshold

voltage variation ΔVTH, as obtained from Monte Carlo simulation of 300 runs, assuming both die-to-die (D2D) variation (e.g., ΔVTH, Δμ, ΔTOX, ΔL, ΔW) and within die (WID) variation (e.g., σV TH , σμ, σT OX , σL, σW) in transistor parameters [21; 22; 23] Each open circle and square show IDS for a run The subthreshold current depends strongly on the threshold voltage variation (2.5%/mV) in comparison with the strong inversion current (0.8%/mV) Therefore, the subthreshold current is strongly dependent on temperature and process variations In circuit designs, the process sensitivity of the subthreshold current has to be reduced by using large-sized transistors [23] and various analog layout techniques [24] On the other hand, the exponential behavior and the high sensitivity to temperature of the subthreshold current can be used to compensate for temperature variation of a constant voltage, such as voltage reference circuits

3 Voltage and current references based on bandgap reference circuits

Bandgap voltage reference circuits are widely used as voltage references Figure 3 shows conventional bandgap voltage reference circuits [5],[6] The circuits generate reference voltages independent of the process, supply voltage, and temperature, and consist of the MOSFET circuits, substrate pnp bipolar transistors, and resistors The operation principles are as follows

CMOS Voltage and Current Reference Circuits consisting of Subthreshold MOSFETs 5

Fig 3 (A) Conventional bandgap voltage reference circuit [5] (B) Sub-1-V output bandgap

voltage reference circuit [6] and current reference circuit [25]

3.1 Operation as voltage reference circuit

The collector current IC of the bipolar transistor is given by

where K is the transistor size, IS is the saturation current, and VBE is the base-emitter voltage [5]

In the circuit in Fig 3-(A), the operation current IP is determined by the bipolar transistors

Q1 and Q2 with different transistor sizes and the resistor R1, and is given by

−

(8)

The current IP is proportional to absolute temperature (PTAT) The resistor R2 and the

transistor Q3 accept the current through the current mirror circuit and produce the output

voltage, which is given by

Equation (9) shows that VREF can be expressed as a sum of the base-emitter voltage and

thermal voltage scaled by the resistor ratio Because VBE has a negative T.C and VT has a

positive T.C., output voltage VREF with a zero T.C can be obtained by adjusting the resistor

ratio The reference voltage is based on the bandgap energy of silicon, which is about 1.25 V

Banba et al proposed a modified bandgap voltage reference circuit as shown in Fig 3-(B)

The circuit generates sub-1-V reference voltage The operation currents I1 and I2 are given by

The resistor R4 accepts the current IREF(=I1+I2) through a current mirror circuit and produces

output voltage, so the output voltage can be expressed as