Advances in Solid State Part 2 pdf

Limitations of low voltage and low power The average power consumption of the circuit is expressed by current short static P DD sc DD leakage o V C where f is the frequency, C is the cap

shows the rank-order function, whereas Fig 22(b) shows the function of the k-WTA On the

average, the accuracy of whole circuit was approximated 150 mV The performance of the

chip was degraded by many factors such as the mismatch in comparator cells, the different

capacitance at input terminals of the evaluation cells, and the clock feed-through error Due

to these non-ideal effects, each rank-order function was finished in 20 μs After increasing

supply voltage up to 1.5 V and proper biasing voltage V bias adjusting, the performance of the

circuit can be improved Including power consumption of the input/output pads, the static

power consumption of the chip was 1.4 mW

Many factors such as precision, speed, process variation, and chip area must be considered

for design of a low-power low-voltage rank order extractor

1 Limitations of low voltage and low power

The average power consumption of the circuit is expressed by

current short static

P

DD sc DD leakage o

V C

where f is the frequency, C is the capacitance in the circuit, V DD is the voltage supply, I o is the

standby current, I leakage is the leakage current, and the Q sc is the short-current charge during

the clock transient period In order to reduce the power consumption, the voltage supply

VDD must be reduced, and the standby current in the comparator and evaluation cell must

be designed as small as possible In mask layout, the clock and its complementary are

generated locally to reduce delay and mismatch Thus, the probability of a short current

occurring in the circuit is minimized

2 Speed and precision

The accuracy of the comparators determines the resolution of the circuit For the comparator

design, the smallest differential voltage, that is, distinguished correctly is influenced by two

factors One is the charge-injection error in analog switches, and the other is the parasitic

capacitor C p effect The effect is reduced by enlarging the sampling capacitor C s and making

the switches dimension as small as possible In the design, the response time τ of the

extractor is the summation of the auto-zero time τaz, the comparison time τcmp, and the

evaluation time τeval

eval cmp

τ

Reducing τaz, τcmp and τeval will improve the response time τ The minimum auto-zero

time τaz is required to sample the input voltage correctly at sampling capacitor C s and to

bias the inverter properly at high gain region The switches shown in Fig 19 with larger

dimension reduce auto-zero time τaz However, the clock feed-through error and charge

injection error will also be enlarged during the clock transition In the same situation, the

smaller sample capacitor C s will reduce the time τaz Unfortunately, it will reduce the

effective magnitude of the difference voltage; thus, the comparator accuracy is degraded

The comparison time τcmp dominates the response time τ, especially when the input levels

are close each other Since the amplification in the transition region of a CMOS inverter

operated at low voltage supply is not high enough, the comparator must take a long time to

identify which input variable has a larger level The evaluation time τeval is defined so that

the time interval between the comparator cells generates the proper currents and the

extractor has finished finding the desired rank order Time τeval is a function of the current

Iunit The maximum number M of input variables is also influenced by the current I unit

Although reducing the magnitude of the current I unit is able to reduce the power

consumption, however, the relationship among τeval , I unit, and M in this architecture is a

complicated function

3 Process variation analysis

With contemporary technology, process variation during fabrication cannot be completely

eliminated; as a result, mismatch error must be noticed in VLSI circuit design The match in

dimension of the binary-weight MOS in the evaluation cell (M1 - M8 in Fig 20) is an

important factor for the circuit operation If the mismatch error induces an error current I err

larger (or smaller) than half of the unit current I unit, decision of the evaluation cell fails Thus,

a rough estimated constraint for I err is

2/

unit err I

5 Conclusion

The chapter describes various nonlinear signal processing CMOS circuits, including a high

reliable WTA/LTA, simple MED cell, and low-voltage arbitrary order extractor We focus

the discussion on CMOS analog circuit design with reliable, programmable capability, and

low voltage operation It is a practical problem when the multiple identical cells are required

to match and realized within a single chip using a conventional process Thus, the design of

high-reliable circuit is indeed needed The low-voltage operation is also an important design

issue when the CMOS process scale-down further In the chapter, Section 1 introduces

various CMOS nonlinear function and related applications Section 2 describes design of

highly reliable WTA/LTA circuit by using single analog comparator The analog

comparator itself has auto-zero characteristic to improve the overall reliability Section 3

describes a simple analog MED cell Section 4 presents a low-voltage rank order extractor

with k-WTA function The flexible and programmable functions are useful features when

the nonlinear circuit will integrate with other systems Depend on various application

requirements, we must have different design strategies for design of these nonlinear signal

process circuits to achieve the optimum performance In state-of-the-art process, small chip

area, low-voltage operation, low-power consumption, high reliable concern, and

programmable capability still have been important factors for these circuit realizations

6 References

Aksin, D Y (2002) A high-precision high-resolution WTA-MAX circuit of O(N) complexity

IEEE Trans Circuits Syst II, Analog Digit Signal Process., vol 49, no 1, 2002, pp 48–

53

Cilingiroglu, U & Dake, L E (2002) Rank-order filter design with a sampled-analog

multiple-winners-take-all core IEEE J Solid-State Circuits, vol 37, Aug 2002, pp

978 – 984

Demosthenous, A.; Smedley, S & Taylor, J (1998) A CMOS analog winner-take-all network

for large-scale applications IEEE Trans Circuits Syst I, Fundam Theory Appl., vol

45, no 3, 1998, pp 300–304

Diaz-Sanchez, A.; Jaime Ramirez-Angulo; Lopez-Martin, A & Sanchez-Sinencio, E (2004) A

fully parallel CMOS analog median filter IEEE Trans Circuits Syst II, vol 51,

March 2004, pp 116 – 123

He, Y & Sanchez-Sinencio, E (1993) Min-net winner-take-all CMOS implementation

Electron Lett., vol 29, no 14, 1993, pp 1237–1239

Hosotani, S.; Miki, T.; Maeda, A & Yazawa, N (1990) An 8-bit 20-MS/s CMOS A/D

converter with 50-mW power consumption IEEE J Solid-State Circuits, vol 25, no

1, Feb 1990, pp 167-172

Hung, Y.-C & Liu, B.-D (2002) A 1.2-V rail-to-rail analog CMOS ranorder filter with

k-WTA capability Analog Integr Circuits Signal Process., vol 32, no 3, Sept 2002, pp

219-230

Hung, Y.-C & Liu, B.-D (2004) A high-reliability programmable CMOS WTA/LTA circuit

of O(N) complexity using a single comparator IEE Proc.—Circuits Devices and Syst.,

vol 151, Dec 2004, pp 579-586

Hung, Y.-C.; Shieh, S.-H & Tung, C.-K (2007) A real-time current-mode CMOS analog

median filtering cell for system-on-chip applications Proceedings of IEEE Conference

on Electron Devices and Solid-State Circuits (EDSSC), pp 361 – 364, Dec 2007, Tainan,

Taiwan

Lazzaro, J.; Ryckebusch, R.; Mahowald, M A & Mead, C A (1989) Winner-take-all

networks of O(N) complexity Advances in Neural Inform Processing Syst., vol 1,

1989, pp 703-711

Lippmann, R (1987) An introduction to computing with neural nets IEEE Acoust., Speech,

Signal Processing Mag., vol 4, no 2, Apr 1987, pp 4-22

Opris, I E & Kovacs, G T A (1994) Analogue median circuit Electron Lett., vol 30, no 17,

Aug 1994, pp 1369-1370

Opris, I E & Kovacs, G T A (1997) A high-speed median circuit IEEE J Solid-State

Circuits, vol 32, June 1997, pp 905-908

Semiconductor Industry Association (2008) International technology roadmap for

semiconductors 2008 update [Online] Available:

http://public.itrs.net/

Smedley, S.; Taylor, J & Wilby, M (1995) A scalable high-speed current mode

winner-take-all network for VLSI neural applications IEEE Trans Circuits Syst I, Fundam Theory

Appl., vol 42, no 5, 1995, pp 289–291

Starzyk, J.A & Fang, X (1993) CMOS current mode winner-take-all circuit with

both excitatory and inhibitory feedback Electron Lett., vol 29, no 10, 1993, pp 908–

910

Vlassis, S & Siskos, S (1999) CMOS analogue median circuit Electron Lett., vol 35, no 13,

June 1999, pp 1038-1040

Yamakawa, T (1993) A fuzzy inference engine in nonlinear analog mode and its

applications to a fuzzy logic control IEEE Trans Neural Netw., vol 4, no 3, May

1993, pp 496–522

Yuan, J & Stensson, C (1989) High - speed CMOS circuit technique IEEE J Solid-State

Circuits, vol 24, no 1, Feb 1989, pp 62-69

The portable electronic equipments are the trend in comsumer markets Therefore, the low power consumption and low supply voltage becomes the major challenge in designing CMOS VLSI circuitry However, designing for low-voltage and highly linear transconductor, it requires to consider many factors The first factor is the linear input range

The range of linear input is justified by the constant transconductance, G m Since the distortion of transconductor is determined by the ratio of output currents versus input voltage The second factor is the control voltage of transconductor This voltage can greatly impact the value of transconductance, linear range, and power consumption For example, when the control voltage increases, the transconductance also increase but the linear input range of transconductor is reduced and power consumption is increased Hence it is critical

in designing transconducotr operated at low supply voltage The third factor is the symmetry of the two differential outputs If the transconductance of the positive and

negative output is G m+=IO+/Vi and G m−=IO−/Vi , then how close G m+ and G m− should be is a

critical issue, where I O+ is the positive output current, I O− is the negative output current, and

Vi is the input differential voltage This factor is the major cause of common-mode distortion

of transconductor which occurs at outputs

In general, the design of differential transconductor can be classified into triode-mode and saturation-mode methods depending on operation regions of input transistors Triode-mode transconductor has a better linearity as well as single-ended performance On the other hand, saturation-mode transconductor has better speed performance However, it only exhibits moderate linearity performance Furthermore, the single-ended transconductor of saturation-mode suffers from significant degradation of linearity Several circuit design techniques for improving the linearity of transconductors have been reported in literatures The linearization methods include: source degeneration using resistors or MOS transistors

[Krummenacher & Joeh, 1988; Leuciuc & Zhang, 2002; Leuciuc, 2003; Furth & Andreou,

1995], crossing-coupling of multiple differential pairs [Nedungadi & Viswanathan, 1984;

Seevinck & Wassenaar, 1987] class-AB configuration [Laguna et al., 2004; Elwan et al., 2000;

Galan et al., 2002], adaptive biasing [Degrauwe et al., 1982; Ismail & Soliman, 2000;

Sengupta, 2005], constant drain-source voltages [Kim et al., 2004; Fayed & Ismail, 2005;

Mahattanakul & Toumazou, 1998; Zeki, 1999; Torralba et al., 2002; Lee et al., 1994;

Likittanapong et al., 1998], pseudo differential stages [Gharbiya & Syrzycki, 2002], and shift

level biasing [Wang & Guggenbuhl, 1990]

Source degeneration using resistors or MOS transistors is the simplest method to linearize

transconductor However, it requires a large resistor to achieve a wide linear input range In

addition, MOS used as resistor exhibits considerable varitions affected by process and

temperture and results in the linearity degradation Crossing-coupling with multiple

differential pairs is designed only for the balanced input signals The Class-AB configuration

can achieve low power consumption On the other hand, the linearity is the worst due to the

inherited Class-AB structure The adaptive biasing method generates a tail current which is

proportional to the square of input differential voltage to compensate the distortion caused

by input devices However, the complication of square circuitry makes this technique hard

to implement The constant drain-source voltage of input devices is a simple structure It can

achieve a better linearity with tuning ability However, it needs to maintain V DS of input

devices in low voltage and triode region Therefore, this technique is difficult to implement

in low supply voltage Hence, a new transconductor using constant drain-source voltage in

low voltage application is proposed to achieve low-voltage, highly linear, and large tuning

range abilities

In section 2, basic operatrion and disadvantage of the linerization techniques are described

The proposed new transconductor is presented in section 3 The simulation results and

conclusion are given in section 4 and 5

2 Linearization techniques

In this section, reviews of common linearization techniques reported in literatures are

presented The first one is the transconductor using constant drain-source voltage The

second one is using regulated cascode to replace the auxiliary amplifier The third one is

transconductor with source degeneration by using resistors and MOS transistors The last

one is the linear MOS transconductor with a adaptive biasing scheme Besides introducing

their theories and analyses, the advantages and disadvantages of these linearization

techniques are also discussed

2.1 Transconductor using constant drain-source voltage

The idea of transconductors using constant drain-source voltages is to keep the input

devices in triode region such that the output current is linearized The schematic of this

method is shown in Fig 1 Considering that transistors M1, M2 operate at triode region, M3,

M4 are biased at saturation region, channel length modulation, body effect, and other

second-order effects are ignored, the drain current of M1 and M2 is given by

V V V V

where β =μnCOX (W/L), V GS is the gate-to-source voltage, V T is the threshold voltage, and V DS

is the drain-to-source voltage If the two amplifiers in Fig 1 are ideal amplifiers, then

C DS

Fig 1 Transconductor using constant drain-source voltage

The transfer characteristic of this transconductor is given by

2 1

2 1 1 1

out

V V V V V

V V V

2 2

2 2 2 2

out

V V V V V

V V V

In fact, it is difficult to design an ideal amplifier implemented in this circuits However, it

can force VDS1 =VDS2 =VDS by using two auxiliary amplifiers controlled with the same VC to

keep VDS at the constant value Therefore, the transfer characteristic of this transconductor is

2 1

2 1 1 1

out

V V V V V

V V V

2 2

2 2 2 2

out

V V V V V

V V V

, where VGS1= Vin1 and VGS2= Vin2

Therefore, the new transconductance value is

DS

The linearity of this transconductor is moderated It is also easy to implement in circuit

However, VDS of the input devices must be small enough to keep transistors in triode region

The following condition has to be satisfied:

T GS

On the other hand, the auxiliary amplifiers need to design carefully to reduce the overhead

of extra area and power

2.2 Transconductor using regulated cascode to replace auxiliary amplifier

In Fig 2(a) regulating amplifier keeps VDS of M1 at a constant value determined by VC It is

less than the overdrive voltage of M1 The voltage can be controlled from VC so as to place

M3 in current-voltage feedback, thereby increasing output impedance The concept is to

drive the gate of M3 by an amplifier that forces VDS1 to be equal to VC Therefore, the voltage

variations at the drain of M3 affect VDS1 to a lesser extent because amplifiers “regulate” this

voltage With the smaller variations at VDS1, the current through M1 and hence output

current remains more constant, yielding a higher output impedance [Razavi, 2001]

1 3

3O O m

It is one of solutions using regulated cascode to replace the auxiliary amplifier in order to

overcome restrictions on Fig 1 The circuit in Fig 2(b) proposed in [Mahattanakul &

Toumazou, 1998] uses a single transistor, M5, to replace the amplifier in Fig 2(a) This circuit

called regulated cascode which is abbreviated to RGC The RGC uses M5 to achieve the gain

boosting by increasing the output impedance without adding more cascode devices VDS1 is

calculated by follows: Assuming M5 is in saturation region in Fig 2(b) It can be shown that

5 52

1

T GS

5 1

5

2

T C C DS

2

T C C

=

5 1

1 1

2

T C C DS

G

ββ

voltage source VC or current source IC However, it is preferable in practice to use a

controllable voltage source VC for lowering power consumption since VDS1 only varies as a

square root function of IC

Simple RGC transconductor using a single transistor to achieve gain boosting can reduce

area and power wasted by the auxiliary amplifiers However, it still has some

disadvantages First, it will cause an excessively high supply-voltage requirement and also

produce an additional parasitic pole at the source of transistors Therefore, it can not apply

to the low-supply voltage design Second, the tuning range of VDS1 is restricted The smallest

value of VDS1 is I + C V T

5

2

β when VC = 0 In other words, VDS1 can not be set to zero Owing

to the restriction of (7), VDS is as low as possible and the best value is zero Third, VT

dependent Gm may be a disadvantage due to the substrate noise and VT mismatch problems

[Lee et al., 1994]

In Fig 3, another RGC transconductor that can apply to the low-voltages applications is

proposed in [Likittanapong et al., 1998] The circuit overcomes the disadvantages mentioned

above is to utilize PMOS transistor that can operate in saturation region as gain boosting

The use of this PMOS gain boosting in the feedback path can result in a circuit with a wide

transconductance tuning range even at the low supply voltage In [Likittanapong et al.,

1998], it mentions that at the maximum input voltage, M3 may be forced to enter triode

region, especially if the dimension of M2 is not properly selected, resulting in a lower

dynamic range Besides, β2 may be chosen to be larger for a very low distortion

transconductor It means that the tradeoff between linearity and bandwidth of

transconductor is controlled by β2 Therefore, β2 should be selected to compromise these two

characteristics for a given application

VDS1 is calculated by follows Assuming M3 is in saturation region in Fig 3

( )2

3 3 32

1

T GS

3 1 3

2

T C DS C

−

3 1

2

T C C

−

=

3 1

1 1

2

T C C DS

G

ββ

β Therefore, this transconductor has a wider tuning range compared to that of

RGC transconductor and is capable of working in low-supply voltage (3V) However, this

transconductor still has some drawbacks The major drawback is the tuning ability For

example, it is difficult to control 3

3

2

T C

β if V DS1 is set to zero The minor drawback

is that V T depends on the Gm It also may cause substrate noise and V T mismatch problems

Fig 3 RGC transconductor with PMOS gain stage

2.3 Transconductor using source degeneration

A simple differential transconductor is shown in Fig 4(a) Assuming that M1 and M2 are in

saturation and perfectly matched, the drain current is given by

The transfer characteristic using (5) is given by

( GS T)

i i

SS SS

i i

SS out

out

V V

I I

V V

I I

I I

812

2 2

2

, where Vi = (Vin1 −Vin2)

If V GS is large enough, the higher linearity can be achieved Unfortunately, it can not be used

in the low-voltage application and the linear input range is limited Simplest techniques to

linearize the transfer characteristic of MOS transconductor is the one with source

degeneration using resistors as shows in Fig 4(b) The circuit is described by

2

1 GS GS out

i SS out

I RI V RI

V I I

812

g G

m

m

where g m is the transconductance of transistor M1 and M2

We should notice that in (14), the nonlinear term depends on V i − RIout rather than Vi Higher

linearity can be achieved when R >> 1/g m The disadvantage of this transconductor is that

large resistor value is needed in order to maintain a wider linear input range Owing to

Gm ≈ 1/R, the higher transconductance is limited by the smaller resistor Hence, there is a

tradeoff between wide linear input range and higher transconductance which is mainly

Another method to linearize the transfer characteristic of MOS transconductor is using source

degeneration to replace the degeneration resistor with two MOS transistors operating in triode

region The circuit is shown in Fig 5 Notice that the gates of transistor M3 and M4 connect to

the differential input voltage rather than to a bias voltage To see that M3 and M4 are generally

in triode region, we look at the case of the equal input signals (V in1=Vin2), resulting in

1

1 GS in y

Therefore, the drain-source voltages of M3 and M4 are zero However, V DS of M3 and M4

equal those of M1 and M2 Owing to (7), M3 and M4 are indeed in triode region Assuming

M3, M4 are operating in triode region, the small-signal drain-source resistance of M3, M4 is

given by

( GS T)

ds ds

V V r

1

It must be noted that in this circuit the effect of varying V DS of M1 and M2 can not be ignored

since the drain currents are not fixed to a constant value The small-signal source resistance

of M1, M2 is given by

( 1 1)

1 1 2 1

11

T GS m

2 1 1

||ds

ds s s

in in o

r r r r

V V i

++

−

3 1 3 1 14

2

in in T GS

+

=ββββ

1

T GS

1 1 1

2

βSS

T GS

I V

24

2

in in SS

(21)

The transconductance G m is

1 3 1 3

4

2

ββββ

m

I G

+

Linearity can be enhanced (assuming r ds3 >> rs1) compared to that of a simple differential pair because transistors operated in triode region exhibits higher linearity than the source resistances of transistors operated in saturation region When the input signal is increased, the small-signal resistance in one of two triode transistors in parallel, M3 or M4, is reduced Meanwhile, the reduced resistance results in the lower linearity and the larger

transconductance As discussed in [Krummenacher & Joeh, 1988], if the proper size ratio of

β1 /β3 is chosen, the balance between higher linearity and stable transconductance can be

achieved How to choose the optimum size ratio of β1 /β3 for the best linearity performance

becomes slightly dependent on the quiescent overdrive voltage, V GS−VT The size ratio of β1

/β3=6.7 is used to achieve the best linearity performance

According to (22), the transconductance can be tuned by changing I SS and size ratio of β1 /β3

Nevertheless, the nonlinearity error is up to 1% for I out /ISS < 80% It is required to have a better linearity so as to achieve a THD of -60 dB or less in some filtering applications [Kuo & Leuciuc, 2001]

Fig 5 Transconductor with source degeneration using MOS transistors

2.4 Transconductor using adaptive biasing

The transconductor using adaptive biasing is shown in Fig 6 All transistors are assumed to

be operated in saturation region, neglecting channel lengh modulation effect First, transistor M3 is absent, and output current as a function of two input voltages V in1 and V in2 is obtained as

1 1

2 V GS V T

2 2

2 V GS V T

SS in in in

in SS out

I V V V

V I I I I

41

2 2 1 2

1 2

, where I SS is a tail current and equals I B

An adaptive biasing technique is using a tail current containing an input dependent

quadratic component to cancel the nonlinear term in (23) Consequently, the circuit in Fig 6

changes the tail current by adding transistor M3 The tail current will be changed by

C B

2 1

C

I I B

Fig 6 Transconductor with adaptive biasing

3 New transconductor

The conventional structure which uses the constant drain source-voltage such as RGC with

NMOS or PMOS can not operate at 1.8V or below The main reason is that auxiliary amplifier

under the low supply voltage can’t provide enough gain to keep the constant drain-source

voltage Therefore, we propose a triode transconductor which uses new structure to replace

the auxiliary amplifier Fig 7 shows the proposed triode transconductor structure

MOS M5, M7, M9 and M11 are made up a two-stage amplifier to replace the auxiliary

amplifier The two-stage amplifier is implemented using M9 with the active loads M11

formed the first stage and M5 with the active load M7 formed the second stage The first and

second stages exhibit gains equal to

( 1 11)9

Fig 7 Proposed triode transconductor

Therefore, the overall gain is

( 11) 5( 5 7)

1 9 9 2

1

out I

Fig 8 The proposed transconductor

Considering that the large gain is achieved and is able to keep transistors M1 and M2 in

triode region, the drain current of M1 and M2 is given by

out

V V V V

out

V V V V

The transfer characteristic is given by