Introduction to computing laboratory manual implementation of basic logic gates and functional ics on fpga

IMPLEMENTATION OF DIGITAL CIRCUIT ON BREADBOARD

Breadboard is the component on which the circuits can be set up and external experiments can be done The information about usage is given in Figure 1.1

❖ Remember these points when implement digital circuits on breadboard :

- Inserting a DIP – Dual Inline Package:

Before inserting a DIP into the breadboard, ensure that all pins are straight and that the pins on one side of the DIP do not connect to those on the opposite side This requires positioning the DIP across one of the long gaps that separate the breadboard into distinct sections.

- Providing access to the DIP:

When wiring your circuit, ensure that the DIP's pins are easily accessible for probing and allow for straightforward replacement of the DIP without the need to disconnect any wires.

 Never pass a wire over a DIP Instead, route the wires around the DIP

 When you run wires to a DIP, use the breadboard holes farther away from the DIP before you use the holes that are closer

To avoid damaging a DIP by bending its pins, refrain from using your fingers for removal from the breadboard; instead, opt for a chip puller to gently lift the chip.

Digital integrated circuits (ICs), primarily TTL, operate on two logic levels: HIGH (1) and LOW (0) A signal is classified as HIGH when the voltage ranges from 2V to 5V, while it is considered LOW when the voltage falls between 0V and 0.8V.

Output: the signal is called HIGH when the voltage is between 2.7V and 5V, and LOW when the voltage is from 0 to 0.5V

We usually apply 5V to implement HIGH level signal and 0V for LOW level signal

In this lab, DIP switches provide the input signal, with various connection methods illustrated in Figure 1.2 The circuits typically utilize 10 Kohm resistors Students are advised to construct the input circuit depicted in Figure 1.2 (c), where the signal is set to 1 when the switch is in the upper position and 0 when it is in the lower position.

Outputs are typically indicated using various types of LEDs, including standard LEDs, bar-LEDs, and 7-segment LEDs As illustrated in Figure 1.3, the left circuit activates the LEDs when the signal is at level 1, while the right circuit turns off the lights under the same signal condition In these output circuits, resistors are generally selected with a value of 1 Kohm.

Figure 1.4: Implementation of Boolean function F(a,b) = a + b

Figure 1.5: Implementation of Boolean function F(a,b) = a + b – application circuit.

QUESTIONS

1 What is numbering principle in DIP IC?

2 Identify X, Y, Z, W in four circuits below:

3 If f1,f2,f3,f4 are respectively 0,1,1,0 Indentify status of each LEDs in below figure

4 Hoàn thành bảng sau (xem datasheet c a chúng) ủ

74LS00 4 c ng NAND ổ 14-VCC; 7- GND; 3 = 1 nand 2; 6 = 4 nand 5; …….

74LS02 74LS04 74LS08 74LS32 74LS86 74LS125 74LS126 74LS138 74LS151

5 Compare IC 74LS125 and IC 74LS126 Explain the difference between these 2 ICs

6 Implement boolean function 𝑓(𝑥, 𝑦, 𝑧 = 𝑥 𝑦 + 𝑦𝑧 ) : ICs and quantity:

Circuit implementation (remember to note pin numbers on ICs)

7 Implement boolean function 𝑓(𝑥, 𝑦, 𝑧 = 𝑥 𝑦 + 𝑦𝑧 ) using NAND2 gates (2-input NAND gates)

Convert the function using NAND equivalents:

8 Implement Boolean function 𝑓(𝑥, 𝑦, 𝑧) = m1 + m3 + m6 (z is LSB):

List all ICs used to implement the circuit:

9 Implement boolean function 𝑓(𝑥, 𝑦, 𝑧) = m1 + m3 + m6, using NOR2 gates (2-input NOR gates)

Convert the function using NOR equivalents:

Draw the circuit that implement F using IC 74LS151 and logic gates:

Circuit implementation (remember to note pin numbers on ICs).

LAB MANUAL

OBJECTIVES

- Getting familiar with TTL 74LS series IC

- Implementation of simplified Boolean functions with different logic gate combinations

- Getting to know functional combinational ICs.

LAB PREPARATION

Students have to complete Prelab before class Students without lab preparation won’t be allowed to join in the class.

LAB INSTRUCTION

Objectives: Implementation of a function math 𝑓(𝑥, 𝑦, 𝑧 = 𝑥 𝑦 + 𝑦𝑧 ) in AND – OR form

- Integrated Circuits (ICs) : 74LS04, 74LS08, 74LS32

- Construct the circuit and apply the power (remember to note pin numbers on ICs)

- Apply all possible combinations to the inputs obtain the output values then take note of ; the output f Test in the Table 1.1 x y z f f Test f nand

➢ Draw the schematic that implement F using NAND equipvalents

NAND equipvalent circuit – application circuit

- Construct the circuit and apply the power (remember to note pin numbers on ICs).

- Apply all possible combinations to the inputs and obtain and take note of the outputs f NAND in the Table 1.1 Student’s implementation on breadboard

Objectives: Implementation of a boolean function given in the truth table (Figure 1.2)

- Apply all possible combinations to the inputs obtain the output values then take note of ; the output f Test in the Table 1.2

- Write the Boolean expression: F = x y z f f Test f nor

➢ Draw the schematic that implement F using NOR equipvalents

NOR equipvalent circuit – application circuit

- Apply all possible combinations to the inputs; obtain the output value then take note of the outputs f NOR in the Table 1.2

Objectives: Implementation of a boolean function given in the following schematic

- Integrated Circuits (ICs) : 74LS04, 74LS08, 74LS32, 74LS86

- Apply all possible combinations to the inputs obtain the output value then take note of the ; outputs F in the Table 1.3 1 x y z F 1 F 2

➢ Optimize boolean function F1 and draw the schematic: F2 =

- Construct the circuit and apply the power (remember to note IC codes and their pin numbers)

- Apply all possible combinations to the input obtain the output value then take note of the ; outputs F2 in the Table 1.3

➢ Give your comments on F1 and F2 results:

Objectives: Implementation of a Boolean function 𝑓(𝑥, 𝑦, 𝑧) = ∑( 2,3,5,7 ) by using a 8x1 Multiplexer

Connection diagram and function table:

- Integrated Circuits (ICs): 74LS151, 74LS04

Draw the schematic diagram to implement the boolean function using 74LS151

- Construct the circuit and apply the power (remember to note IC pin numbers)

- Apply all possible combinations to the inputs and obtain and take note of the outputs F Test in the Table 1.4 x y z f f Test

Objectives: Implementation of a Boolean function (𝑥, 𝑦, 𝑧) = ∑( 2,3,5,7 ) by using a 3x8 Decoder

- Integrated Circuits (ICs): 74LS138, and other logic gates

Connection diagram and function table: x y z f f Test

- Apply all possible combinations to the inputs and obtain and take note of the outputs F Test in the Table 1.5

IMPLEMENTATION OF BASIC LOGIC GATES AND FUNCTIONAL

PRELAB

I IMPLEMENTATION OF DIGITAL CIRCUIT ON BREADBOARD

Breadboard is the component on which the circuits can be set up and external experiments can be done The information about usage is given in Figure 1.1

❖ Remember these points when implement digital circuits on breadboard :

- Inserting a DIP – Dual Inline Package:

Before inserting a DIP into the breadboard, ensure that all pins are straight and properly aligned It's crucial to position the DIP so that the pins on one side do not connect with those on the opposite side, which requires placing the DIP across one of the long gaps that separate the breadboard into distinct sections.

- Providing access to the DIP:

When wiring your circuit, ensure that the DIP's pins are easily accessible for probing and allow for straightforward replacement of the DIP without needing to disconnect any wires.

 Never pass a wire over a DIP Instead, route the wires around the DIP

 When you run wires to a DIP, use the breadboard holes farther away from the DIP before you use the holes that are closer

To prevent bent pins when removing a DIP from a breadboard, avoid using your fingers, as they can easily slip and twist the chip Instead, utilize a chip puller for a gentle and safe extraction of the chip from the board.

Digital integrated circuits (ICs), primarily based on Transistor-Transistor Logic (TTL), operate at two logic levels: HIGH (1) and LOW (0) A signal is classified as HIGH when the voltage ranges from 2V to 5V, while a LOW signal is defined by a voltage between 0V and 0.8V.

Output: the signal is called HIGH when the voltage is between 2.7V and 5V, and LOW when the voltage is from 0 to 0.5V

We usually apply 5V to implement HIGH level signal and 0V for LOW level signal

In this lab, DIP switches are utilized to provide the input signal, with various connection methods illustrated in Figure 1.2 Typically, resistors in these circuits are selected at 10 Kohm Students are advised to construct the input circuit as depicted in Figure 1.2 (c), where the signal is equal to 1 when the switch is in the upper position and 0 when it is in the lower position.

Outputs are typically indicated using various types of LEDs, including standard LEDs, bar-LEDs, and 7-segment LEDs In the provided diagram, the left circuit illuminates the LEDs when the signal is high (1), whereas a high signal in the right circuit turns off the LEDs Generally, resistors used in these output circuits are selected at a value of 1 kΩ.

Figure 1.4: Implementation of Boolean function F(a,b) = a + b

Figure 1.5: Implementation of Boolean function F(a,b) = a + b – application circuit

1 What is numbering principle in DIP IC?

2 Identify X, Y, Z, W in four circuits below:

3 If f1,f2,f3,f4 are respectively 0,1,1,0 Indentify status of each LEDs in below figure

4 Hoàn thành bảng sau (xem datasheet c a chúng) ủ

74LS00 4 c ng NAND ổ 14-VCC; 7- GND; 3 = 1 nand 2; 6 = 4 nand 5; …….

74LS02 74LS04 74LS08 74LS32 74LS86 74LS125 74LS126 74LS138 74LS151

5 Compare IC 74LS125 and IC 74LS126 Explain the difference between these 2 ICs

6 Implement boolean function 𝑓(𝑥, 𝑦, 𝑧 = 𝑥 𝑦 + 𝑦𝑧 ) : ICs and quantity:

7 Implement boolean function 𝑓(𝑥, 𝑦, 𝑧 = 𝑥 𝑦 + 𝑦𝑧 ) using NAND2 gates (2-input NAND gates)

Convert the function using NAND equivalents:

8 Implement Boolean function 𝑓(𝑥, 𝑦, 𝑧) = m1 + m3 + m6 (z is LSB):

List all ICs used to implement the circuit:

9 Implement boolean function 𝑓(𝑥, 𝑦, 𝑧) = m1 + m3 + m6, using NOR2 gates (2-input NOR gates)

Convert the function using NOR equivalents:

- Getting familiar with TTL 74LS series IC

- Implementation of simplified Boolean functions with different logic gate combinations

- Getting to know functional combinational ICs

Students have to complete Prelab before class Students without lab preparation won’t be allowed to join in the class

Objectives: Implementation of a function math 𝑓(𝑥, 𝑦, 𝑧 = 𝑥 𝑦 + 𝑦𝑧 ) in AND – OR form

- Apply all possible combinations to the inputs obtain the output values then take note of ; the output f Test in the Table 1.1 x y z f f Test f nand

➢ Draw the schematic that implement F using NAND equipvalents

NAND equipvalent circuit – application circuit

- Construct the circuit and apply the power (remember to note pin numbers on ICs).

- Apply all possible combinations to the inputs and obtain and take note of the outputs f NAND in the Table 1.1 Student’s implementation on breadboard

Objectives: Implementation of a boolean function given in the truth table (Figure 1.2)

- Apply all possible combinations to the inputs obtain the output values then take note of ; the output f Test in the Table 1.2

- Write the Boolean expression: F = x y z f f Test f nor

➢ Draw the schematic that implement F using NOR equipvalents

NOR equipvalent circuit – application circuit

- Apply all possible combinations to the inputs; obtain the output value then take note of the outputs f NOR in the Table 1.2

- Integrated Circuits (ICs) : 74LS04, 74LS08, 74LS32, 74LS86

- Apply all possible combinations to the inputs obtain the output value then take note of the ; outputs F in the Table 1.3 1 x y z F 1 F 2

➢ Optimize boolean function F1 and draw the schematic: F2 =

- Construct the circuit and apply the power (remember to note IC codes and their pin numbers)

- Apply all possible combinations to the input obtain the output value then take note of the ; outputs F2 in the Table 1.3

➢ Give your comments on F1 and F2 results:

Objectives: Implementation of a Boolean function 𝑓(𝑥, 𝑦, 𝑧) = ∑( 2,3,5,7 ) by using a 8x1 Multiplexer

Connection diagram and function table:

- Integrated Circuits (ICs): 74LS151, 74LS04

- Apply all possible combinations to the inputs and obtain and take note of the outputs F Test in the Table 1.4 x y z f f Test

Objectives: Implementation of a Boolean function (𝑥, 𝑦, 𝑧) = ∑( 2,3,5,7 ) by using a 3x8 Decoder

- Integrated Circuits (ICs): 74LS138, and other logic gates

Connection diagram and function table: x y z f f Test

- Apply all possible combinations to the inputs and obtain and take note of the outputs F Test in the Table 1.5

LAB 2: IMPLEMENTATION OF BASIC LOGIC

GATES AND FUNCTIONAL ICs ON FPGA

Họ và tên: Lớp TN:

In Lab 2, the project utilizes the LEDR, LEDG, and SW peripherals The following are the essential header codes for these peripherals that students will use when synthesizing a project in Intel Quartus Remember to import the DE2_pin_list/assignment file.

Note, the top-level file of the project must be named the name of the header file, for example

"lab2tn1_wrapper", with the module "lab2tn1" being the module containing the code describing the design of experiment 1

Ex: The experiment of writing hardware design in SystemVerilog language for the function 𝑓(𝑥, 𝑦, 𝑧) = x𝑦𝑧 as experiment 1 of lab 2, we have the following SystemVerilog code:

Figure 2.1: Implementation of 𝑓(𝑥, 𝑦, 𝑧) = 𝑥𝑦𝑧 – module “lab2tn1”

Below is top level “lab2tn1_wrapper” that implement 𝑓(𝑥, 𝑦, 𝑧) = x𝑦𝑧:

Figure 2.2: Implementation of 𝑓(𝑥, 𝑦, 𝑧) = 𝑥𝑦𝑧 – module “lab2tn1_wrapper”

Next, students perform the simulation, and load the Kit as instructed at Lab 0

For the experiments that require the use of IC 74LS151/74LS138, students write the code describing this IC and call that module as above

Objective: Implementation of Boolean function 𝑓(𝑥, 𝑦, 𝑧) = 𝑥𝑦𝑧 + 𝑥𝑦 𝑧 + 𝑥𝑦 on FPGA DE2.

● Construct the truth table of 𝑓(𝑥, 𝑦, 𝑧) = 𝑥𝑦𝑧 + 𝑥𝑦 𝑧 + 𝑥𝑦

● Write the SystemVerilog code that describe 𝑓(𝑥, 𝑦, 𝑧) = 𝑥𝑦𝑧 + 𝑥𝑦  𝑧 + 𝑥𝑦s instructed in lab 0 with the following pin assignment:

○ Pins x, y, z assigned to SW2, SW1, SW0 and LEDR2, LEDR1, LEDR0 respectively

● Compile and simulate the project The output waveform have to show all possible input combinations Capture the output waveform

Objectives: Write SystemVerilog code to describe the truth table in Table 2.1

● Write the SystemVerilog code that describe the digital circuit in Figure 2.3 with the following pin assignment:

Objective: Write SystemVerilog code to describe the digital circuit in Figure 2.3.

● Write the SystemVerilog code that describe the digital circuit in Figure 2.3 with the following pin assignment:

Objective: Write SystemVerilog code to describe IC Multiplexer 74LS151 Implement function 𝑓(𝑥, 𝑦, 𝑧) = ∑(1,2,4,7) using that multiplexer.

● Write SystemVerilog code describe IC multiplexer 74LS151 operation.

● Using above multiplexer, write SytemVerilog code implementing Boolean function 𝑓(𝑥, 𝑦, 𝑧) = ∑(1,2,4,7):

○ Call IC 74LS151 as a submodule

Objective: Write SystemVerilog code to describe IC Decoder 74LS1 38 Implement function 𝑓(𝑥, 𝑦, 𝑧) = ∑(0,2,5,7) using that decoder.

● Write SystemVerilog code describe IC decoder 74LS138 operation.

● Using above decoder, write SytemVerilog code implementing Boolean function 𝑓(𝑥, 𝑦, 𝑧) = ∑(0,2,5,7):

○ Call IC 74LS1 38 as a submodule

- Understand how to use FPGA kits, programming software

- Understand how to design a basic functional ICs on FPGA

- Understand the process of describing hardware on FPGAs

- To prepare well for the test, students MUST read Appendix 1 first and complete the steps of Sample lab in Appendix 2, and submit it with Prelab 2 before entering class

- Students must complete and submit Prelab 2 before entering class

Students should consult the appendix and the DE2 Kit Manual to learn about the DE2 Kit's usage, wiring, and peripherals, as well as how to utilize Quartus software for circuit simulation and synthesis Additionally, the documentation serves as a valuable resource for understanding how to write hardware designs using the SystemVerilog language.

Objectives: Implementation of a function math 𝑓(𝑥, 𝑦, 𝑧 = 𝑥 𝑦 + 𝑦𝑧 ) on DE 2 kit

➢ Apply all possible combinations to the inputs and take note the outputs in the f column of Table 2.2

➢ Draw the logic diagram of F:

➢ Write the SystemVerilog describe the operation of 𝑓(𝑥, 𝑦, 𝑧) = 𝑥𝑦𝑧 + 𝑥𝑦 𝑧 + 𝑥𝑦 with the pin assignment as follows: o Pins x, y, z assigned to SW2, SW1, SW0 and LEDR2, LEDR1, LEDR0 respectively o Pin f assigned to LEDG0

➢ Synthesize the SystemVerilog design and take note the output in the f sim column in

(Insert a photo demonstrating simulation results)

➢ Students view the result of the circuit (Tool → Netlist Viewer → RTL Viewer) Is this result similar to the logic gate diagram drawn above? Exlain

➢ Download the code to DE2 Kit Does the design perform exactly as required? Take note the results in f Kit column of Table 2.2

(Project demonstration on DE2 kit)

Objectives: Implementation of a boolean function given in the truth table on DE 2 kit

➢ Write the Boolean expression of f (x, y, z):

➢ Draw the logic diagram of f:

➢ Write the SystemVerilog describe the operation of 𝑓(𝑥, 𝑦, 𝑧) with the pin assignment as follows: o Pins x, y, z assigned to SW2, SW1, SW0 and LEDR2, LEDR1, LEDR0 respectively o Pin f assigned to LEDG0

Objectives: Write SystemVerilog code to describe IC Multiplexer 74LS1 51

Implement function 𝑓(𝑥, 𝑦, 𝑧) = ∑(1,2,4,7) using that multiplexer x y z f f sim f Kit

➢ Draw the circuit that implement f(x,y,z) using 74LS151

➢ Write SystemVerilog code describe IC multiplexer 74LS151 operation.

➢ Using above multiplexer, write SytemVerilog code implementing Boolean function 𝑓(𝑥, 𝑦, 𝑧) = ∑(1,2,4,7): o Pins x, y, z assigned to SW2, SW1, SW0 and LEDR2, LEDR1, LEDR0 respectively o Pin f assigned to LEDG0 o Call IC 74LS151 as a submodule

Table 2.5 (Insert a photo demonstrating simulation results)

Objectives: Write SystemVerilog code to describe IC Decoder 74LS138

Implement function 𝑓(𝑥, 𝑦, 𝑧) = ∑(0,2,5,7) using that decoder x y z f f sim f Kit

➢ Draw the circuit that implement f(x,y,z) using 74LS138

➢ Write SystemVerilog code describe IC decoder 74LS138 operation.

➢ Using above multiplexer, write SytemVerilog code implementing Boolean function 𝑓(𝑥, 𝑦, 𝑧) = ∑(0,2,5,7): o Pins x, y, z assigned to SW2, SW1, SW0 and LEDR2, LEDR1, LEDR0 respectively o Pin f assigned to LEDG0 o Call IC 74LS138 as a submodule

Table 2.5 (Insert a photo demonstrating simulation results)

QUARTUS AND UBUNTU INSTALLATION ON WINDOWS 48 A UBUNTU INSTALLATION ON WINDOWS

Download and install Xming and WSL2

Xming is X Server on Windows operating system, used to run Linux applications on Windows

Xming download link: https://sourceforge.net/projects/xming/

Download WSL2 Kernel: (only do this step if the computer uses Windows 11 operating system) WSL2 Kernel is a tool that allows users to run Linux in Windows

Link download: https://wslstorestorage.blob.core.windows.net/wslblob/wsl_update_x64.msi

Install Ubuntu on Windows

Step 1: Turn on Windows Subsystem for Linux

- Open Control Panel ➔ Programs and Features ➔ “Turn Windows features on or off”

- Select “Windows Subsystem for Linux, Virtual Machine Platform”

- For Windows 11, install WSL2 Kernel

Figure Appendix 1.1 “Turn Windows features on or off”

- Set Username and Password Note: the password will NOT be displayed on the screen

Figure Appendix 1.4 Setting UNIX username and password

To determine the working directory of Ubuntu in Windows, use the command `cd ~; explorer.exe ` This will open the home directory where you can find a folder named after your username Right-click on this folder and select "Pin to Quick Access" for easy access All files and folders created in Ubuntu are stored within this username folder.

Bướ c 3: Download the following file ( install203.tar ) and save it in a folder named username set: https://drive.google.com/file/d/1F2aKS83WR8D6xWmu1k4xSWetmcbcmeue/view?usp=shar ing

Figure Appendix 1.5 Position of “install203” folder

Test: After completing the above steps, when booting Ubuntu ➔ type “ ls ” (list the files in the directory) ➔ the install203.tar file appears

Install the install203.tar file :

Open Ubuntu 22.04.1 LTS and run the following command:

Some basic commands in Linux

In the Ubuntu terminal, in front of the $ Displays the name of the current directory

Essential Linux commands include: `ls` to list files in a directory, `tree` for a visual directory tree, and `mkdir abc` to create a new directory named "abc." Use `cd abc` to navigate into the "abc" directory, and `cd ` to return to the previous directory To create or edit a file named "file1.sv," use `micro file1.sv` The command `cp file1.sv file2.sv` copies "file1.sv" to the current directory as "file2.sv," while `cp file1.sv abc/` transfers it to the "abc" folder For renaming, `mv file1.sv file0.sv` changes "file1.sv" to "file0.sv," and `mv file0.sv abc/` moves it to the "abc" folder To move files, `mv abc/file3.sv ` brings "file3.sv" from the "abc" directory to the current directory To copy an entire directory, use `cp -r abc/ xyz/` to create a new directory "xyz" with the contents of "abc." The command `pwd` displays the current directory path, and `rm file1.sv` deletes "file1.sv," while `rm file2.sv xyz/file1.sv` removes "file2.sv" and "file1.sv" in the "xyz" folder.

You should type these commands in the above order, each time you enter, remember to enter ls or tree , and pwd to understand how it works

Micro : Alt+G for keyboard shortcuts, for example “^S Save” means to Save, press Ctrl+S

INSTALL QUARTUS 13.0SP1

Step 1: Download and install Quartus 13.0sp1

Download link: https://www.intel.com/content/www/us/en/software-kit/711791/intel-quartus- ii-web-edition-design-software-version-13-0sp1-for-windows.html

Unzip the installation file Right click the Setup file ➔ select Run as Administrator

Choose the installation address as C:\altera Note: When installing Quartus, select components : select Cyclone devices to communicate with DE2 and DE10 kit

Step 2: Install the communication driver with the FPGA kit

- USB connection between the FPGA kit and the computer Power supply to the FPGA kit

- Open Control Panel ➔ Device Manager ➔ Other devices, right click USB-Blaster

➔ select Update Driver ➔ Browse for drivers on your computer ➔ select the path to the folder containing the USB – Blaster.

DIGITAL CIRCUIT DESIGN FLOW USING

DESIGN FLOW

Figure Appendix 2.1 Digital design flow using SystemVerilog

1 RTL Coding: Algorithm design, FSM, to solve the set requirements, the design language here is SystemVerilog HDL

2 Lint Check: Checks for syntax/syntax errors or coding practices that may cause errors or bugs Lint needs to be run after writing the code Note, Lint Check is a static code checking process - ie the code will not be run, so the correctness and operation of the code will not be checked

→ If Lint Check gives an error, need to read the error to know what is the error, in which line → Correct the code

3 Verification: Check the operation of the code - based on the design requirements, for this input, the code is expected to give the output This is the process of checking the correctness of the code

→ If Verification has an error, need to read the code to know what is the error, in which line → Correct the code → Lint Check

4 Implementation: The design after Verification is completed and meets the

COMBINATIONAL LOGIC MODELING

Design the following combinational circuit

Inputs: data0, data1 : 3 bit sel : 2 bit Outputs: result : 3 bit

At ~ ( cd ~ if necessary), create directory projects , in it create directory lab0 , in lab0 get the template on GitHub to use, name it ex01 gettemplate ex01

Type ls to see the files and directories in the current directory, or tree if you want to see the directory tree

├── filelist ├── makefile ├── quartus │ ├── de10_pin_assign.qsf │ └── de2_pin_assign.qsf └── test

├── driver.cpp └── tb_top.cpp

A project should be neatly organized as follows:

• Go to ex01 : (cd ex01 )and create directory src mkdir src :

• All design sv files need to be placed in the src directory

• Edit: create file or edit file (if file already exists) type: micro

• Design files need to be declared in the filelist

Create a design file named design_1.sv and place it in src micro src/design_1.sv hoặc cd src rồi micro design_1.sv src/design_1.sv

29 module design_1 ( // input input logic [2:0] data0_i, input logic [2:0] data1_i, input logic [1:0] sel_i,

This article discusses the implementation of basic logical operations in a digital circuit It introduces temporary variables for AND, OR, and XOR results, specifically using 2-bit and 1-bit logic The AND operation is performed using the bitwise AND operator, while the OR operation utilizes the bitwise OR operator The XOR operation is executed with the bitwise XOR operator The results are processed in a combinational block, with a case statement determining the output based on the selection input.

2'b01: result_o and_tnp; = 2'b11: result_o = or_tmp;

2'b11: result_o xor_tmp; = endcase end endmodule : design_1

At ex01, open and add the filename to the filelist Enter micro filelist or if in src then go to ex01 by typing cd filelist

Lint Check Step 1: Run Lint Check to check for errors, type make lint

%Error: src/design_1.sv:23:25: Can't find definition of variable: 'and_tnp' : Suggested alternative: 'and_tmp'

%Error: Exiting due to 1 error(s) make: *** [makefile:50: lint] Error 1

After running Lint, a bug was identified on line 23 due to a typo; the variable and_tnp was incorrectly declared as and_tmp To resolve this issue, correct line 23, repeat Step 1, and run Lint again.

%Warning-WIDTH: src/design_1.sv:17:18: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's OR generates 3 bits

17 | assign or_tmp = data0_i | data1_i;

| ^ For warning description see https://verilator.org/warn/WIDTH?v=4.225 Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message

%Warning-WIDTH: src/design_1.sv:24:23: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS's VARREF 'or_tmp' generates 2 bits

%Warning-CASEOVERLAP: src/design_1.sv:25:7: Case values overlap (example pattern 0x3)

%Warning-CASEINCOMPLETE: src/design_1.sv:21:5: Case values incompletely covered (example pattern 0x2)

%Error: Exiting due to 4 warning(s) make: *** [makefile:50: lint] Error 1

1 The first error, %Warning-WIDTH: src/design_1.sv:17 → error about bit length mismatch, further reading we see that or_tmp is 2 bits but the RHS (Right Hand Side - right) result is 3 bits, this is because the declaration of or_tmp is 2 bits ( [1:0]) → Fix or_tmp declaration line (line 12) to 3 bits: [2:0]

2 The next error on line 24 is similar

3 Error on line 25, %Warning-CASEOVERLAP: src/design_1.sv:25 → error about duplicate value compare case Reviewing the code, there are 2 cases 2'b11

4 Error on line 21, %Warning-CASEINCOMPLETE: src/design_1.sv:21 → er er er error er ror ror ror ror a a a a abou bou bou bou bout t t t t mis mis mis mis missi si si si sing ng ng ng ng ca ca ca case ca se se se se co co co comp co mp mp mp mpar ar ar ar ariso iso iso iso ison n n n Th n Th Th Th This is is is is er er er er erro ro ro ro ror r r r is r is is is ca is ca ca ca caus us us used us ed ed ed by ed by by by th by th th the th e e e e mis mis mis mis missi si si si sing ng ng ng ng 2'b10 ins ins ins ins instan tan tan tance tan ce ce ce ce

So error lines 21 and 25 are related, fix line 24 to 2'b10

Bướ c 3: Sau khi debug, lặp lại Bướ c 1, make lint

No errors, the next step is Verification

Set Up: To verify the above design, it is necessary to create a driver to drive the input and set the condition in the output corresponding to the specific input

Input values, known as test transactions, are generated randomly, making it challenging to determine the exact inputs being used for comparison against pre-computed outputs For large designs with thousands of test samples, manual calculations become impractical for designers Therefore, it is essential to automate output verification using assertions to ensure accurate results.

Bướ c 1: Create file top.sv in directory ex01 , call file design_1.sv

1 Declare input and output as in design_1 , add clock Each clock pulse is a test transaction top.sv

4 module top ( // input input logic clk_i, input logic [2:0] data0_i,

2 Call the design_1 module Note, after the dot is the port name of the design, in the brackets is the signal/data name connected to that port top.sv

16 17 design_1 dut ( data0_i (data0_i ), data1_i (data1_i ), sel_i (sel_i ), result_o(result_o) );

3 Set the condition for the output Use the assert keyword to constrain the output like the code below as required by the design, for example, if sel = 2'b11 , then the result must be equal to xor two data, otherwise the simulation will fail because the design is not satisfactory assertion case Here there is a total of 4 conditions with 4 sel values top.sv

In the given Verilog code, a process named "proc_assertions" is triggered on the positive edge of the clock signal (clk_i) It includes conditional assertions based on the value of the selector input (sel_i) When sel_i is '00', it asserts that the output (result_o) should be '0' For sel_i '01', it checks that result_o equals the bitwise AND of data0_i and data1_i If sel_i is '10', it asserts that result_o is the bitwise OR of the two data inputs Finally, when sel_i is '11', it verifies that result_o is the result of the bitwise XOR operation between data0_i and data1_i This structured approach ensures the correctness of the output based on the specified conditions.

Step 2: Create driver to drive input randomly (easier to detect bugs than preset input and check output, because output output only needs to be constrained to check correctness)

1 Create file driver.cpp in test micro test/driver.cpp : or cd test then micro driver.cpp test/driver.cpp

#define MAX_SIM 20 void set_random(Vtop *dut, vluint64_t sim_unit) { dut->data0_i = rand()%8; dut->data1_i = rand()%8; dut->sel_i = rand()%4;

2 Note 1: the input includes data0_i, data1_i, and sel_i, but needing to be in the form dut->data0_i, … clk_i is always automatically given, so top.sv should always have the logical input clk_i

3 Note 2: this is a C++ file, to generate random, use the function rand() , divide the remainder by 4 because sel_i only has 2 bits, and data has 3 bits, so divide and divide by 8 If you want to keep the value fixed, for example data0_i is 3'b101 , just assign dut->data0_i = 0b101 (C++ assignment)

4 Note 3: MAX_SIM is the number of random samples generated

Step 1: Run Simulating to check for errors, enter make sim

[0] %Error: top.sv:26: Assertion failed in TOP.top.proc_assertions: 'assert' failed

%Error: top.sv:26: Verilog $stop Aborting make: *** [makefile:61: sim] Aborted (core dumped)

The error message indicates an assertion failure on line 26 of top.sv This assertion checks the condition where sel equals 2'b11, revealing that the design in design_1.sv is incorrect when sel is set to this value.

Step 2 : Open waveform to observe, enter make wave Select top → → → → → Select all signals in the lower cell → Select Insert Output is 001 instead of 110

Figure Appendix 2.3 Kết quả mô phỏng bước Verification

It is possible to open the menu and save the selection of this signal: File → Write Save File

Step 3: Check the design_1.sv code again and observe: src/design_1.sv

18 assign xor_tmp = data0_i ~^ data1_i;

Bug on line 18 because the math was supposed to be ^ but was ~^ Edit code

Step 4 : Repeat Step 1 Run sim: make sim

No error Repeat Step 2 , observing the waveform: make wave

Figure Appendix 2.4 Kết quả mô phỏng sau khi hoàn tất bước Verification

Step 1: Create wrapper.sv file

The wrapper file, designated as top.sv, will interface with design_1, utilizing inputs and outputs specified in the DE2_UserManual_1.6 or DE2 Pin Table available at Terasic's website The inputs consist of data0_i, data1_i, and sel_i, which are sourced from designated switches as outlined in Table 4.1 of the manual Specifically, data0_i is assigned to switches SW 2, SW 1, and SW 0, while data1_i corresponds to switches SW 5, SW 4, and SW 3, with sel_i linked to switches SW 7 and SW 6 The input declaration will occur on line 3 and will be assigned across lines 9, 10, and 11.

The output consists of a 3-bit result labeled as result_o, which is referenced in Table 4.3 of the aforementioned file, specifically concerning the red LEDs LEDR 2, LEDR 1, and LEDR 0 Consequently, the output is declared in line 5 and assigned in line 12 of the quartus/wrapper.sv file.

6 module wrapper ( // input input logic [7:0] SW, // output output logic [2:0] LEDR );

data0_i (SW[2:0] ), data1_i (SW[5:3] ), sel_i (SW[7:6] ), result_o(LEDR[2:0]) ); endmodule : wrapper

Step 2 : Create a project in Quartus

2 Choose File → New Project Wizard a To directory quartus in ex01

To ensure proper organization and functionality, the project wrapper should be named exactly as the file it corresponds to, which is wrapper.sv, while the actual project resides in the ex01 directory.

Figure Appendix 2.6 Directory, Name, Top-Level Entity settings c Next to continue

3 Select … to get the source code a Point to directory wrapper.sv which is quartus, select all files → Open →

Add b Point to the directory containing the source code as src, select all files → Open

→ Add c Make sure the Type column is SystemVerilog HDL File d Next to continue

4 For DE2 a Device family selects Cyclone II b Available devices select EP2C35F672C6 c Finish to complete

Figure Appendix 2.7 Family and device settings

Step 3: Import pin assignment of DE2

2 Select … , point to quartus and select de2_pin_assign.qsf ➔ ➔ ➔ ➔ ➔ Open ➔ ➔ ➔ ➔ ➔ OK Step 4: Compilation

Ctrl+L or Processing → Start Compilation

Check the message window has no errors → proceed to upload to KIT

1 Connect the DE2 using the USB cord at the Blaster port

3 Check connected: USB-Blaster X, if No Hardware is displayed, click Hardware Setup and select USB-Blaster X → Close

4 Select Start to start loading Check in the box Progress is 100% (successful), ie successfully loaded

Figure Appendix 2.11 Nạp kit thành công

Design a circuit to count the number of button presses, if pressed and held, it is still counted as a press, and a 7-segment LED display shows the number of presses

The system operates by receiving input from a push button, registering a bit value of 1 when pressed and 0 when not It displays outputs on a 7-segment LED, limited to values of 0 to 9 Additionally, the sequential system includes clock and reset inputs, with a selective active low reset feature Notably, the sequencer processes the push button signal as 1 for just one cycle upon activation.

The circuit features a counter that increases its state by 1 upon receiving an input signal of 1 Additionally, it requires a BCD to 7-segment LED converter to effectively display the counter's status on a 7-segment LED.

Tiêu đề	Introduction to Computing Laboratory Manual Implementation of Basic Logic Gates and Functional ICs on FPGA
Trường học	Ho Chi Minh City University of Technology
Chuyên ngành	Electrical and Electronics Engineering
Thể loại	Laboratory manual
Thành phố	Ho Chi Minh City

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Số trang	80
Dung lượng	5,1 MB