NORME INTERNATIONALE CEI IEC INTERNATIONAL STANDARD 61188 5 6 Première édition First edition 2003 01 Cartes imprimées et cartes imprimées équipées – Conception et utilisation – Partie 5 6 Considératio[.]
Description générale des composants
The components consist of J-lead chip carrier packages with outputs extending beyond the package dimensions The package shapes can be either square or rectangular These terminals generally provide space for the package body concerning encapsulation and interconnection structure, addressing issues related to clearance, control, or the arrangement of thermal expansion differences.
In plastic output chip carriers, the primary encapsulation distinction refers to the point at which a chip is integrated into the housing A pre-molded housing is provided as a body with an open cavity for chip attachment Typically, a portion of the post-molded body features a chip secured to a connection grid, surrounded by a molded insulating plastic body.
Marquage
QFJ product families, whether square or rectangular, are typically labeled according to the manufacturer's specific marking This includes the manufacturer's name or logo and the designation of pin 1 In some cases, the pin indication may be found on the housing instead of the pin 1 marking Additional markings may include the lot code date and/or the manufacturing location.
Format de support de boợtier
The use of strip supports is preferred over bar supports for better handling and high-volume applications Tray supports are not suitable due to the required coplanarity of the pins for placement and soldering.
Prise en compte des processus
Les boợtiers QFJ sont normalement traitộs par opộration de brasage par fusion (voir la CEI
Les dispositifs à pas fins et à sorties nombreuses peuvent nécessiter un traitement spécial hors de la localisation normale de la duite et des opérations en fabrication de fusion.
Remarques introductives
This article outlines the dimensions of the component and the pad area for square QFJ packages It also addresses the basic construction Figures 2 and 3 present a list of tolerances and specified dimensions for the solder joints used to achieve the pad area dimensions.
Description des composants
Les QFJ sont utilisés dans de nombreuses applications pour l’électronique commerciale, industrielle ou militaire.
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The component features quad flat J-lead packages with terminations that extend beyond the package outlines, available in both square and rectangular shapes These terminations serve to separate the package body from the packaging and interconnect structure (P&IS), facilitating clearance, inspection, and accommodating variations in thermal expansion.
In plastic leaded chip carriers, the key distinction in packaging lies in the timing of chip integration Pre-molded packages feature a leaded body with an open cavity designed for chip attachment, while post-molded packages involve attaching the chip to a lead frame, which is then encased in an insulating plastic body.
The QFJ families of square and rectangular parts typically feature the manufacturer's part numbers, name or symbol, along with a pin 1 indicator In some cases, the pin 1 designation may be integrated into the case shape rather than marked explicitly Additional markings may also indicate the date code, manufacturing lot, and location of production.
For optimal handling and high-volume applications, embossed carrier taping is preferred over tube packaging Bulk packaging is unsuitable due to the necessary lead coplanarity for effective placement and soldering.
QFJ packages are normally processed by reflow solder operations (see IEC 60068-2-58).
High lead-count fine pitch parts may require special processing outside the normal pick/place and reflow manufacturing operations.
This clause outlines the dimensions for the land pattern and components of square QFJ (quad flat J-lead) parts, including details on basic construction Tolerances and target solder joint dimensions, essential for determining the land pattern dimensions, are illustrated in Figures 2 and 3.
QFJs are widely used in variety of applications for commercial, industrial or military electronics.
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QFJ chip holders are utilized when a hermetic seal is not required They have limitations, including a restricted temperature range (typically between 0 °C and 70 °C) and nominal environmental protection The primary advantage of QFJ holders is their low cost compared to ceramic enclosures.
La coplanéité à extrémité de sortie élevée dans les porte-puce à sorties pour montage en surface est un facteur important pour la fiabilité des fixations brasées à la carte imprimée.
La planộitộ peut ờtre mesurộe à partir des trois sorties les plus faibles d’un boợtier à sorties.
La coplanéité de 0,1 mm au maximum est recommandée avec toutefois, une préférence pour
Le porte-puce en plastique prộ-moulộ a ộtộ conỗu pour ờtre connectộ au substrat P et l
The assembly and interconnection structure utilizes a socket, with spring pressure on both sides of the housing designed to constrain movement and accommodate substrate warping of up to 0.5% A soldered fixation to substrate P is also feasible Additionally, the design aims to incorporate silicone encapsulation techniques for chip protection and coating.
The plastic pre-molded and post-molded chip carriers consist of a composite metal dielectric assembly that includes a conductive connection grid and a molded insulating body In both types of plastic chip carriers, all necessary operations for encapsulation are performed by the packaging manufacturer to eliminate damage and metallization by the user.
All devices must display a model number and the location of the ôBroche 1ằ The position of the ôBroche 1ằ can either be molded into the plastic body or marked with ink.
4.2.4 Format de support de boợtier
Le support des boợtiers pour les boợtiers plats peut ờtre en barrettes, mais dans la plupart des cas les boợtiers plats sont fournis sur support en bande.
4.2.5 Prise en compte des processus
Devices must withstand ten cycles using a standardized reflow system operating at 235 °C, with each cycle involving exposure to this temperature for 60 seconds Additionally, the devices should endure at least 10 seconds of immersion in molten solder at 260 °C All components must comply with the IEC 61760-1 standards.
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QFJs, or quad flat J-lead packages, are utilized in applications that do not necessitate a hermetic seal, operating effectively within a limited temperature range of 0 °C to 70 °C They offer nominal environmental protection and are favored for their cost-effectiveness compared to ceramic packages.
High lead-end coplanarity in surface-mounted lead chip carriers is crucial for ensuring reliable solder attachment to printed circuit boards It is measured from the lowest three leads of a leaded package, with a recommended maximum coplanarity of 0.1 mm and a preferred value of 0.05 mm.
The pre-molded plastic chip carrier is engineered for connection to the packaging and interconnection (P&I) substrate via a socket It features spring pressure on both sides to limit movement while accommodating substrate warpage.
0,5 % Solder attach to the P&l substrate is also possible The design is also intended to make use of silicone encapsulate technology for chip coverage and protection.
The pre- and post-molded plastic leaded chip carrier is composed of a composite metal/dielectric assembly that includes a conductor lead frame and a molded insulating body.
In both types of plastic chip carriers, all necessary plating operations are performed by the package manufacturer to eliminate tinning or plating by the user.
All parts shall be marked with a part number and “Pin 1” location The “Pin 1” location may be molded into the plastic body or marked with ink.
The carrier package format for flat packs may be provided in tubes but, in most instances, flat packs are delivered in embossed taping.
Parts must endure ten cycles in a reflow system at 235 °C, with each cycle involving a 60-second exposure Additionally, they should withstand at least 10 seconds of immersion in molten solder at 260 °C Compliance with IEC 61760-1 standards is required for all components.
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Les Figures 2 et 4 fournissent les dimensions des composants QFJ (carré).
Identificateur de composant Min Max Min Max Min Max Min Max Min Max Réfé- rence Max De base
Figure 2 – Dimensions de boợtier QFJ (carrộ)
4.4 Conception d’excroissance de pastille de joint brasé
Figure 3 illustrates the dimensions and shape of the solder joint after the soldering process The minimum, median, and maximum dimensions of each end, heel, and side joint are determined by considering the reliability of the solder joint, quality, and productivity during the assembly of devices The design of the reporting areas requires consideration of three precision factors: the dimensional accuracy of the devices (C), the accuracy of device mounting on printed circuit boards (P), and the dimensional accuracy of the chips on the printed circuit boards (F), in addition to the dimensions of the joints The necessary formula to obtain the resulting tolerance from these factors is as follows: a) Design effect for soldering without self-alignment (level 1).
Dans le processus de brasure à la vague, il n’y a pas d’effet d’auto-alignement De ce fait la formule ne peut pas être simplifiée mais reste identique comme indiqué ci-après:
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Figures 2 to 4 provide the component dimensions for QFJ (square) components.
Component identifier Min Max Min Max Min Max Min Max Min Max Ref Max Basic
Conception d’excroissance de pastille de joint brasé
Figure 3 illustrates the dimensions and shape of the solder joint after the soldering process The minimum, median, and maximum dimensions of each end, heel, and lateral joint are determined by considering the reliability of the solder joint, quality, and productivity during the assembly of devices The design of the reporting areas requires consideration of three precision factors: the dimensional accuracy of the devices (C), the accuracy of device mounting on printed circuit boards (P), and the dimensional accuracy of the chips on the printed circuit boards (F), in addition to the dimensions of the joints The necessary formula to obtain the resulting tolerance from these factors is as follows: a) Design effect for soldering without self-alignment (level 1).
Dans le processus de brasure à la vague, il n’y a pas d’effet d’auto-alignement De ce fait la formule ne peut pas être simplifiée mais reste identique comme indiqué ci-après:
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Figures 2 to 4 provide the component dimensions for QFJ (square) components.
Component identifier Min Max Min Max Min Max Min Max Min Max Ref Max Basic
Figure 3 illustrates the shape and dimensions of the solder fillet post-soldering The dimensions of the toe, heel, and side fillet are assessed based on solder joint reliability, as well as the quality and productivity of the parts mounting process When designing land patterns, it is essential to consider three accuracy factors: part dimension accuracy (C) and part mount accuracy.
The accuracy of PW Bs (P) and land shape on PW Bs (F), along with fillet dimensions, significantly influences tolerance The following formulae are used to determine the tolerance when soldering without the self-alignment effect (level 1).
In the flow soldering process, there is no self-alignment effect Thus, the formulae cannot be simplified but remain the same as follows:
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X max = W min + 2 J S max + T S T S = F L1 2 +P L1 2 +C W 2 b) Effet sur la conception pour une brasure sans auto-alignement (niveau 2):
X max = W min + 2 J S mdn + T S T S = F L2 2 +P L2 2 +C W 2 c) Effet sur la conception pour une brasure avec auto-alignement (niveau 3):
In the fusion soldering process, an auto-alignment effect occurs because adhesives are not used to hold the components During surface mounting with fusion soldering, the movement of device placement and the dimensional accuracy of chips on printed circuit boards can be corrected through this auto-alignment effect, effectively rendering factors P and F negligible Consequently, the formulas can be simplified accordingly.
T H = C L, Z max = L min + 2 J H min + C L = L max + 2 J H min
T S = C W , X max = W min + 2 J S min + C W = W max + 2 J S min
Toutes tolérances autres que celles ci-dessus peuvent être utilisées selon la force de brasure requise et de procédé de fabrication utilisé.
Figure 3 presents the minimums for brazed joints in butt, heel, and side connections It discusses statistical tolerances, assuming an equal distribution of tolerances for the component, manufacturing, and installation accuracy.
Les tolộrances individuelles de fabrication (ôFằ) et la prộcision de l’ộquipement de mise en place du composant (ôPằ) sont censộes correspondre aux donnộes du tableau associộ à la
Figure 3 Ces nombres peuvent être modifiés sur la base de la capacité de l’équipement de l’utilisateur ou les critères de fabrication Les gammes de tolérances de composant (C L , C S , et
The dimensions in Figure 2 are derived by subtracting the minimum dimensions from the maximum dimensions Users have the flexibility to adjust these values based on their experience with suppliers Altering the tolerances may lead to alternating patterns of printed pads, which differ in size from the standard printed pad dimensions recorded in the IEC.
Les dimensions pour les raccords de soudure minimaux au niveau du bout, du talon ou du côté
The values of (J T, J H, J S) were established based on empirical knowledge in the industrial field and reliability testing The strength of brazed joints is significantly influenced by the volume of filler metal used An observable solder joint is essential to demonstrate proper wetting Consequently, the values in the table typically indicate a positive solder joint However, users have the flexibility to adjust the minimum value based on the process capability.
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X max = W min + 2 J S max + T S T S = F L1 2 +P L1 2 +C W 2 b) Design consideration when soldered without self-alignment effect (level 2):
X max = W min + 2 J S mdn + T S T S = F L2 2 +P L2 2 +C W 2 c) Design consideration when soldered with self-alignment effect (level 3):
In the reflow soldering process, components experience a self-alignment effect due to the absence of adhesives This self-alignment allows for the correction of part displacement and land shape accuracy on printed circuit boards (PCBs) during soldering, effectively rendering factors P and F negligible Consequently, the associated formulae can be simplified.
T H = C L, Z max = L min + 2 J H min + C L = L max + 2 J H min
T S = C W, X max = W min + 2 J S min + C W = W max + 2 J S min
Any tolerance other than the above may be used depending on the soldering strength required, the capability of the production process used.
Figure 3 shows the solder joint minimum for toe, heel, and side fillets, as discussed.
The tolerances are addressed statistically and assume even distribution for component, fabrication, and placement accuracy.
Individual tolerances for fabrication (F) and component placement equipment accuracy (P) are specified in the table associated with Figure 3, but can be adjusted according to user equipment capabilities or fabrication standards The component tolerance ranges (C L, C S, and C w) are calculated by subtracting the minimum dimensions from the maximum dimensions shown in Figure 2 Users have the option to modify these values based on their experiences with suppliers, which may lead to alternative land patterns that differ from the IEC registered land pattern dimensions.
Minimum dimensions for solder fillets at the toe, heel, or side (J T, J H, J S) are established based on industry standards and reliability testing The strength of a solder joint is significantly influenced by the volume of solder used A visible solder fillet is essential to demonstrate adequate wetting, ensuring that the values in the table typically result in a reliable solder fillet.
Nevertheless, the user may increase or decrease the minimum value based on process capability.
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Raccord de talon Raccord du bout Raccord latéral
J Hmin Raccord de talon minimal
T H Tolérances combinées au raccord de talon
J Tmin Raccord du bout minimal
T T Tolérances combinées au raccord du bout
T S Tolérances combinées au raccord latéral
Joint brasé Notification de tolérance
L -1 L -2 L -3 L -1 L -2 L -3 C L Max Moyen Min C S Max Moyen Min C W Max Moyen Min
Figure 3 – Conception d’excroissance de pastille de joint brasé de composant
QFJ carré ayant différents niveaux
(voir Tableau 5 de la CEI 61188-5-1)
Dimensions de la zone de report
La Figure 4 donne des dimensions de la zone de report pour des composants à QFJ.
La surface est calculée conformément aux formules ci-après et arrondies (le facteur d’arrondi est proche de 0,05 pour les valeurs minimales et de 0,5 pour les valeurs maximales).
CY 1 = {la plus grande des dimensions [L 1 min + F 2 +P 2 +C L1 2 ] ou [Z 1 ]}
CY 2 = {la plus grande des dimensions [L 2 min + F 2 +P 2 +C L2 2 ] ou [Z 2 ]}
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Heel fillet Toe fillet Side fillet
T H Combined tolerances at heel fillet
T T Combined tolerances at toe fillet
T S Combined tolerances at side fillet
L -1 L -2 L -3 L -1 L -2 L -3 C L Max Mdn Min C S Max Mdn Min C W Max Mdn Min
Figure 3 – Solder joint fillet design of QFJ square component with different levels
Figure 4 shows the land pattern dimensions for QFJ components.
The courtyard is calculated using the following formulae and rounded up (the round-up factor is to the nearest 0,05 for minimum values and to the nearest 0,5 for maximum values).
CY 1 = {whichever is larger [L 1 min + F 2 +P 2 +C L1 2 ] or [Z 1 ]}
CY 2 = {whichever is larger [L 2 min + F 2 +P 2 +C L2 2 ] or [Z 2 ]}
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Surface pour l’emplacement de la grille IEC 3273/02
Identificateur du composant Z G X Y E C D CY 1 CY 2
Identificateur du composant Z G X Y E C D CY 1 CY 2
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Identificateur du composant Z G X Y E C D CY 1 CY 2
Figure 4 – Dimensions de la zone de report pour QFJ (carré)
Remarques introductives
This article outlines the dimensions of the component and the pad area for rectangular QFJ packages (quad flat plastic packages) It also addresses the basic construction Figures 6 and 7 provide a list of tolerances and the specified dimensions for solder joints used to achieve the pad area dimensions.
Description des composants
Les QFJ sont utilisés dans de nombreuses applications pour l’électronique commerciale, industrielle ou militaire.
QFJ chip holders are utilized when a hermetic seal is not required They have limitations, including a restricted temperature range (typically between 0 °C and 70 °C) and nominal environmental protection The primary advantage of QFJ holders is their low cost compared to ceramic enclosures.
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Figure 4 – QFJ (square) land pattern dimensions
This clause outlines the dimensions for the land pattern and components of square QFJ (plastic quad flat pack) parts, including details on basic construction Additionally, Figures 6 and 7 present the tolerances and target solder joint dimensions that inform the land pattern specifications.
QFJs are widely used in variety of applications for commercial, industrial or military electronics.
QFJs are utilized in applications that do not necessitate a hermetic seal, operating effectively within a limited temperature range of 0 °C to 70 °C and providing nominal environmental protection Additionally, QFJs offer a cost-effective alternative to ceramic packages.
LICENSED TO MECON Limited - RANCHI/BANGALORE FOR INTERNAL USE AT THIS LOCATION ONLY, SUPPLIED BY BOOK SUPPLY BUREAU.
High output-end coplanarity in surface-mount chip carriers is crucial for the reliability of soldered connections on printed circuit boards This coplanarity can be assessed by measuring the three lowest outputs of a leaded package.
La coplanéité de 0,1 mm au maximum est recommandée avec une préférence pour 0,05 mm.
The plastic pre-molded chip holder is designed to connect to substrate P through a socket The spring pressure on both sides of the housing is intended to restrict movement and accommodate substrate warping.
0,5 % Une fixation brasée au substrat P et l est également possible La conception est également destinée à utiliser la technique de l’encapsulant en silicone pour la protection et le revêtement de puce.
The plastic pre-molded and post-molded chip carriers consist of a composite dielectric/metal assembly that includes a conductive connection grid and a molded insulating body In both types of plastic chip carriers, all necessary operations for metallization are performed by the packaging manufacturer to eliminate damage and metallization by the user.
All devices must display a model number and the location of the "Pin 1." The location of "Pin 1" can either be molded into the plastic body or marked using ink.
5.2.4 Format de support de boợtier
Le support des boợtiers pour les boợtiers plats peut ờtre en barrettes, mais dans la plupart des cas les boợtiers plats sont fournis sur support en bande.
5.2.5 Prise en compte des processus
Devices must withstand ten cycles using a standardized reflow system operating at 235 °C, with each cycle involving exposure to this temperature for 60 seconds Additionally, they should endure at least 10 seconds of immersion in molten solder at 260 °C Components must comply with the IEC 61760-1 standards.
Dimensions des composants
La Figure 6 fournit les dimensions des composants QFJ (rectangulaire).
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High lead-end coplanarity in surface-mounted lead chip carriers is crucial for ensuring reliable solder attachment to printed circuit boards It is measured from the lowest three leads of a leaded package, with a recommended maximum coplanarity of 0.1 mm.
The pre-molded plastic chip carrier is engineered for connection to the P&l substrate via a socket, featuring spring pressure on both sides to limit movement and accommodate substrate warpage up to 0.5% Additionally, solder attachment to the P&l substrate is feasible, and the design incorporates silicone encapsulate technology for enhanced chip coverage and protection.
The pre- and post-molded plastic leaded chip carrier is composed of a composite metal/dielectric assembly that includes a conductor lead frame and a molded insulating body.
In both types of plastic chip carriers, all necessary plating operations are performed by the package manufacturer to eliminate tinning or plating by the user.
All parts shall be marked with a part number and “Pin 1” location The “Pin 1” location may be molded into the plastic body or marked with ink.
The carrier package format for flat packs may be tube format but in most instances flat packs are delivered in embossed taping.
Parts must endure ten cycles in a standard reflow system at 235 °C, with each cycle involving a 60-second exposure Additionally, they should withstand at least 10 seconds of immersion in molten solder at 260 °C Compliance with IEC 61760-1 standards is required for all components.
Figure 6 provide the component dimensions for QFJ (rectangular) components.
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Identifi- cateur du compo- sant
Comp- tage des broches Côté court
Comp- tage des broches Côté long
Min Max Min Max Min Max Min Max Max Max Réf Réf Max De base
Figure 6 – Dimensions de boợtier QFJ (rectangulaire)
Conception d’excroissance de pastille de joint brasé
La Figure 7 donne les dimensions et la forme du raccord de brasure après l’opération de brasure.
The minimum, median, and maximum dimensions of each end, heel, and lateral connection are determined by considering the reliability of the solder joint, as well as the quality and productivity during the assembly of devices The design of the connection areas must take into account three precision factors: the dimensional accuracy of the devices (C), the accuracy of device mounting on printed circuit boards (P), and the accuracy of chip dimensions on printed circuit boards (F), in addition to the dimensions of the connections The necessary formula to obtain the resulting tolerance from these factors is as follows: a) Design effect for soldering without self-alignment effect (level 1).
Dans le processus de brasure à la vague, il n’y a pas d’effet d’auto-alignement De ce fait la formule ne peut pas être simplifiée mais reste identique comme suit:
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Min Max Min Max Min Max Min Max Max Max Ref Ref Max Basic
Figure 7 illustrates the shape and dimensions of the solder fillet post-soldering The dimensions of the toe, heel, and side fillet are evaluated based on solder joint reliability, as well as the quality and productivity of the parts mounting process When designing land patterns, it is essential to consider three accuracy factors: part dimension accuracy (C), part mount accuracy, and overall assembly precision.
The accuracy of PW Bs (P) and the shape of PW Bs (F) are influenced by fillet dimensions The formulas for determining the tolerance based on these factors are outlined, particularly focusing on design considerations when soldering without the self-alignment effect (level 1).
In the flow soldering process, there is no self-alignment effect Thus, the formulae cannot be simplified but remain the same as follows:
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X max = W min + 2 J S max + T S T S = F L1 2 +P L1 2 +C W 2 b) Effet sur la conception pour une brasure sans effet d’auto-alignement (niveau 2):
X max = W min + 2 J S mdn + T S T S = F L2 2 +P L2 2 +C W 2 c) Effet sur la conception pour une brasure avec effet d’auto-alignement (niveau 3):
In the fusion soldering process, an auto-alignment effect occurs because adhesives are not used to hold the components During surface mount assembly through fusion soldering, the movement of device placement and the dimensional accuracy of chips on printed circuit boards can be corrected by this auto-alignment effect, allowing factors P and F to be considered negligible Consequently, the formulas can be simplified accordingly.
T H = C L , Z max = L min + 2 J H min + C L = L max + 2 J H min
T S = C W , X max = W min + 2 J S min + C W = W max + 2 J S min
Toute tolérance autre que celles ci-dessus peuvent être utilisées selon la force de brasure requise et de procédé de fabrication utilisé.
Figure 7 presents the minimums for brazed joints in butt, heel, and side connections It discusses statistical tolerances, assuming an equal distribution of tolerances for the component, manufacturing, and installation accuracy.
Les tolộrances individuelles de fabrication (ôFằ) et la prộcision de l’ộquipement de mise en place du composant (ôPằ) sont censộes correspondre aux donnộes du tableau associộ à la
Figure 7 Ces nombres peuvent être modifiés sur la base de la capacité de l’équipement de l’utilisateur ou les critères de fabrication Les gammes de tolérances de composant (C L , C S , et
C W) are derived by subtracting the minimum dimensions from the maximum dimensions shown in Figure 6 Users can also adjust these values based on their experience with suppliers Altering the tolerances may lead to alternate chip printing arrays, which have dimensions different from those recorded in the IEC chip printing arrays.
Les dimensions pour les raccords de soudure minimaux au niveau du bout, du talon ou du côté
The parameters (J T, J H, J S) were established based on empirical knowledge in the industrial sector and reliability testing The strength of brazed joints is significantly influenced by the volume of filler metal used An observable solder joint is essential to demonstrate proper wetting Consequently, the values in the table related to Figure 7 typically indicate a positive solder joint However, the user has the flexibility to adjust the minimum value based on the process capability.
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X max = W min + 2 J S max + T S T S = F L1 2 +P L1 2 +C W 2 b) Design consideration when soldered without self-alignment effect (level 2):
X max = W min + 2 J S mdn + T S T S = F L2 2 +P L2 2 +C W 2 c) Design consideration when soldered with self-alignment effect (level 3):
In the reflow soldering process, the self-alignment effect occurs due to the absence of adhesives holding components in place This effect allows for the correction of component displacement and ensures accurate land shape on printed wiring boards (PWBs) during soldering, effectively simplifying the relevant formulae by considering factors P and F as zero.
T H = C L , Z max = L min + 2 J H min + C L = L max + 2 J H min
T S = C W , X max = W min + 2 J S min + C W = W max + 2 J S min
Any tolerance other than the above may be used depending on the soldering strength required, the capability of the production process used.
Figure 7 shows the solder joint minimum for toe, heel and side fillets, as discussed The tolerances are addressed statistically, and assume even distribution for component, fabrication and placement accuracy.
Individual tolerances for fabrication (F) and component placement equipment accuracy (P) are specified in the table associated with Figure 7, but can be adjusted according to user equipment capabilities or fabrication standards The component tolerance ranges (C_L, C_S, and C_w) are calculated by subtracting the minimum dimensions from the maximum dimensions shown in Figure 6 Users have the option to modify these values based on their experiences with suppliers, which may lead to alternative land patterns that differ from the IEC registered land pattern dimensions.
The minimum dimensions for solder fillets at the toe, heel, or side (J T, J H, J S) are established from industry empirical knowledge and reliability testing The strength of a solder joint is significantly influenced by the volume of solder used, and a visible solder fillet indicates proper wetting The values presented in the table associated with Figure 7 typically ensure a positive solder fillet; however, users have the flexibility to adjust these minimum values according to their process capabilities.
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Raccord de talon Raccord du bout Raccord latéral
J Hmin Raccord de talon minimal
T H Tolérances combinées au raccord de talon
J Tmin Raccord du bout minimal
T T Tolérances combinées au raccord du bout
T S Tolérances combinées au raccord latéral
Joint brasé Notification de tolérance
L -1 L -2 L -3 L -1 L -2 L -3 C L Max Moyen Min C S Max Moyen Min C W Max Moyen Min
Figure 7 – Conception d’excroissance de pastille de joint brasé de composant
QFJ rectangulaire ayant différents niveaux
(voir Tableau 5 de la CEI 61188-5-1)