Iec 61188 5 5 2007

IEC 61188-5-5Edition 1.0 2007-10 INTERNATIONAL STANDARD Printed boards and printed board assemblies – Design and use – Part 5-5: Attachment land/joint considerations – Components with

General component description

The four-sided gull wing family features gull-wing leads on all four sides of square or rectangular packages, encompassing both molded plastic and ceramic case styles This family is commonly referred to by the acronyms PQFP (plastic quad flat pack) and CQFP (ceramic quad flat pack).

There are several lead pitches within the family form 1,0 mm to 0,30 mm High lead-court packages are available in this family that accommodate complex, high lead-count chips.

Marking

The PQFP and CQFP component families typically display the manufacturer's part numbers, name or symbol, and a pin 1 indicator In some cases, the pin 1 feature may be integrated into the case shape rather than marked explicitly Additional markings can include date codes, manufacturing lots, and the location of production.

LICENSED TO MECON Limited - RANCHI/BANGALORE,FOR INTERNAL USE AT THIS LOCATION ONLY, SUPPLIED BY BOOK SUPPLY BUREAU.

Carrier packaging format

For optimal handling and high-volume applications, packaging trays are preferred over tube formats for carrier packaging Bulk packaging is unsuitable due to the necessity of lead co-planarity for effective placement and soldering.

Process considerations

PQFP and CQFP packages are normally processed by reflow solder operations

High lead-count fine pitch parts may require special processing outside the normal pick/place and reflow manufacturing operations

Field of application

This section outlines the dimensions for the land pattern and components of square PQFP (plastic quad flat pack) devices, including their basic construction Additionally, it concludes with a summary of the tolerances and target solder joint dimensions that inform the land pattern specifications.

Component descriptions

PQFPs are widely used in a variety of applications for commercial, industrial or military electronics

The quad flat pack has been developed for applications requiring low height and high density

The PQFP, along with the LSOP components, are frequently used in memory card applications (see Figure 1)

Leads shall be solder-coated with a tin/lead alloy The solder should contain between 58 % to

Solder, composed of 68% tin, can be applied to leads through hot dipping or by plating from a solution It is essential to perform a post-plating reflow operation on plated solder terminations to ensure proper fusion of the solder.

The tin/lead finish should be at least 0,007 5 mm thick

All parts shall be marked with a part number and an index area The index area shall identify the location of pin 1

The carrier package format for flat packs may be tubular in shape but, in most instances, flat packs are delivered in a carrier tray

PQFPs are usually processed using standard reflow solder processes Parts should be capable of withstanding ten cycles through a standard reflow system operating at 235 °C

Each cycle shall consist of 60 s exposure at 235 ° C

Component dimensions

Land pattern dimensional data may need to be adjusted if the component dimensional data does not match JEDEC and/or JEITA sheets

Figure 2 provides the component dimensions for PQFP (square) components

L2 L1 Lp EIAJ codes JEDEC code

Min Max Min Max Min Max

Min Nom Max Min Max

Figure 2 – PQFP (square) component dimensions

Min Nom Max Min Max B A P H Remarks

Min Nom Max Max Max

Solder joint fillet design

Figure 3 illustrates the shape and dimensions of the solder fillet post-soldering The minimum, median, and maximum dimensions for the toe, heel, and side fillet are established with a focus on ensuring solder joint reliability, as well as enhancing quality and productivity during the component mounting process.

In designing land patterns, three accuracy factors need to be taken into consideration:

– parts mount accuracy on PWBs (P);

The accuracy of land shape in printed wiring boards (PWBs) is influenced by fillet dimensions The tolerance calculations for these factors are primarily based on design considerations, particularly when soldering occurs without the self-alignment effect (level 1).

In the flow soldering process there is no self-alignment effect Thus, the formulae cannot be simplified but remain the same, as follows:

L2+ + Gmin = Smax (rms) – 2J H max – T H T H = F P CS2

L2+ + b) Design consideration when soldered without self-alignment effect (level 2)

L 2+ + Gmin = Smax(rms) – 2J H mdn – T H T H = F P CS2

L 2+ + c) Design consideration when soldered with self-alignment effect (level 3)

L 2+ + Gmin = Smax(rms) – 2J H min – T H T H = F P CS2

The reflow soldering process exhibits a self-alignment effect, allowing for the cancellation of parts mount displacement during surface mount soldering, effectively making factor P equal to 0 Additionally, the land shape accuracy tolerance of printed wiring boards (PWBs) is approximately ±30 µm, which is significantly smaller than the dimensional accuracy of the components, leading to factor F also being considered as 0.

Thus, the formulae can be simplified as follows:

T T = C L, Zmax = Lmin + 2J T min + C L = Lmax + 2J T min

T S = C W, Xmax = Wmin + 2J S min + C W = Wmax + 2J S min

To ensure that the land is not obscured by the QFP, it is essential that the value Gmin is greater than or equal to A and B Additionally, the stand-off of the component mold should be nearly zero, and the land pattern design must be optimized to prevent lead floating due to solder beneath the component.

Any tolerance other than the above may be used depending on the soldering strength required, the capability of the production process used, and so on

L-2/L-3 C L Max Mdn Min C S Max Mdn Min C W Max Mdn Min

NOTE PQFP with lead pitch of 0,5 mm or less are not suitable for flow soldering

Figure 3 – Solder joint fillet design

Land pattern dimensions

Figure 4 shows land pattern dimensions for PQFP (square) for reflow and flow soldering

These values are calculated based on the formula for the solder joint fillet design of 4.5

The courtyard dimensions are determined using a specific formula, with results rounded to the nearest 0.05 mm for minimum values and to the nearest 0.5 mm for maximum values.

CY 1 ={whichever larger [L1min + F 2 + P 2 + C L 2 ] or [Z1]} + (courtyard excess × 2)

CY 2 ={whichever larger [L2min + F 2 + P 2 + C L 2 ] or [Z2]} + (courtyard excess × 2)

Pattern identifier EIAJ code JEDEC code Z G X Y P CY 1 CY 2

* When the X dimension is used, it is necessary to confirm whether the space between adjacent land patterns is proper

Figure 4 – PQFP (square) land pattern dimensions

This clause provides the component and land pattern dimensions for rectangular PQFP

(plastic quad flat pack) components Basic construction of the PQFP device is also covered

At the end of this clause is a listing of the tolerances and target solder joint dimensions used to arrive at the land pattern dimensions.

PQFPs are widely used in a variety of applications for commercial, industrial or military electronics

The PQFPs, along with the LSOP components, are frequently used in memory card applications (see Figure 5)

Solder, composed of 68% tin, can be applied to leads through hot dipping or solution plating It is essential to perform a post-plating reflow operation on plated solder terminations to ensure proper fusion of the solder.

For lead removal applications, various lead-free or lead-free compatible finishes are available It is essential to conduct solderability testing according to IEC 60068-2-54 to assess the attachment capability of the relevant component type.

The carrier package format for flat packs may be tubular in shape, but, in most instances, flat packs are delivered in a carrier tray

PQFPs are usually processed using standard solder reflow processes Parts should be capable of withstanding ten cycles through a standard reflow system operating at 235 °C

Each cycle shall consist of 60 s exposure at 235 °C

Figure 6 provides the component dimensions for PQFP (rectangular) components

Min Nom Max Min Max Min Max

Figure 6 – PQFP (rectangular) component dimensions

Figure 7 illustrates the shape and dimensions of the solder fillet post-soldering The minimum, median, and maximum dimensions for the toe, heel, and side fillets are established based on the reliability of the solder joint, as well as the quality and productivity during the assembly of components.

– land shape accuracy of PWBs (F), in addition to fillet dimensions The formulae to obtain the tolerance resulting from these factors are basically as follows:

LICENSED TO MECON Limited - RANCHI/BANGALORE,FOR INTERNAL USE AT THIS LOCATION ONLY, SUPPLIED BY BOOK SUPPLY BUREAU. a) Design consideration when soldered without self-alignment effect (level 1)

In the flow soldering process, there is no self-alignment effect Thus, the formulae cannot be simplified but remain the same as follows:

The reflow soldering process exhibits a self-alignment effect, allowing for the cancellation of part displacement during the surface mount process, effectively making factor P equal to 0 Additionally, the land shape accuracy tolerance of printed wiring boards (PWBs) is approximately ±30 µm, which is significantly smaller than the dimensional accuracy of the components, leading to factor F also being considered as 0.

T T = C L, Zmax = Lmin + 2J T min + C L = Lmax + 2J T min

To ensure that the land is not obscured by the QFP, it is essential that the value Gmin is greater than or equal to A and B Additionally, the stand-off of the component mold should be nearly zero Proper land pattern design is crucial to prevent lead floating due to solder beneath the component.

Toe fillet Heel fillet Side fillets

NOTE QFP with lead pith of 0,5 mm or less are not suitable for flow soldering

Figure 8 shows land pattern dimensions for PQFP (rectangular) for reflow and flow soldering

These values are calculated based on the formula for the solder joint fillet design given in 6.4

The courtyard is determined using a specific formula, with results rounded to the nearest 0.05 mm for minimum values and to the nearest 0.5 mm for maximum values.

CY 1 ={whichever is larger [L1min + F 2 + P 2 + C L 2 ] or [Z1]} + (courtyard excess × 2)

Pattern identifier EIAJ code JEDEC code Z 1 Z 2 G 1 G 2 X* Y P CY 1 CY 2

Figure 8 – PQFP (rectangular) land pattern dimensions

This section outlines the dimensions for the land pattern and components of square PLQFP (low profile plastic quad flat pack) devices It also details the fundamental construction of the PLQP D device Additionally, it concludes with a summary of the tolerances and target solder joint dimensions that inform the land pattern specifications.

PLQFPs are widely used in a variety of applications for commercial, industrial or military electronics

The PLQFPs, along with the LSOP components, are frequently used in memory card applications (see Figure 9)

Solder, composed of 68% tin, can be applied to leads through hot dipping or plating from a solution It is essential to perform a post-plating reflow operation on plated solder terminations to ensure proper fusion of the solder.

The carrier package format for flat packs may be in tube format but, in most instances, flat packs are delivered in a carrier tray

P-QFPs are typically subjected to standard solder reflow processes, requiring components to endure ten cycles in a reflow system set at 235 °C Each cycle involves a 60-second exposure to this temperature.

Figure 10 provides the component dimensions for PLQFP (square) components

Min Nom Max Max Max

Figure 10 – PLQFP (square) component dimensions

Min Nom Max Max Max B A P H Remarks

Figure 11 illustrates the shape and dimensions of the solder fillet post-soldering The minimum, median, and maximum dimensions for the toe, heel, and side fillet are established based on factors such as solder joint reliability, quality, and productivity during the assembly of components.

– land shape accuracy of PWBs (F),

This document is licensed to MECON Limited for internal use in Ranchi and Bangalore, as supplied by the Book Supply Bureau It includes essential fillet dimensions and outlines the formulas for calculating tolerances based on various factors, particularly focusing on design considerations when soldering without the self-alignment effect (level 1).

In the flow soldering process there is no self-alignment effect Thus, the formulae cannot be simplified but remain the same as follows:

The reflow soldering process exhibits a self-alignment effect, allowing for the cancellation of parts mount displacement during surface mount soldering, effectively making factor P equal to 0 Additionally, the land shape accuracy tolerance of printed wiring boards (PWBs) is approximately ±30 µm, which is significantly smaller than the dimensional accuracy of the components, leading to factor F also being considered as 0.

T T = C L, Zmax = Lmin + 2J T min+ C L = Lmax + 2Jmin

Toe fillet Heel fillet Side fillet

NOTE QFP with lead pitch of 0,5 mm or less is not suitable for flow soldering

Figure 12 shows land pattern dimensions for PLQFP (square) for reflow and flow soldering

These values are calculated based on the formula for the solder joint fillet design given in 7.4

Pattern identifier EIAJ code JEDEC code Z G X* Y P CY 1 CY 2

Pattern identifier EIAJ code JEDEC code Z G X* Y P CY1 CY2

Figure 12 – PLQFP (square) land pattern dimensions

This clause provides the component and land pattern dimensions for rectangular PLQFP

The article discusses the components of plastic low profile quad flat pack (PLQFP) devices, detailing their basic construction Additionally, it provides a list of tolerances and target solder joint dimensions that are essential for determining the appropriate land pattern dimensions.

PLQFPs are widely used in a variety of applications for commercial, industrial or military electronics

The PLQFPs, along with the LSOP components, are frequently used in memory card applications (see Figure 13)

Solder containing 68% tin can be applied to leads through hot dipping or solution plating It is essential to perform a post-plating reflow operation on plated solder terminations to ensure proper fusion of the solder.

The carrier package format for flat packs may be in tube format, but, in most instances, flat packs are delivered in a carrier tray

PLQFPs are usually processed using standard solder reflow processes Parts should be capable of withstanding ten cycles through a standard reflow system operating at 235 °C

Each cycle shall consist of 60 s of exposure at 235 °C

Land pattern dimensional data may need to be adjusted if the component dimensional data does not match JEDEC and/or JEITA sheets, see Figure 14

Min Nom Max Min Max Min Max B A P H Remarks

Figure 14 – PLQFP (rectangular) component dimensions

Figure 15 illustrates the shape and dimensions of the solder fillet post-soldering The minimum, median, and maximum dimensions for the toe, heel, and side fillet are established, focusing on solder joint reliability, quality, and productivity during the component mounting process.

The accuracy of land shape in printed wiring boards (PWBs) is influenced by fillet dimensions To determine the tolerance resulting from these factors, specific formulae are applied, particularly in design considerations when soldering without the self-alignment effect (level 1).

L2+ + Gmin = Smax (rms) – 2J H max– -T H T H = F P CS2

The reflow soldering process exhibits a self-alignment effect, allowing for the cancellation of part displacement during the surface mount process, effectively making factor P equal to 0 Additionally, the land shape accuracy tolerance of printed wiring boards (PWBs) is approximately ±30 µm, which is significantly smaller than the dimensional accuracy of the components, leading to factor F also being considered as 0.

T T = C L, Zmax = L min + 2 J T min+ C L = Lmax + 2J T min

T S = C W, Xmax = W min + 2J S min + C W = Wmax + 2J S min

Figure 16 shows land pattern dimensions for PLQFP (Rectangular) low soldering These values are calculated based on the formula for the solder joint fillet design given in 8.4

The courtyard dimensions are determined using a specific formula, with results rounded to the nearest 0.05 mm for minimum values and to the nearest 0.5 mm for maximum values.

CY 1 ={whichever is larger [L 1 min + F 2 + P 2 + C L 2 ] or [Z1]} + (courtyard excess × 2)

CY 2 ={whichever is larger [L 2 min + F 2 + P 2 + C L 2 ] or [Z2]} + (courtyard excess × 2)

Level 1 Pattern identifier EIAJ code JEDEC code Z1 Z2 G1 G2 X Y P CY1 CY2

Figure 16 – PLQFP (rectangular) land pattern dimensions

This section outlines the dimensions for the land pattern and components of square PTQFP (plastic thin quad flat pack) devices It also details the basic construction of PTQFP devices Additionally, it concludes with a summary of the tolerances and target solder joint dimensions that inform the land pattern dimensions.

PTQFPs are widely used in variety of applications for commercial, industrial or military electronics

The PTQFPs, along with the LSOP components, are frequently used in memory card applications (see Figure 17)

Solder, composed of 68% tin, can be applied to leads through hot dipping or by plating from a solution It is essential to perform a post-plating reflow operation on plated solder terminations to ensure proper fusion of the solder.

For lead removal applications, various lead-free or lead-free compatible finishes are available It is essential to conduct solderability testing according to IEC 60068-2-54 to assess the attachment capability of the relevant component type.

The carrier package format for flat packs may be tubular in shape but, in most instances, flat packs are delivered in a carrier tray

PTQFPs are usually processed using standard solder reflow processes Parts should be capable of withstanding ten cycles through a standard reflow system operating at 235 °C

Each cycle shall consist of 60 s exposure at 235 °C

Figure 18 provides the component dimensions for PTQFP components

Min Nom Max Max Max

Figure 19 illustrates the shape and dimensions of the solder fillet post-soldering The minimum, median, and maximum dimensions for the toe, heel, and side fillet are established based on the reliability of the solder joint, as well as the quality and productivity during the component mounting process.

The accuracy of land shape in printed wiring boards (PWBs) is influenced by fillet dimensions To determine the tolerance resulting from these factors, specific formulae are applied, particularly in design considerations when soldering without the self-alignment effect (level 1).

The reflow soldering process exhibits a self-alignment effect, allowing for the cancellation of parts mount displacement during soldering, effectively making factor P equal to 0 Additionally, the land shape accuracy tolerance of printed wiring boards (PWBs) is approximately ±30 µm, which is significantly smaller than the dimensional accuracy of the components, leading to factor F also being considered as 0.

T T = C L, Zmax = Lmin + 2J t min + C L = Lmax + 2J T min

T S = C W, Xmax = Wmin + 2J S min + C W = Wmax + J S min

To ensure that the land is not obscured by the QFP, it is essential that the value Gmin is greater than or equal to A and B Additionally, the stand-off of the component mold should be nearly zero, and the land pattern design must be optimized to prevent lead floating due to solder beneath the component.

Figure 20 shows land pattern dimensions for PTQFP and flow soldering These values are calculated based on the formula for the solder joint fillet design given in 8.4

Bảng thông số kỹ thuật của các loại chip P-TQFP và P-LQFP bao gồm nhiều kích thước và thông số khác nhau Các mã sản phẩm như 5095M, 5096M, và 5097M có kích thước từ 32 đến 80 chân, với chiều dài và chiều rộng khác nhau từ 5x5 mm đến 24x24 mm Các thông số như điện áp, dòng điện và kích thước chân cũng được ghi rõ, ví dụ, mã 5102M có kích thước 10x10 mm với điện áp 13,4V và dòng điện 0,80A Các sản phẩm này phù hợp cho nhiều ứng dụng trong lĩnh vực điện tử, từ vi điều khiển đến các mạch tích hợp phức tạp.

Bảng thông số kỹ thuật cho các loại chip P-TQFP và P-LQFP bao gồm nhiều mẫu mã khác nhau với kích thước và thông số kỹ thuật đa dạng Các mẫu chip như 5095N, 5096N, 5097N, và 5098N có kích thước từ 5x5mm đến 10x10mm, với độ dày từ 0,29mm đến 0,48mm Các chip lớn hơn như 5107N, 5108N, và 5114N có kích thước lên đến 12x12mm và 14x14mm, với độ dày tương tự Tất cả các chip này đều có thông số điện áp và dòng điện phù hợp cho nhiều ứng dụng khác nhau trong ngành công nghiệp điện tử.

Pattern identifier EIAJ code JEDEC code Z G X Y P CY1 CY2

5116N P-TQFP-0120-1616-0,50 P-LQFP/120-16x16-0,50 19,0 16,0 0,33 1,5 0,50 19,5 19,5 5117N P-TQFP-0144-1616-0,40 P-LQFP/144-16x16-0,40 19,0 16,0 0,29 1,5 0,40 19,5 19,5 5119N P-TQFP-0128-1818-0,50 P-LQFP/128-18x18-0,50 21,0 18,0 0,33 1,5 0,50 21,5 21,5 5120N P-TQFP-0160-1818-0,40 P-LQFP/160-18x18-0,40 21,0 18,0 0,29 1,5 0,40 21,5 21,5 5122N P-TQFP-0112-2020-0,65 P-LQFP/112-20x20-0,65 23,0 20,0 0,42 1,5 0,65 23,5 23,5 5123N P-TQFP-0144-2020-0,50 P-LQFP/144-20x20-0,50 23,0 20,0 0,33 1,5 0,50 23,5 23,5 5124N P-TQFP-0178-2020-0,40 P-LQFP/176-20x20-0,40 23,0 20,0 0,29 1,5 0,40 23,5 23,5 5126N P-TQFP-0176-2424-0,50 P-LQFP/176-24x24-0,50 27,0 24,0 0,33 1,5 0,50 27,5 27,5 5127N P-TQFP-0216-2424-0,40 P-LQFP/216-24x24-0,40 27,0 24,0 0,29 1,5 0,40 27,5 27,5

Bảng thông số kỹ thuật cho các loại chip P-TQFP và P-LQFP bao gồm nhiều kích thước và thông số khác nhau Các mã sản phẩm như 5095L, 5096L, 5097L, và 5098L cung cấp các kích thước từ 32 đến 80 chân với chiều dài và chiều rộng khác nhau, từ 5x5 mm đến 14x14 mm Các thông số như chiều cao, khoảng cách chân, và kích thước chân cũng được liệt kê, ví dụ như 0,25 mm, 0,40 mm, và 0,50 mm Các chip lớn hơn như 5126L và 5127L có kích thước lên đến 24x24 mm, phù hợp cho các ứng dụng yêu cầu hiệu suất cao Tất cả các sản phẩm đều có thông số kỹ thuật chi tiết, giúp người dùng dễ dàng lựa chọn chip phù hợp với nhu cầu của họ.

Figure 20 – PTQFP land pattern dimensions

IEC 60068-2-54, Environmental testing – Part 2-54: Tests – Test Ta: Solderability testing of electronic components by the wetting balance method

IEC 60068-2-58, Environmental testing – Part 2-58: Tests – Test Td: Test methods for solderability, resistance to dissolution of metallization and to soldering heat of surface mounting devices (SMD)

IEC 60191-2 (all parts), Mechanical standardization of semiconductor devices – Part 2:

IEC 61191-1, Printed board assemblies – Part 1: General specification – Requirements for soldered electrical and electronic assemblies using surface mount and related assembly technologies

Tiêu đề	IEC 61188-5-5:2007 - Printed Boards and Printed Board Assemblies – Design and Use – Part 5-5: Attachment (Land/Joint) Considerations – Components with Gull-Wing Leads on Four Sides
Trường học	International Electrotechnical Commission
Thể loại	Standard
Năm xuất bản	2007
Thành phố	Geneva

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Số trang	48
Dung lượng	1,07 MB