BSI Standards PublicationIntegrated circuits — Measurement of electromagnetic immunity Part 1: General conditions and definitions... NORME EUROPÉENNE English Version Integrated circuits
General
The default test conditions are designed to maintain a consistent testing environment Any alternative values agreed upon by the users must be documented in the test report.
Ambient conditions
Ambient temperature
The ambient temperature during the test shall be 23 °C ± 5 °C
NOTE The RF immunity of some ICs is dependent on the ambient temperature.
RF ambient
The RF ambient noise level must be at least 6 dB below the lowest intended immunity measurement, which should be verified prior to testing The Device Under Test (DUT) should be set up with the power supply disabled, and the RF ambient conditions must be detailed in the test report.
RF-immunity of the test setup
Prior to conducting the test, it is essential to verify that all equipment involved in the test setup, apart from the Device Under Test (DUT), is adequately shielded from disturbance signals to prevent any impact on the test outcomes.
Other ambient conditions
All other ambient conditions that may affect the test result shall be stated in the individual test report
NOTE Even illumination would influence the test results when a semiconductor device is exposed in an open ceramic IC package.
Test generator
Depending on applications and the desired test, various test signals (disturbance signals) can be used:
– non-modulated RF signal (continuous wave);
– amplitude-modulated RF signal, e.g according to IEC 61000-4-6 and IEC 61000-4-3; – pulse-modulated RF signals , e.g according to IEC 61000-4-3.
Frequency range
The recommended frequency range for applications is between 150 kHz and 1 GHz, with the possibility of extension based on specific procedures Depending on the requirements of the application, the range of interest may be narrower Each section of IEC 62132 outlines the applicable frequency range.
General
Clause 5 outlines the common equipment used across all test methods in IEC 62132, while the specific components of the test equipment are detailed in the individual procedures of each part.
Shielding
The shielding requirements for testing are influenced by the test method, ambient noise levels, and the sensitivity of the equipment involved Typically, the ambient RF noise must be at least 6 dB lower than the disturbance signal to ensure adequate margin A shielded room may be necessary to provide sufficient attenuation for the protection of operators, equipment, and telecommunication services Additionally, some measurement setups incorporate intrinsic shielding Detailed measurement procedures are outlined in each section of IEC 62132.
Test generator and power amplifier
The test generator will provide the specified test signal as outlined in section 4.3 The RF power amplifier must comply with the testing requirements detailed in other sections of IEC 62132 It is essential that the amplitude response is linear, with distortions maintained below -20 dBc to minimize spurious signals.
20 dB below the RF carrier level) of the signal amplitude.
Other components
It shall be checked that cables, connectors and terminators included in the measurement path meet the required characteristics over the intended frequency range
Ensure that cables, connectors, and terminators not directly in the measurement path between the reference point and the measuring instrument are evaluated for their characteristics over the intended frequency range, as they can still influence the measurement results.
General
The test setup must adhere to the specific procedures outlined in the relevant section of IEC 62132, and all pertinent test parameters should be documented to guarantee the reproducibility of the results.
Test circuit board
The selection of test boards for RF immunity testing is guided by the measurement methods outlined in IEC 62132, with general recommendations provided in Annex B It is essential to include a description of the test board in the test report, ensuring that the boards adhere to the good layout practices specified in other sections of IEC 62132.
The interaction between the electromagnetic (EM) environment and integrated circuits (IC) during immunity testing resembles that of radio frequency (RF) emission testing, allowing for the use of similar test boards However, the key distinction lies in the monitoring of output signals in immunity tests to determine the impact of RF disturbances on the IC.
Pin selection scheme
Pins that are considered to be subject to RF immunity testing are those connected to external devices through cables, e.g.:
– communication cables, e.g for use with controller area network (CAN), RS 422/485, unshielded twisted pairs (UTP) with ethernet, low voltage differential signalling (LVDS)
Pins that are connected by traces to active or passive devices on the application board are not considered to be subject to RF immunity testing (see IEC 62132-3 and IEC 62132-4), e.g.:
– biasing or current reference inputs with analogue part.
IC pin loading/termination
The DUT pins must be loaded or terminated based on the default values outlined in Table 1, which includes manufacturer-specified parameters Any pins not categorized in Table 1 should be loaded as functionally necessary The pin loading conditions during testing must be documented in the test report.
Table 1 – IC pin loading default values
IC pin type Pin loading
– Supply According to the device specification
– Input 10 kΩ to ground (V ss ) unless the IC is internally terminated
– Output signal 10 kΩ to ground (V ss ) unless the IC is internally terminated
– Output power Nominal loading as stated by the manufacturer
– Supply According to device specification
– Input Ground (V ss ) or 10 kΩ to supply (V dd ) if the input cannot be grounded, unless the IC is internally terminated – Output 47 pF to ground (V ss )
– Input Ground (V ss ) or 10 kΩ to supply (V dd ) if the input cannot be grounded, unless the IC is internally terminated – Output According to the device specification
– Bi-directional 47 pF to ground (V ss )
– Analogue According to the device specification
Power supply requirements
The Device Under Test (DUT) must be powered by a source that is unaffected by the test signal If a battery is utilized, it should comply with Integrated Circuit (IC) requirements and deliver a stable voltage to ensure consistent operation Additionally, all power supply lines to the DUT must be properly filtered in accordance with the recommendations of the IC manufacturer.
IC specific considerations
IC supply voltage
The supply voltage(s) shall be as specified by the IC manufacturer with a tolerance of ±5 %.
IC decoupling
The test report must specify the value and layout position of power supply decoupling capacitors It is recommended to follow the manufacturer's guidance for decoupling each supply pin of the device under test (DUT).
NOTE A term, ”blocking capacitors,” is used instead of “supply decoupling capacitors” in IEC 62132-4.
Operation of IC
Attempts should be made to fully execute and test all relevant functions that significantly contribute to the immunity of the IC
To achieve higher test throughput, the integrated circuit (IC) can be set to a fixed operation mode, enabling the disturbance signal to be swept across the relevant frequency range Utilizing asynchronous operation modes between the device under test (DUT) and the RF disturbance signals effectively simulates real-world operating conditions.
When a relation between the activity of the IC and the test signal exists, it should be documented in the test report.
Guidelines for IC stimulation
To ensure test reproducibility for a specific integrated circuit (IC) function, it is essential to control certain parameters as agreed upon by the manufacturer and user For programmable ICs, a continuous loop software must be developed to guarantee consistent measurements Additionally, the test report should document the type of software utilized to drive the IC, whether it is minimum, typical, or worst case.
IC monitoring
IC monitoring is intended to monitor all relevant activity states without disturbing the immunity performance.
IC stability over time
The IC's functional behavior must remain stable throughout the entire measurement process to guarantee that results can be consistently reproduced within the anticipated measurement tolerances.
Monitoring check
Energize the DUT and complete an operational check for proper function of the DUT and normal activity, and ensure proper function of the failure detection.
Human exposure
For open RF immunity tests without shielding structure or shielding enclosure, precautions shall be taken not to exceed the applicable human exposure limits.
System verification
The DUT can be checked on various parameters or responses Examples include:
– DC output voltage (e.g voltage regulator);
– supply current (cross current may increase due to change of threshold voltages);
– demodulated audio frequency signal (e.g audio amplifier, video);
– jitter (e.g time base, logic gate, àCs, AD/DA-converters);
Specific procedures
Frequency steps
The measurement frequency range typically spans from 150 kHz to 1 GHz, with some methods extending beyond this limit The practical test frequency range is influenced by the cut-off frequencies of the injection network and the test setup, such as IC-decoupling The frequency step size should be chosen based on Table 2, and for specific immunity measurement procedures, refer to other sections of IEC 62132.
Table 2 – Frequency step size versus frequency range
Logarithmic steps ≤5 % increment a The frequency step for the frequency range above 10 000 MHz is specified in each part of the IEC 62132 series, if necessary
Critical frequencies such as clock frequencies, system frequencies of RF devices, etc should be tested in finer frequency steps, as agreed by the users of this procedure
Above 1 GHz, resonances will be seen in most of the radiated and conducted immunity test due to mechanical sizes of the test setups (cavity effects), test board (100 mm × 100 mm) or from the DUT itself, e.g die pad size, heat spreader, heat sink The quality of these resonances can be high Responses from the DUT above 1 GHz are not related with the functional operational frequencies of the device (or its multiples thereof), so that they shall be ignored but recorded in the test report (with probable explanation on their cause(s)).
Amplitude modulation
The disturbance signal shall follow the test method chosen, e.g CW (continuous wave), 80 % amplitude modulated by a 1 kHz sine wave or pulse modulated wave.
Power levelling for modulation
The IEC 62132 series defines disturbance signals in different ways, either by maintaining the peak power of the RF signal or the power of the RF carrier, which is commonly used in most RF generators.
NOTE The application of the power-levelling method is different from the RF modulation used with product immunity standards such as IEC 61000-4-3 and IEC 61000-4-6
When conducting an immunity test at peak test levels, it is essential that the peak power of the AM test signal matches the peak power of the continuous wave, irrespective of the modulation index \( m \).
NOTE For example: 80 % AM modulation (m = 0,8) results in: P AM =0,407⋅P CW ,
Figure 1 – RF signal when RF peak power level is maintained
Dwell time
The dwell time for each frequency step and modulation should generally be set to 1 second or at least long enough for the Device Under Test (DUT) to respond, allowing the measurement system to accurately record the data Users are responsible for defining the response time of the DUT.
Monitoring of the IC
The test will be conducted with careful attention to all operational functions, ensuring that the test signal is properly leveled This control is essential for accurately detecting all critical responses of the Device Under Test (DUT), including hysteresis effects and reactions to level variations.
General
IC testing must adhere to a defined test plan, which should be documented in the test report This plan outlines specific parameters and expected responses for the IC tests For instance, it should specify which IC pins will be tested individually or in combination, as well as the applicable immunity acceptance criteria.
This report shall also include:
– circuit diagram of the application (supply decoupling, pin loading/terminations, peripheral ICs, etc.);
– description of the test board on which the IC is applied (layout);
– actual operating conditions of the IC (supply voltage, output signals, etc.);
– description of the type of software exercising the IC(s), if applicable
All deviations to the defined test conditions shall be documented in the test report
Other particular requirements for the different test methods are described in the respective parts
Immunity limits or levels
Immunity test levels, criteria or limits depend upon the application and functional requirements.
IC performance classes
The IC immunity can be classified by IC performance classes which slightly differ from electronic unit performance classes as follows:
Class A IC : All monitored functions of the IC perform within the defined tolerances during and after exposure to disturbance
Class B Integrated Circuits (ICs) may not be suitable for evaluating short-term degradation of monitored signals during disturbances, as this classification is not applicable to ICs.
Short-term degradation of monitored signals may be acceptable in applications due to their error handling mechanisms, which are often not well understood in the context of integrated circuit (IC) testing.
Class C IC refers to an integrated circuit where at least one monitored function falls outside the specified tolerances during a disturbance but automatically returns to the defined tolerances after the disturbance has ceased.
Class D IC : At least one monitored function of the IC does not perform within the defined tolerances during exposure and does not return to normal operation by itself The
IC returns to normal operation by manual intervention
Class D1 IC The IC returns to normal operation by manual intervention: (e.g reset)
Class D2 IC The IC returns to normal operation by power cycling the device
Class E IC : At least one monitored function of the IC does not perform within the defined tolerances after exposure and can not be returned to proper operation.
Interpretation of results
Comparison between IC(s) using the same test method
To ensure accurate comparisons, measurements must be conducted under identical conditions, utilizing the same code across devices It is essential to maintain a consistent test environment and use the same test board for all evaluations.
Comparison between different test methods
A quantitative correlation among various test methods addressing different phenomena is neither anticipated nor pursued However, correlations have been established for methods that assess the same phenomena, as detailed in Annex A.
Correlation to module test methods
When sufficient data is available to correlate measured values with expected immunity from the integrated circuit (IC) for a specific application, this correlation should be detailed in the specific test method, such as component or system level tests The translation from IC level immunity to module or product level involves several factors, and this IC-to-module correlation is generally applicable only in controlled scenarios.
Table A.1 and Table A.2 should be used as a guideline
Test method Bulk current injection Direct RF power injection Workbench Faraday cage
Document number IEC 62132-3 IEC 62132-4 IEC 62132-5
Type of disturbances Conducted Conducted Conducted
Proposed frequency range 150 kHz to 1 000 MHz 150 kHz to 1 000 MHz 150 kHz to 1 000 MHz Frequency range extendable Downwards, current injection probe dependent Upwards, injection network dependent Not recommended
Measurement of disturbances RF current RF forward power RF voltage
Common-mode disturbances Yes Yes Yes
Differential-mode disturbances Yes Yes No
Single pin influencing Yes Yes No
Multiple pin influencing Yes Yes Yes
– comparison of ICs Dedicated According to Annex B According to Annex B – evaluation in application n.a Not restricted Not restricted
Verification of coupling path Yes, via measurement Yes, via measurement No
Reproducing of measurement; High High High
IC qualification Yes Yes Yes
Working in a shielded room or a shielded enclosure
Yes Recommended, depends on power level (see national and international safety standards)
– drain/path analysis Yes Yes No
– on-chip coupling (cross- talk) Yes Yes Yes
Test method (G-)TEM Cell IC stripline Surface scan
Document number IEC 62132-2 IEC 62132-8 IEC TS 62132-9
Type of disturbances Radiated Radiated Radiated
Proposed frequency range 150 kHz to 2 GHz and higher (up to 18 GHz) 150 kHz to 3 GHz 150 kHz to 6 GHz Frequency range extendable Upwards, cell dependent Upwards, stripline dependent Probe dependent
Measurement of disturbances Electric and magnetic field Electric and magnetic field Electric and magnetic field
– comparison of ICs According to Annex B According to Annex B According to Annex B – evaluation in application Not restricted Not restricted Not restricted
Verification of coupling path No No Yes
Reproducing of measurement High High High
IC qualification Yes Yes No
Working in a shielded room or a shielded enclosure
Recommended, depending on power level (see national and international safety standards)
IC immunity (Possible by probe positioning.)
– drain/path analysis No No Yes
– on-chip coupling (cross- talk) No No Yes
Overview
This annex serves as a comprehensive guide for designing a universal test board essential for evaluating the EMC performance of various integrated circuits (ICs) from different manufacturers It outlines the constraints on parameters that significantly impact EMC characteristics.
Board description – Mechanical
The test board measures 100 ± 3 mm × 100 ± 3 mm, with optional holes at the corners as illustrated in Figure B.1 To ensure proper contact with the TEM cell, all edges of the board must be tinned with a minimum width of 5 mm or made conductive Alternatively, the edges can be gold-plated.
The vias at the outer edge of the board shall be at least 5 mm away from that edge.
Board description – Electrical
General
Figure B.1 illustrates the universal test board, which requires at least a double-layer configuration Additional layers, such as layers 2 and 3, can be incorporated as needed to develop a multi-layer board.
Layer 1 is for the ground plane Layer 4 can be used for ground, power and other signals, but shall be left as intact as possible to be used as a ground plane as well
The test board design will feature the IC package positioned solely on one side (layer 1), while all other components and trace patterns will be located on the opposite side (layer 4).
Ground planes
The ground planes (layers 1 and 4) shall be interconnected by means of vias These vias shall be placed at the following positions over the board as described in Table B.1
Table B.1 – Position of vias over the board
1 All around, at the edges of the board
2 Just outside the DUT area
3 Just inside, underneath the IC area
The ground plane at layer 1 shall be continued in between vias at position 2 As such the ground plane at layer 1 is continued over the whole board
If possible the same shall be done for layer 4, but the possibility to do so depends on the IC package and the space available.
Package pins
All essential components and supply/I/O ports for measuring responses or providing signals, excluding the IC, must be installed on layer 4 Consequently, it is crucial to connect I/O and other necessary pins from layer 1 to layer 4 Additionally, optimizing loop areas, trace lengths, via placements, and component orientations is essential to achieve minimal loop areas.
These packages do not require vias, as plated through-hole pins are considered present or established by the pins themselves
These packages necessitate the use of vias, which should ideally be centered in the soldering pads for the ICs To reduce the loop area through which the IC currents flow, it is recommended that these vias be positioned at location 3 in Table B.1.
These packages do not require vias, as plated through-hole pins are considered present or established by the pins themselves
These packages require the use of vias The vias for power supply and ground interconnection should preferably be located in accordance with the manufacturer’s recommendations.
Via diameters
All vias at position 1 have a hole diameter of 0,8 mm All other vias have a diameter of 0,2 mm.
Via distance
Via placement shall be controlled as follows for measurements up to 1 GHz The maximum lateral distance between vias connecting layer 1 to layer 4 (positions 1, 2 and 3) shall be
10 mm Vias for signal traces shall be placed as close as possible to those vias connecting layer 1 to layer 4.
Additional components
All supplementary components must be installed at layer 4, ensuring they are positioned to avoid any interference with the constraints established for layers 1 and 4, as well as the interconnecting vias.
Supply decoupling
For reliable measurement data, proper supply decoupling is essential, following the specifications of the test board Decoupling capacitors on the test board are categorized into two groups The specific values and placement of these decoupling capacitors, along with other related components, must be detailed in the individual test report.
For optimal performance of the device under test (DUT), supply decoupling for the integrated circuit (IC) must adhere to the manufacturer's guidelines Decoupling capacitors should be connected to the ground plane on layer 4, directly beneath the IC, as illustrated in Figure B.1 The value and placement of each decoupling capacitor for the DUT's supply pins should align with the manufacturer's recommendations or be specified in the test report.
B.3.7.3 Power supply decoupling for the test board
Inadequate design of power supply decoupling on the test board can significantly impact measurement results To manage the supply impedance for any external power supply used in measurements, a set of decoupling capacitors must be strategically placed on the test board The values and layout of these capacitors should adhere to the specific measurement standards or be clearly outlined in the test report.
I/O load
Additional components necessary to load or activate the IC shall be mounted on layer 4, preferably directly underneath the IC package area This includes the necessary ports to allow
IC monitoring during the RF immunity test
Figure B.1 – Example of an immunity test board
Layer 4 – ground and/or signal and/or power
0,2 vias connect DUT pin traces
Additional components shall be added at layer 4, preferably inside the via perimeter
Additional holes may be added at the corners
0,8 vias connect layer 1 with layer 4
Ground plane extended below DUT
0,8 vias connect layer 1 with layer 4
Supply decoupling shall be referred to this part of the ground plane
All non-ground layers shall be recessed
2 mm away from board edges +3 100 –1 s quar ed
IEC 60050 (all parts), International Electrotechnical Vocabulary (available at
IEC 61000-4-3, Electromagnetic compatibility (EMC) – Part 4-3: Testing and measurement techniques – Radiated, radio frequency, electromagnetic field immunity test
IEC 61000-4-6, Electromagnetic compatibility (EMC) – Part 4-6: Testing and measurement techniques – Immunity to conducted disturbances, induced by radio-frequency fields
IEC 61967-1:2002, Integrated circuits – Measurement of electromagnetic emissions, 150 kHz to 1 GHz – Part 1: General conditions and definitions
CISPR 20, Sound and television broadcast receivers and associated equipment – Immunity characteristics – Limits and methods of measurement
ANSI/IEEE Std 100-1984 (updated 2000), IEEE Standard Dictionary of Electrical an Electronics Terms, Third Edition, Distributed by: Wiley Interscience