Bsi bs en 61340 3 2 2007

BS EN 61340 3 2 cover fm BRITISH STANDARD BS EN 61340 3 2 2007 Electrostatics — Part 3 2 Methods for simulation of electrostatic effects — Machine model (MM) electrostatic discharge test waveforms The[.]

BRITISH STANDARD BS EN

61340-3-2:2007

Electrostatics —

Part 3-2: Methods for simulation of

electrostatic effects — Machine model

(MM) electrostatic discharge test

waveforms

The European Standard EN 61340-3-2:2007 has the status of a

British Standard

ICS 17.220.99; 29.020

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BS EN 61340-3-2:2007

This British Standard was

published under the authority

of the Standards Policy and

Strategy Committee

on 30 April 2007

© BSI 2007

ISBN 978 0 580 50470 9

National foreword

This British Standard was published by BSI It is the UK implementation of

EN 61340-3-2:2007 It is identical with IEC 61340-3-2:2006 It supersedes

BS EN 61340-3-2:2002 which is withdrawn

The UK participation in its preparation was entrusted to Technical Committee GEL/101, Electrostatics

A list of organizations represented on GEL/101 can be obtained on request to its secretary

This publication does not purport to include all the necessary provisions of a contract Users are responsible for its correct application

Compliance with a British Standard cannot confer immunity from legal obligations.

Amendments issued since publication

EUROPEAN STANDARD EN 61340-3-2

NORME EUROPÉENNE

CENELEC

European Committee for Electrotechnical Standardization Comité Européen de Normalisation Electrotechnique Europäisches Komitee für Elektrotechnische Normung

Central Secretariat: rue de Stassart 35, B - 1050 Brussels

© 2007 CENELEC - All rights of exploitation in any form and by any means reserved worldwide for CENELEC members

Ref No EN 61340-3-2:2007 E

ICS 17.220.99; 29.020 Supersedes EN 61340-3-2:2002

English version

Electrostatics - Part 3-2: Methods for simulation of electrostatic effects -

Machine model (MM) electrostatic discharge test waveforms

(IEC 61340-3-2:2006)

Électrostatique -

Partie 3-2: Méthodes pour la simulation

des effets électrostatiques -

Formes d'onde d'essai des décharges

électrostatiques pour les modèles

de machine (MM)

(CEI 61340-3-2:2006)

Elektrostatik - Teil 3-2: Verfahren zur Simulation elektrostatischer Effekte -

Prüfwellenformen der elektrostatischen Entladung für das Machine Model (MM) (IEC 61340-3-2:2006)

This European Standard was approved by CENELEC on 2007-02-01 CENELEC members are bound to comply with the CEN/CENELEC Internal Regulations which stipulate the conditions for giving this European Standard the status of a national standard without any alteration

Up-to-date lists and bibliographical references concerning such national standards may be obtained on application to the Central Secretariat or to any CENELEC member

This European Standard exists in three official versions (English, French, German) A version in any other language made by translation under the responsibility of a CENELEC member into its own language and notified

to the Central Secretariat has the same status as the official versions

CENELEC members are the national electrotechnical committees of Austria, Belgium, Bulgaria, Cyprus, the Czech Republic, Denmark, Estonia, Finland, France, Germany, Greece, Hungary, Iceland, Ireland, Italy, Latvia, Lithuania, Luxembourg, Malta, the Netherlands, Norway, Poland, Portugal, Romania, Slovakia, Slovenia, Spain, Sweden, Switzerland and the United Kingdom

EN 61340-3-2:2007 – 2 –

Foreword

The text of document 101/237/FDIS, future edition 2 of IEC 61340-3-2, prepared by IEC TC 101, Electrostatics, was submitted to the IEC-CENELEC parallel vote and was approved by CENELEC as

EN 61340-3-2 on 2007-02-01

This European Standard supersedes EN 61340-3-2:2002

The major change of EN 61340-3-2:2007 is that it no longer contains the application to semiconductor devices

It recognizes the direction of the IEC SMB (Standardization Management Board) in terms of considering inputs from TC 47 documents with regard to ESD test methods TC 101 has revised this IEC 61340-3-2, concerning the machine model, in collaboration with the JWG of TC 47/TC 101 IEC 61340-3-2 incorporates TC 47 input, based on the corresponding TC 47 IEC 60749-27

The following dates were fixed:

– latest date by which the EN has to be implemented

at national level by publication of an identical

– latest date by which the national standards conflicting

Endorsement notice

The text of the International Standard IEC 61340-3-2:2006 was approved by CENELEC as a European Standard without any modification

– 3 – EN 61340-3-2:2007

ELECTROSTATICS – Part 3-2: Methods for simulation of electrostatic effects –

Machine model (MM) electrostatic discharge test waveforms

1 Scope

This part of IEC 61340 describes the discharge current waveforms used to simulate machine model (MM) electrostatic discharges (ESD) and the basic requirements for equipment used to develop and verify these waveforms

This standard covers MM ESD waveforms for use in general test methods and for application

to materials or objects, electronic components and other items for ESD withstand test or performance evaluation purposes The specific application of these MM ESD waveforms to non-powered semiconductor devices is covered in IEC 60749-27

2 Terms and definitions

For the purposes of this document, the following terms and definitions apply

2.1

unit under test

UUT

material, object, item or product to be subjected to the MM ESD test

2.2

UUT failure

condition in which a UUT does not meet one or more specified parameters as a result of the

ESD test

2.3

ESD withstand voltage

maximum applied ESD voltage level that does not cause failure parameter limits to be exceeded provided that all UUTs stressed at lower levels have also passed

3 Equipment

This equipment produces an electrostatic discharge current pulse simulating a MM ESD event

loads are illustrated in Figure 1

Equipment capable of verifying the MM current waveform is defined in this standard This equipment includes, but is not limited to, a waveform recording system, a high-voltage resistor and a current transducer

EN 61340-3-2:2007 – 4 –

The waveform recording system shall have a minimum single shot bandwidth of 350 MHz

Two evaluation loads are necessary to verify the functionality of the waveform generator: a) load 1: a shorting wire;

the voltages that will be used for waveform qualification

The lead length of the evaluation loads (shorting wire or resistor) shall be as short as possible

in Figure 1) while passing through the current transducer

The current transducer shall have a minimum bandwidth of 350 MHz

4 MM current waveform requirements

4.1 General

Prior to UUT testing, the MM ESD waveform generator qualification shall ensure the waveform integrity of the discharge current through both a shorting wire and a resistive load The shorting wire waveform requirements are specified in Figure 2 for all positive and negative

shown in Figure 3 and Table 1

Equipment qualification shall be performed during initial acceptance testing Re-qualification

is required whenever equipment repairs are made that may affect the waveform Additionally, the waveforms shall be verified periodically If a test fixture or circuit-board is used to perform UUT testing, the test fixture (board) shall also be used during equipment qualification tests In case the waveform no longer meets the waveform parameters described in Table 1 and Figures 2 and 3, all ESD testing performed after the previous satisfactory waveform check shall be considered invalid

– 5 – EN 61340-3-2:2007

Key

1 MM ESD waveform generator (nominally 200 pF)

2 terminal A

3 switch

4 terminal B

5 UUT

6 evaluation load

7 shorting wire

8 resistance R = 500 Ω

9 current transducer

Figure 1 – MM ESD waveform generator equivalent

Requirements for Figure 1:

a) The evaluation loads (7 and 8) are specified in 3.2.2

b) The current transducer (9) is specified in 3.2.3

c) The reversal of terminals A (2) and B (4) to achieve dual polarity is not permitted

d) The switch (3) is closed 10 ms to 100 ms after the pulse delivery period of each single MM pulse to ensure that the UUT and any test fixture are not left in a charged state

NOTE 1 The performance of the waveform generator is strongly influenced by parasitic capacitance and inductance

NOTE 2 Precautions should be taken in the design of the waveform generator to avoid recharge transients and double pulses

NOTE 3 A resistance in series with the switch ensures a slow discharge of the UUT

IEC 678/02

EN 61340-3-2:2007 – 6 –

Table 1 – Waveform specification Level Equivalent

voltage

V

Ip1 peak current

through a shorting wire

A (±15 %)

IPR peak current

through a 500 Ω resistor

A

I100 current through a

500 Ω resistor at 100 ns

A (±15 %)

20 ns per division

Ip1

tpm

t1

t3

Ip2

IEC 682/02

Figure 2 – Typical current waveform through a shorting wire

Requirements for Figure 2:

The current pulse shall meet the following requirements

Ip1 the maximum peak current is specified in Table 1

Ip2 the second peak current shall be between 67 % and 90 % of the absolute value

obtained for Ip1 for each level

point, t3

– 7 – EN 61340-3-2:2007

20 ns per division

IPR

I100

IEC 683/02

Figure 3 – Typical current waveform through a 500 Ω resistor

Requirements for Figure 3

5 Evaluation of ESD robustness of the UUT

5.1 General

Application conditions appropriate to the UUT shall be established for the following parameters:

• stress voltage levels;

• test temperature and humidity;

• relevant parameter specification limits indicating ESD test failure

5.2 Evaluation of UUTs that have electrical terminals

Evaluation of the ESD robustness of a UUT that has electrical terminals will often require that the terminals are classified into different types, for example, input, output, power supply or ground

EN 61340-3-2:2007 – 8 –

Each non-power supply terminal shall then be tested (one at a time) with respect to power supply or ground terminals

In the case of evaluation of UUTs that have electrical terminals, the weakest pin combination and the failure threshold for MM should be found Thus, UUTs that do not have many electrical terminals, generally are tested for MM on all pin combination, but, in the case of UUTs having many electrical terminals, it is possible to select the test pin combination as the pin grouping

The specific application of the MM waveform to determine the ESD robustness of semiconductor devices is given in IEC 60749-27

5.3 Evaluation of UUTs that do not have electrical terminals

In the case where the UUT is a material or object that does not have electrical terminals (for example, packaging materials), it may be necessary to apply the waveform to the UUT via applied electrodes or other appropriate means

6 Test procedure

An appropriate test procedure shall be defined according to the specific application

NOTE 1 The specific application of the MM waveform to determine the ESD robustness of semiconductor devices

is given in IEC 60749-27

It is permitted to use any voltage level as the starting stress level One pulse of both polarities shall be applied for all UUT terminal or electrode combinations and stress levels

NOTE 2 Some types of UUT may have “fail windows” in which no failures are sustained over a range of applied ESD stress levels (for example, no fail at 100 V, fail at 200 V, no fail at 300 V and fail again from 400 V upwards)

It is recommended that no stress level should be missed in order to detect such fail windows

It is permitted to use separate samples for each UUT stress combination and/or polarity It is permitted to use the same samples at the next higher voltage level if all UUT samples pass the failure criteria at testing after stressing at the lower level

If a different UUT sample is stressed at each level and/or combination and/or polarity, it is permitted to perform UUT testing after all samples have been stressed

7 Failure criteria

A UUT is considered to have experienced an ESD failure if it does not meet all the relevant parameter specifications following the ESD test

8 MM ESD withstand classification

An appropriate classification system for the application shall be established if required

NOTE The ESD withstand voltage will normally be an appropriate basis for classification, but, in some cases, other bases may be used In many cases, it will be sufficient to refer to the UUT ESD withstand voltage without the need for an additional classification system

The basic MM ESD withstands classification applicable to semiconductor devices is given in IEC 60749-27

– 9 – EN 61340-3-2:2007

Bibliography

IEC 60749-27, Semiconductor devices – Mechanical and climatic test methods – Part 27:

Electrostatic discharge (ESD) sensitivity testing – Machine model (MM)

NOTE Harmonized as EN 60749-27:2006 (not modified)

_

BS EN

61340-3-2:2007

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