4 lab

These include a VGA Pixel Buffer, a VGA Character Buffer, and a VGA Controller circuit, which are used together with the a memory module and the corresponding memory controller to allow

LAB 4: Video Output Interface

Abstract

The purpose of this lab is to learn how to display images and perform animation on a Video Graphic Array (VGA) component

1 Introduction

The Altera University Program provides a number of hardware controllers, called cores, to control the VGA

Digital-to-Analog Converter (DAC) and display images on a screen These include a VGA Pixel Buffer, a VGA Character Buffer, and a VGA Controller circuit, which are used together with the a memory module and the

corresponding memory controller to allow programs executed by the Nios II processor to generate images for

display on the screen If both the Pixel and Character Buffers are being used in the same system, the Alpha Blending core must be used to combine the two video streams For this lab, VGA Pixel Buffer is located in

SRAMand VGA Character Buffer is located in the on-chip memory.

More information on the Video Cores may be found in Video Out IP Cores for Altera DE Boards [1].

Pixel Buffer

The Pixel Buffer sends pixel color values from a memory buffer to the VGA Controller, via an Avalon

Streaming Interface The starting address of the memory buffer is user selectable Using the default settings, pixel values consist of 16 bits, and the memory buffer is accessed using half-word operations The pixel buffer converts the 16-bit pixels to the 30-bit pixels required by the VGA Controller, and scales the resolution where appropriate The pixel buffer can be configured to provide different resolutions Using the default settings, the resolution is 320x240 pixels for the VGA DAC The resolution of 320x240 pixels will be used in this lab

The VGA pixel buffer gives the size of the screen and the location in the SRAM memory where an image to be

displayed is stored To display an image on the screen, the VGA pixel buffer retrieves it from memory and sends it to the Alpha Blending core which combines two video streams into one For this lab, the Alpha Blending core is used to combine video streams from VGA pixel and VGA character buffers Fig 1 shows the block diagram for the Alpha Blending core.

Fig 1 Block diagram for the Alpha Blending core

The Alpha Blending core sends the combined video stream to the VGA controller The VGA controller then uses

theVGA DAC to send the image data across the VGA cable to the screen

An image consists of a rectangular array of picture elements, called pixels Each pixel appears as a dot on the screen, and the entire screen consists of 320 columns by 240 rows of pixels, as illustrated in Fig 2 Pixels are arranged in a rectangular grid, with the coordinate (0; 0) at the top-left corner of the screen

Fig 2 Pixel array

The address of each pixel is formatted by adding an offset to the base address The supported addressing modes are called consecutive mode and X-Y mode

 Consecutive mode— the pixel addresses are consecutively laid out in the addressable space For example, for 320x240 resolution the pixel at screen coordinate (0, 0) is at the offset 0x0000, (0, 1) is at offset 0x0001, (0, 319) is at offset 0x13F, (1, 0) is at offset 0x140, and so on

 X-Y mode—the address contains x and y coordinates The format of the address is shown in Fig 3

The values of m and n, shown in the figure, are related to the VGA Core’s resolution, as follows:

2

(log )

m  ceil X

2

(log )

n  ceil Y

where X and Y are the resolution in the X, Y directions, respectively For example, for 320x240 resolution we have

2

(log 320) 9

m  ceil 

2

(log 240) 8

n  ceil 

( , )

Pixel Address x y Base Address offset

Base Address y x

Fig 3.X-Y address format for the320x240resolution.

The color of a pixel is a combination of three primary colors: red, green and blue By varying the intensity of each primary color, any other color can be created We use a 16-bit half-word to represent the color of a pixel The five most-significant and least-significant bits in this half-word represent the intensity of the red and blue components, respectively, while the remaining six bits represent the intensity of the green color component, as

shown in Fig 4 For example, a red color would be represented by a value 0xF800, a purple color by a value 0xF81F, white by 0xFFFF, and gray by 0x8410

Fig 4.Pixel Buffer’s data format for the 16-bit color mode.

The VGA pixel buffer module contains memory-mapped registers that are used to access the VGA pixel buffer information and control its operation These registers are listed in Fig 5 The Buffer and Back buffer registers store the locations in the memory where two image buffers are located The first buffer, called the front buffer, is

the memory where the image currently visible on the screen is stored Initially, both buffers can point to the same image If the computer takes too much time to render a new image on screen which may appear to

flicker, the Back buffer can be used for processing and the front buffer can be used for displaying This technique

is called double buffering To enable double buffering, we need to separate the front and the back buffers For example, use half of the SRAM memory for the front buffer, and the other half for the back buffer The Back buffer

register allows the start address of the memory buffer to be changed under program control To change the memory buffer address:

 The desired new address is first written into the Back buffer register.

 Then, a second write operation is performed using the address of the read-only Buffer register The

value of the data provided in this second write operation is not used by the pixel buffer instead, it

interprets a write to the Buffer register as a request to swap the contents of the Buffer and Back buffer registers The swap does not occur immediately Instead, the swap is done after the Pixel Buffer reaches the last pixel value associated with the screen currently being drawn by the VGA controller While this screen is not yet finished, the bit S of the status register is set to 1 After the current screen is finished, the swap is performed and bit S is set to 0.

Fig 5.VGA pixel buffer memory-mapped registers.

The Resolution register provides the X resolution of the screen in bits 15-0, and the Y resolution in bits 31-16 Finally, the status register provides information for the Pixel Buffer,

 m: width of the X coordinate (bits 31-24).

 n: width of the Y coordinate (bits 23-16).

 B: number of bytes of color: 1 (grayscale), 2 (16-bit color), 3 (24-bit color) or 4 (30-bit color).

 A: address mode: 0 (X,Y), or 1 (consecutive).

 S: swap: 0 when swap is done, else 1.

Character Buffer

The Character Buffer’s unit of operation is a character A device can send ASCII character codes to the Character Buffer’s Avalon interface avalon_char_buffer_slave The Character Buffer handles the conversion of characters to

pixels, and sends them to the VGA Core via an Avalon Streaming Interface Upon initialization or reset, the Character Buffer sets all the characters to “space”, so no characters will be displayed This “clear screen”

operation can take up to 5000 clock cycles to finish In the Character Buffer, the resolution is defined by the number of characters per line and the number of lines per screen The Character Buffer currently supports only

one resolution per output device, where each character occupies an 8x8 VGA pixel group Therefore, 80

characters can be displayed per line with 60 lines, since the Character Buffer is streaming the pixel values to the VGA Core, which in turn has a resolution of 640x480 The Character Buffer currently supports only one color

option, which is that characters are drawn in white with a transparent background

The core stores the characters in its on-chip memory.

When the Character Buffer is instantiated in an SOPC Builder system, it is assigned a base address, as a

memory-mapped device Each character in the buffer then has a unique address in this addressable space The coordinate system of the Character Buffer is illustrated in Fig 6 As the figure indicates, each character location

is identified by an (x, y) coordinate, with (0, 0) being the top-left corner of the screen The address in the buffer

of each location is formed by combining the (x, y) coordinates as shown in Fig 7, and then adding this value

to the base address All data for the Character Buffer is character (8-bit) addressable The supported addressing

mode is called the X-Y mode

Fig 6.Character coordinate system.

Fig 7.X-Y address format.

The values of m and n are related to the VGA Core’s resolution as follows:

2

(log )

m  ceil X

2

(log )

n  ceil Y

where X and Y are the resolution in the X, Y directions, respectively

For example, for 80x60 resolution we have

2

(log 80) 7

m  ceil 

2

(log 60) 6

n  ceil 

and this resolution leads to the address format shown in Fig 8.

Fig 8.X-Y address format for the 80x60 resolution.

Device drivers control and communicate with the Character Buffer through two Avalon memory mapped interface, named avalon_char_control_slave and avalon_char_buffer_slave The avalon_char_buffer_slave interface has a one byte data width for ASCII characters and is addressed as described in the Character Buffer’s Address Format section above The avalon_char_control_slave interface consists of the two registers shown in Table 1.

The Control register provides the ability to clear the screen by using the R bit, which is bit 16 of this register.

The R bit remains set to 1 until all characters have been cleared, and then R is set to 0 The Resolution register,

which is read-only, provides two values: the number of characters per line, in bits 15-0, and the number of lines per screen, in bits 31-16.

2 Lab 4 - Part 1: Implementing a Nios II System

Using Quartus II and SOPC Builder to realize the required hardware as follows:

1 Use the DE2_TOP project or the previous lab as a starting point.

2 Use the SOPC Builder to generate the desired system, called nios_system, which comprises (steps

a to k are from lab 3):

a On-chip memory - RAM mode and 32 Kbytes in size (leave all other options at their default settings)

b SRAM/SSRAM Controller

c External Clocks for DE Board Peripherals [2]

i VGA clock

ii DRAM clock

d SDRAM Controller (Memories and Memory Controllers > SDRAM > SDRAM Controller)

i Select Custom from the Presets drop-down list Set the Data Width parameter to

16 bits and leave the default values for the rest

ii Do not select the option Include a functional memory model in the system testbench

iii Due to the clock skew problem, the Nios II processor may be unable to properly access the SDRAM chip The clock skew depends on physical characteristics of the DE2 board For proper operation of the SDRAM chip, it is necessary that its

clock signal, DRAM_CLK, leads the Nios II system clock, CLOCK_50, by 3

nanoseconds This can be accomplished by using the output from the External Clockscomponent created in step c

e Nios II/s processor with JTAG Debug Module Level 1

f An 8-bit PIO output circuit, which will be connected to green LEDs

g A 16-bit PIO output circuit, which will be connected to red LEDs

h A 3-bit PIO input circuit, which will be connected to KEY[3:1] Also, in the Input Options

tab select the following:

i Synchronously capture feature activated by the Falling edge for the Edge capture register

ii Generate IRQ interrupt on Edge

i JTAG UART - Located in the component section Interface Protocols > Serial; use the default settings

j Interval Timer - Located in Peripherals > Microcontroller Peripherals

i 125 ms Period

ii 32-bit Counter Size

iii Choose Custom from Presets drop down menu

iv Make sure to select/check Writable period, Readable snapshot, Start/Stop control bits

k A controller for the 16x2 character display (University Program > Audio & Video > 16x2 Character Display)

i Display Cursor: Both

l Audio/Video Configuration Core (University Program > Audio & Video >Audio and Video Config)

i Check “Auto Initialize Device(s)” box

m VGA Pixel Buffer (University Program > Audio & Video > Video Out > Pixel Buffer for VGA Display)

i DE2

ii VGA Connector

iii Use SRAM start address for both Buffer and Back Buffer Start Address

iv X-Y mode

v Width scaling factor: 2

vi Height scaling factor: 2 vii 16-bit RGB

viii Connect avalon_pixel_buffer_master to SRAM

n VGA Character Buffer (University Program > Audio & Video > Video Out > Character Buffer for VGA Display)

i VGA Connector

ii Check “Enable Transparancy” box

o Alpha Bending Core (University Program > Audio & Video > Video Out > Alpha Blending)

i Connect avalon_foreground_sink to Character Buffer’s avalon_char_source

ii Connect avalon_background_sink to Pixel Buffer’s avalon_pixel_buffer_source

p VGA controller (University Program > Audio & Video > Video Out > VGA)

i Connect Alpha Blending’s avalon_blended_source to VGA’s avalon_vga_sink.

ii DE2 iii VGA Connector

3 Change these names to something that is more meaningful in the context of this design

4 Generate the specified system

5 Instantiate the generated nios_system in the DE2_TOP project Connect the reset input of the nios_systemto the pushbutton KEY(0)

6 Compile the Quartus II project and configure the FPGA with your design

7 Document your design/debug/verification steps in your lab report

3 Lab 4 - Part 2: Drawing an Object/Text

1 Write a C program to

a create a black background screen,

b draw and fill a square with a different color,

c write “ECE 462 - Lab 4” on the screen

2 Demonstrate a working program

4 Lab 4 - Part 3: Controlling VGA and LCD displays

1 Write a C program to

a move the square (part 2) up when the up arrow is pressed

b move the square (part 2) down when the down arrow is pressed

c move the square (part 2) left when the left arrow is pressed

d move the square (part 2) right when the right arrow is pressed

e display “ECE 462 - lab 4” on the first line of the 16x2 LCD

f display “left”, “right”, “up” or “down” accordingly on the second line of the 16x2 LCD

2 Demonstrate a working program

Note:Moving a displayed object is an illusion created by showing the same object at different locations

on the screen To move an object on the screen we must display it at one position first, and then at another later on A simple way to achieve this is to draw an object at one position, and then erase it and draw it at another position

5 Lab 4 - Part 4: Graphic Animation

1 Write a C program to

a draw a 2x2 box at a pseudo-random location on the screen

b start moving the box diagonally if the “space” key is pressed The square should bounce off the top, bottom, left, and right edges of the screen The box stops if the “space” key is pressed again

2 Demonstrate a working program

Note: The key to animation is timing, because to realize animation it is necessary to move objects at regular time intervals The time intervals depend on the graphics controller This is because the controller

draws images onto a screen at regular time intervals The VGA controller redraws the screen every 1/60th

of a second Since the image on the screen cannot change more often than that, this will be the unit of time

To ensure that we draw on the screen only once every 1/60th of a second, we can use the VGA pixel buffer

to synchronize a program executing the nios_system with the redraw cycle of the VGA controller This is

accomplished by writing 1 to the Buffer register and waiting until bit 0 of the Status register in the VGA

pixel buffer becomes 0 This signifies that a 1/60th of a second has passed since the last time an image was drawn on the screen

6 Lab 4 - Part 5: Implementing a Video Game

1 Write a C program to

a implement a PONG game.

i Display the current point on the screen

ii Maintain and display the High game

iii Increase the speed after each checkpoint (i.e increase one speed step every 10 points)

2 Demonstrate a working program.

7 Lab 4 – Part 6: Write a Report for Lab 4

8 Reference

[1] Altera, “Video Out IP Cores for Altera DE Boards,” 2009 [2] Altera, “External Clocks for Altera DE Boards,” 2008