Predicting The Effect Of Task Jitter In Real Time Control Systems

Predicting the Effect of Task Jitter in Real Time Control Systems A thesis submitted in fulfilment of the requirements for the degree of Doctor of Philosophy LONG QUANG TRAN B.Eng.. 3

Predicting the Effect of Task Jitter in Real Time Control Systems

A thesis submitted in fulfilment of the requirements for the degree of Doctor of Philosophy

LONG QUANG TRAN

B.Eng (Computer Technology), HCMC University of Technology and Education, Vietnam

M.Eng (Electronic and Computer Engineering), RMIT University, Vietnam

School of Engineering College of Science, Engineering and Health

RMIT University

September 2019

I

Declaration

I certify that except where due acknowledgement has been made, the work is that of the author alone; the work has not been submitted previously, in whole or in part, to qualify for any other academic award; the content of the thesis is the result of work which has been carried out since the official commencement date of the approved research program; any editorial work, paid or unpaid, carried out by a third party is acknowledged; and, ethics procedures and guidelines have been followed

Long Quang Tran

20/09/2019

II

Acknowledgements

Special thanks to Dr Peter John Radcliffe, my senior supervisor and more than a mentor

It is always great for me to discuss and chat with him not only about my PhD but also life, family, politic, technology and so on I also learn many skills from PJ such as teaching skills, time management and leadership

Many thanks to my second supervisor, Dr Samuel Ippolito for his valuable advice to my PhD works Also, thanks to Prof Liuping Wang for her control theory experience, which

is vital to my PhD works

Thanks to Lina Le, who did a great job in helping me improve the grammar in this thesis Thanks to Mr Michael Manh, who is my second mentor, for his great supports to my living in Melbourne

Thanks to RMIT University and Vietnam International Cooperation Department for my PhD scholarships

Thanks to my wife and my mom for their love and supports that help me finish my PhD works

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Dedication

This thesis is dedicated to my dad who passed away in 2012 due to the esophageal cancer

IV

Table of contents

DECLARATION I ACKNOWLEDGEMENTS II DEDICATION III TABLE OF CONTENTS IV LIST OF FIGURES VII LIST OF TABLES X LIST OF ABBREVIATIONS XI

ABSTRACT 1

CHAPTER 1 INTRODUCTION 3

1.1 Problem statement 3

1.2 The state of the field 4

1.3 Motivation and objectives 5

1.4 Research questions 5

1.5 Overview of thesis structure 6

1.6 Contributions of this thesis 7

1.7 List of research outputs: 7

CHAPTER 2 LITERATURE SURVEY 9

2.1 Jitter and Latency 9

2.2 Effect of jitter on the performance of the system 14

2.3 Practical consequences of jitter 16

2.4 Jitter simulation 19

2.4.1 Modelling jitter as a disturbance 20

2.4.2 Building jitter analysis and predicting performance tools 20

2.4.3 Summary 21

2.5 Jitter measurement 21

2.5.1 Types of jitter measurement 21

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2.5.2 Jitter measurement unit 22

2.5.3 Measurement methodology - Internal time logger 22

2.5.4 Measurement methodology - External time logger 23

2.5.5 Summary 24

2.6 Methodology to cope with task jitter 25

2.6.1 Jitter minimisation 25

2.6.2 Robust controller to an uncertain jitter 28

2.6.3 Jitter compensation 28

2.7 Chapter summary 31

CHAPTER 3 A NOVEL APPROACH TO TASK JITTER SIMULATION IN DIGITAL CONTROL SYSTEM 33

3.1 A new approach to simulating task jitter 33

3.2 Method verification with a simple sine wave signal 36

3.2.1 MATLAB/Simulink 36

3.2.2 LTSpice 38

3.3 Hardware Application 1 – DC Motor Speed controller 39

3.3.1 Hardware 39

3.3.2 Design controller for motor speed application 40

3.3.3 Simulation with MATLAB and Simulink 41

3.3.4 Results and Discussion 44

3.4 Hardware Application 2 – Thermal controller 47

3.4.1 Hardware 47

3.4.2 Controller design 50

3.4.3 Results and discussion 53

3.5 Chapter summary 54

CHAPTER 4 EVALUATING THE EFFECT OF JITTER 56

4.1 Simulation and visualisation methodology 56

4.1.1 Background 56

4.1.2 Methodology 57

4.1.3 Summary 60

4.2 Case study on real hardware– DC motor speed controller 60

4.2.1 Introduction 60

4.2.2 System modelling 60

4.2.3 Pattern generator 61

4.2.4 Implementation on Hardware 62

4.2.5 Result and discussion 62

4.2.6 Summary 65

4.3 Analysis of jitter pattern and RMS jitter 66

VI

4.3.1 Introduction 66

4.3.2 System modelling 66

4.3.3 Pattern generators 67

4.3.4 Implementation 69

4.3.5 Result and discussion 69

4.3.6 Summary 74

4.4 Chapter summary 75

CHAPTER 5 MEASURE AND RECORD TASK JITTER 76

5.1 Methodology 76

5.2 Hardware + OS stressing 78

5.3 Task jitter measurement 79

5.4 Verification of the measurement tool 80

5.5 Measurement results 82

5.6 Using measurement results for a control system model 83

5.6.1 Control system model 83

5.6.2 Use sample time measured from hardware in simulation 85

5.6.3 The envelope of step responses 86

5.6.4 Boxplot for rise time and settling time 89

5.7 Chapter summary 90

CHAPTER 6 DISCUSSION AND CONCLUSIONS 92

6.1 Summary of conclusions 92

6.2 Development process to help real-time designer 94

6.3 Future research directions 94

APPENDICES 96

A Generic Simulink-based model 96

B Jitter generator from MATLAB script 97

C MATLAB example script for simulation with random jitter 98

D MATLAB example script of simulation with jitter measured from real-hardware 99 E MATLAB example script to Plot the envelope response 100

REFERENCES 101

VII

List of figures

Fig 2-1 Jitter with Gaussian distribution [19] 10

Fig 2-2 Jitter characterisation by Nahas [25] 12

Fig 2-3 Illustration of jitter in different calls of a periodic task [28] (𝑟: release time, 𝑠: start time and 𝑓: finish time) 12

Fig 2-4 Jitter characterisation by Marti et al [24] 13

Fig 2-5 Inverted pendulum system responses [24] 15

Fig 2-6: DAC output waveforms with ideal sampling clock (without jitter) and actual sampling clock (with jitter)[32] 16

Fig 2-7 Typical design cycle of a real-time control system[34] 17

Fig 2-8 Design process for integrated real-time control system[35] 18

Fig 2-9 PRESTO design methodology[40] 19

Fig 2-10 Cycle-to-cycle jitter (Jcc) [26] 22

Fig 2-11: Communication jitter [23] 26

Fig 2-12: Calculated speed in the presence of communication jitter [23] 27

Fig 2-13: Speed with(solid line) and without(dashed line) median filter [23] 27

Fig 2-14: Control loop with add-on delay compensator [60] 29

Fig 2-15: Cost comparison between uncompensated and compensated jitter system [60] 29

Fig 2-16: Comparison between systems with/without jitter compensation [24] 30

Fig 3-1: A simple motor controller model 34

Fig.3-2: An example using of digital controller C(z) 35

Fig 3-3: Digital controller C(z) in state-space form 35

Fig 3-4: Diagram of the alternative delay block 36

Fig 3-5 Block diagram of the verification method using Simulink 37

Fig 3-6: Comparison of outputs from scope1(purple dashed line) and scope2(yellow line) 37

Fig 3-7 alternative 𝑧 − 1 Variable delay implemented in LTSpice 38

Fig 3-8 Output waveform in LTSpice model 39

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Fig 3-9 Hardware implementation block diagram 40

Fig 3-10 Motor speed PI controller in Simulink 42

Fig 3-11 Motor speed controller model with added hardware limitation blocks 43

Fig 3-12 Motor speed controller model with jitterred sampling clock 43

Fig 3-13 Inside the introduced PI controller block diagram 44

Fig 3-14 Comparison between 40% jitter and non-jitter sampling clock Left figure simulation, right figure experiment 46

Fig 3-15 Comparison between simulation and experiment Upper figures jitter pattern 1 Bottom figures: Jitter Pattern 2 47

Fig 3-16 Sensor and heats source contact 48

Fig 3-17 Surface temperature rise curve [65] 48

Fig 3-18 Thermal Controller Block Diagram 49

Fig 3-19 Connection diagram 49

Fig 3-20 Open-loop step response 50

Fig 3-21 Closed loop system with PI controller 51

Fig 3-22 PI controller with added hardware constraints 52

Fig 3-23 Comparison between simulation and experiment - Random jitter 53

Fig 3-24 Comparison between simulation and experiment – Problematic jitter 53

Fig 4-1: Example of an envelope of output responses to a step input 57

Fig 4-2 Diagram to simulate jitters patterns into Simulink 59

Fig 4-3 Flow chart diagram for running multiple simulations 59

Fig 4-4 Diagram to simulate jitters patterns into Simulink for the DC motor model 61

Fig 4-5 System response envelope under different patterns 63

Fig 4-6 Comparison between system response envelopes on real hardware and simulation 65

Fig 4-7 Diagram to embed jitter patterns into the Simulink model of 2nd order controller 66

Fig 4-8 Output step response envelopes of a second-order system with different types of jitters 70

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Fig 4-9 Settling time histograms of a second-order system with different types of jitters

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Fig 4-10 Overshoot peak histograms 72

Fig 5-1: Method block diagram 77

Fig 5-2 Measure task jitter on hardware platforms 79

Fig 5-3 Measurement tool verification with Analog Device 2 80

Fig 5-4 Histogram of recorded sampling intervals, the target is 8.3 milliseconds Left - BeagleBone Right – Orange Pi 83

Fig 5-5 Control system block diagram 84

Fig 5-6 The control feedback transfer function diagram 84

Fig 5-7 The system closed-loop step response 85

Fig 5-8 𝐺𝐹𝐵𝑧 transfer function under state-space variable form 86

Fig 5-9 𝐺𝐹𝐵(𝑧) transfer function under the state-space variable form with alter 𝑧 − 1 delay module 86

Fig 5-10 Pattern selection from recorded sample intervals 87

Fig 5-11 Envelope responses from recorded sampling intervals of BeagleBone(left side) and Orange Pi (right side) 88

Fig 5-12 Boxplot for Rise time and Settle time from different hardware configurations 90

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List of tables

Table 3.1 Motor parameters 40

Table 3.2 PI Controller parameters 41

Table 3.3 List of thermal controller components 50

Table 4.1 Statistic data at the overshoot point from different jitter pattern distribution but same RMS value=0.062 71

Table 4.2 Chi-square test fit in pair 73

Table 4.3 Chi-square test fit with normal distribution 73

Table 5.1 List of Stress-ng terminologies 77

Table 5.2 Specification of devices under test 78

Table 5.3 Statistic result of the Arduino for measurement of several frequency signal 81

XI

List of abbreviations

ADC analog-to-digital converter

CAN Controller Area Network

CPU central processing unit

DAC digital-analogue converter

DC direct current

DVS dynamic voltage scaling

FPGA Field Programmable Gate Arrays

GA Simple Genetic Algorithm

GUI graphical user interface

IO input-output

OS Operating system PDF probability density function

PI proportional-integral

PID proportional–integral–derivative

PWM pulse width modulation QNX a commercial Unix-like real-time operating system

RTOS Real-time operating system TTC time triggered cooperative ZOH zero-order-hold

1

Abstract

Designing a real-time embedded control system requires designers to work through many steps, including simulation and full hardware implementation Ideally, simulation can be used to quickly and cheaply check and optimise the system, but this requires simulation to match the hardware quite closely Currently, there is no easy way to simulate task jitter, thus, a simulation is not available for such systems To be safe, designers tend to choose expensive, over engineered hardware solutions in order to guarantee adequate system performance, but if cost is an issue, cheaper systems should be evaluated Current hardware testing methods that adequately evaluate task jitter take considerable time and effort, and may result in a rework cycle with a new controller if cheaper options prove inadequate This thesis provides a novel solution that overcomes these problems and will help designers select appropriate hardware + operating system(OS) platforms during the simulation phase

The first research question is to find an appropriate way to capture task jitter from real controllers This resulted in a low-cost tool and the paper titled “Simulation is essential for embedded control systems with task jitter” [1]

The next research question addresses the problem of simulating a control system using the task jitter information A novel method to model task jitter in MATLAB is developed that creates a variable z−1 delay This newly developed method has been verified by two control experiments: A motor speed controller and thermal controller The experimental results show that simulation and hardware are closely matched given the same task jitter and has been published in two papers: “A new approach to clock jitter simulation in digital control system” [2] and “Designing greener real-time controllers” [3]

Some extended findings of the novel work have also been incorporated in other publications The paper “A Low Budget Take-home Control Engineering Laboratory for Undergraduate” [4] shows the benefit of the developed method by helping students

2

understand the effects of hardware limitations in a control system at the simulation phase Another finding is presented in the paper “Predicting the effect of task jitter in digital control systems” [5], which tests different types of task jitter and concludes that root-mean-square(RMS) value is sometimes a good predictor of the system performance

A further research question aims to determine if simulation can provide insights that the testing of real hardware cannot provide The paper “Simulation is essential for embedded control systems with task jitter” records task jitter from two real hardware platforms and concludes that a real control system subject to task jitter might randomly and very occasionally show extreme behaviour which may be outside acceptable limits This paper shows that the recorded jitter does not follow a classic Gaussian or uniform probability density function (PDF) Cases where the acceptable performance limits are exceeded would take a very long time to find using testing on real hardware but can be identified quickly using simulation