Introduction to VLSI design

Introduction to VLSI Design V O T U A N M I N H Faculty of Electronics and Telecommunication Engineering University of Science and Technology The University of Danang Design of Analog, Mixed Signal Integrated Circuit 1 Thông tin chung  Giảng viên Võ Tuấn Minh  Email vtminhdut udn vn  Giáo trình  Slides bài giảng  Tham khảo  Behzad Razavi, Design of Analog CMOS Integrated Circuits, McGraw Hill  Behzad Razavi, Fundamentals of Microelectronics, Wiley  Phân bố điểm  Điểm danh + Bài tập 30.

Thông tin chung

 Giảng viên: Võ Tuấn Minh

Chủ đề

3

 Giới thiệu Thiết kế vi mạch & Đặc tính của

MOSFET

 Mạch khuếch đại đơn

 Mạch khuếch đại vi sai

 Mạch gương dòng

 Bộ chuyển đổi tương tự/số

 Vòng khóa pha

Digital Signals

 Digital Signals – have only two states

 For digital computers, we refer to binary states, 0 and 1

 Sampled at discrete points in time and discrete values

(amplitude) => signal is quantized, so it is an

approximation

Examples

 Light switch can be either on or off

 Door to a room is either open or closed

6

Analog and Digital Signal

7

http://www.rpi.edu/dept/phys/ScIT/InformationTransfer/sigtransfer/images/analogdigital.gif

Why Analog?

 Physical Signals in Nature

 Super High Frequency Transmitter

 Power Supply, Power Storage

 Circuit Protection

 ESD (ElectroStatic Discharge)

Analog circuit is indispensable piece!

9

 Small signal analysis

and mixed signal circuit simulations

systematic layout, symmetry requirements, common centroid &

inter-digitating techniques, off-set cancellation, noise prevention & floor planning of your design.

Must-have Knowledge

10

Some VLSI Manufacturers

 Integrated Device Manufacturers (IDM)

 Intel, Fujitsu, Samsung, Toshiba…

 Foundry, only manufacture

 TSMC, MediaTek…

 Design and sale of hardware devices and semiconductor

chips while outsourcing the fabrication of the devices to a

specialized manufacturer called a semiconductor foundry

 Qualcomm, Texas Instrument, AMD, Nvidia, Marvell, Apple…

12

 Transistors are built on a silicon substrate

 Silicon is a Group IV material

 Forms crystal lattice with bonds to four neighbors

 Silicon is a semiconductor

 Pure silicon has no free carriers and conducts poorly

 Adding dopants increases the conductivity

 Group V: extra electron (n-type)

 Group III: missing electron, called hole (p-type)

Dopants

15

As Si Si

Si Si Si

Si Si Si

B Si Si

Si Si Si

Si Si Si

+

-+ -

Tiếp giáp pn ở điều kiện cân bằng nhiệt

 Dòng khuếch tán nhỏ: chỉ ít hạt mang điện đủ năng lượng

 Dòng trôi nhỏ: hạt mang điện thiểu số (minority) rất ít và xa

 Dòng trôi độc lập với lớp ngăn!

 Dòng khuếch tán là hàm phụ thuộc mạnh (lũy thừa) lớp ngăn

- -

- - - - -

-+ + + + + + + + + + + + +

Reverse Bias

 Reverse Bias causes an increases barrier to diffusion

 Diffusion current is reduced exponentially

 Drift current does not change

 Net result: Small reverse current

-

- -

-+ + + + + +

−

17

Forward Bias

 Forward bias causes an exponential increase in the number of carriers with sufficient energy to

penetrate barrier

 Diffusion current increases exponentially

 Drift current does not change

 Net result: Large forward current

-

- -

-+ + + + + + +

+

−

18

Device Structure

20

 Four-terminal device: gate (G), source (S), drain (D) and body (B)

 The device size (channel region) is specified by width (W) and length (L)

 Two kinds of MOSFETs: n-channel (NMOS) and p-channel (PMOS)

 Source and drain terminals are specified by the operation voltage

 This structure is different with the structure of power MOSFET

Device Structure

21

 Charge carriers are electrons in NMOS devices, and holes in PMOS devices

 Electrons have a higher mobility than holes So, NMOS

devices are faster than PMOS devices

 Actual length of the channel (Leff) is less than the length of

gate (Ldrawn)

 Leff = Ldrawn - 2LD

 LD due to side diffusion

 Poly-silicon used instead

of Metal for fabrication

reasons

Device Structure

22

 CMOS technology employs both PMOS and NMOS

 n-wells allow both NMOS and PMOS devices to reside on the same piece of die

 B of NMOS is connected to the most (-) voltage, and B of PMOS is connected to the most (+) voltage

 To prevent effect of Schottky diode, use p+ and n+ for B

23

 Symbols in (b) are the most widely used in analog circuits

 Symbols in (c) are used in digital circuits

Operation with Zero Gate Voltage

25

 The MOS structure form a

parallel plate-plate capacitor

with gate oxide layer in the

middle

 Two pn junctions (S/B & D/B) are connected as

back-to-back diodes

 The source and drain terminals are isolated by two

depletion regions without conducting current

Creating a Channel for Current Flow

26

 Positive charges accumulate in gate as a positive voltage

applies to gate electrode

 The electric field forms a depletion region by pushing holes

in p-type substrate away from the surface

 Electrons start to accumulate on the substrate surface as

gate voltage exceeds a threshold voltage V TH

 The induced n forms a channel region thus for current

flow from drain to source

 The channel is created by inverting the substrate surface

from p-type to n-type -> inversion layer

 The field controls the amount of charge in the channel and determines the channel conductivity

Applying a Small Drain Voltage

27

 Free electrons travel from source to drain through the

induced n-channel due to a small VDS

 The resulting current

ID flows from drain to

source (opposite to the

direction of the flow of

negative charge)

Applying a Small Drain Voltage

 The electron charge in the channel due to

the overdrive voltage: |Q| = C ox WLV ov

 Gate oxide capacitance C ox is defined

as capacitance per unit area

 MOSFET can be approximated as a linear resistor in this region

Operation as Increasing Drain Voltage

29

 As V DS increases, the voltage along the channel increases

from 0 to V DS , and the voltage between the gate and the

points along the channel decreases from V GS at the source

end to (V GS – V DS) at the drain end

 Since the inversion layer depends on the voltage difference across the MOS structure,

increasing V DS will result in a

tapered channel

 The resistance increases due

to tapered channel and the

ID /VDS curve does not

continue as a straight line

Operation as Increasing Drain Voltage

30

 At the point V DS,sat = V GS – V TH, the channel is pinched off

at the drain side

 Increasing V DS beyond this value has little effect on the

channel shape and I D saturates at this value

 If V GS > V TH then the channel is induced:

Derivation of I/V Relationship

33

 The drain current I D is calculated by

𝐼𝐷 = 𝑄𝐷 𝑥 ∙ 𝑣(𝑥)

 Q D (x): mobile charge density per meter

 v(x): velocity of the charge

Derivation of I/V Relationship

34

𝐼𝐷 = 𝜇𝑛𝑊𝐶𝑜𝑥 𝑉𝐺𝑆 − 𝑉𝑇𝐻 − 𝑉 𝑥 𝑑𝑉 𝑥

𝑑𝑥

න0

NMOS I/V Characteristics

NMOS I/V Characteristics

 When is the device on?

 What is the region of operation if the device is on?

 Sketch the on-resistance Ron of transistor M1 as a

function of VG

 The drain current of the MOSFET in saturation region

is ideally a function of gate-overdrive voltage (effective

voltage) In reality, it is also a function of VDS

 It makes sense to define a figure of merit that indicates how well the device converts the voltage to current

 Which current are we talking about?

 What voltage is in the designer’s control?

 What is this figure of merit?

 Example: Plot the transconductance of the following circuit

39

41

 Transconductance in saturation is also expressed as:

𝒈𝒎 = 𝝁𝒏𝑪ox 𝑾𝑳 𝑽ov = 𝟐𝝁𝒏𝑪ox 𝑾𝑳 𝑰𝐃 = 𝟐𝑰𝐃

𝑽ov

W/L: h ằng Vov: hằng ID: hằng

Channel Length Modulation

43

 The channel pinch-off point moves

slightly away from D as V DS > V DS,sat

 The effective channel length (Leff)

reduces with V DS

 The length accounted for conductance

in the channel is replaced by Leff

44

Channel Length Modulation

Channel Length Modulation

46

 Changing the length of the device from L1 to 2L1 will flatten

the I D /V DS curves (slope will be divided by two in triode and

by four in saturation)

 Increasing L will make a transistor a better current source,

while degrading its current capability

 Increasing W will improve the current capability

Finite Output Resistance

 Due to the dependence of I D on V DS, MOS FET shows finite output

resistance in saturation region

Body Effect

48

 The BS and BD junction should be reverse biased for the device to function properly

connected to the most negative voltage

 The depletion region widens in BS and BD junctions

and under the channel as VSB increases

in the depletion region under the channel

 The body effect can cause considerable degradation

in circuit performance

Body Effect

49

 Threshold voltage:

𝑉𝑇𝐻 = 𝑉𝑇𝐻0 + 𝛾[ 2𝜙f + 𝑉𝑆𝐵 − 2𝜙f]where, 𝛾 =

2𝑞𝑁A𝜀Si

𝐶𝑜𝑥 and 𝜙f = 𝑘𝑇

𝑞 ln 𝑁A

𝑛i

Body Effect

50

transistor is in the active region) Plot the difference

of (Vin – Vout) with and without body effect when Vout

increases

Body Effect

51

 If body effect is ignored, V TH will be constant, I1 will only

depend on V GS1 = Vin – Vout Since I1 is constant, Vin – Vout

remains constant

 In general, I1 depends on V GS1 – V TH = Vin – Vout – V TH (with

body effect, V TH is not constant) Since I1 is constant

 Vin – Vout – V TH = C = Const => Vin – Vout = V TH + C

 As Vout increases, V SB1 increases, V TH increases and Vin - Vout

increases

 Depletion Capacitance: 𝐶2 = 𝑊𝐿 𝑞𝜀Si𝑁Sub/(4Φ F )

 Overlap Capacitance: 𝐶3 = 𝐶4 = 𝑊𝐶𝑜𝑣 = 𝑊𝐿D𝐶𝑜𝑥 + 𝐶fringer

 Junction Capacitance: 𝐶5 = 𝐶6 = 𝑊𝐸𝐶𝑗 + 𝑊 + 2𝐸 𝐶𝑗𝑠𝑤

E

Device Capacitances

57

 In Triode:

 The channel isolates G from the substrate Moreover, change

of V G draws equal amounts of charge from S and D Thus, C1 is

equally divided between C GS and C GD , and, C2 is equally divided

Device Capacitances

58

 In Saturation:

 Equivalent capacitance between S and G is approximately

(2/3)C1 Equivalent capacitance between S and B is

Small-Signal Models

60

 Small-signal model is an approximation of the large-signal model around the operation point

 In analog, most transistors are biased in saturation region

 In general, I D is a function of V GS , V DS and V BS

Body Effect

Small-Signal Models

 Complete small signal model makes the intuitive (qualitative) analysis of even a few-transistor circuit difficult!

 Typically, CAD tools are used for accurate circuit analysis

 For intuitive analysis, try to find the simplest model that can represent the role of each transistor with reasonable accuracy

62

PMOS Small-Signal Model

63

64

 Static power dissipation in CMOS is almost zero

 Three operation regions in CMOS