High Gain High Efficiency Doherty Amplifiers with Optimized Driver Stages44890

High Gain High Efficiency Doherty Amplifiers with Optimized Driver Stages Duy P.. 2SISLAB, VNU University of Engineering and Technology, Hanoi, Vietnam Abstract — In this paper, we pres

High Gain High Efficiency Doherty Amplifiers with Optimized Driver

Stages

Duy P Nguyen1, Xuan-Tu Tran2, Phat T Nguyen1, Nguyen L K Nguyen1, and Anh-Vu Pham1

Email: dypnguyen@ucdavis.edu; tutx@vnu.edu.vn; ptng@ucdavis.edu; nlknguyen@ucdavis.edu; ahpham@ucdavis.edu

1Department of Electrical and Computer Engineering, University of California, Davis, CA, USA

2SISLAB, VNU University of Engineering and Technology, Hanoi, Vietnam

Abstract — In this paper, we present two different approaches

to design a driver for high gain Doherty power amplifiers (DPAs):

single driver and dual-driver topologies Detailed analysis and

quantitative comparison between the two approaches are

proposed In particular, the single driver topology is preferred

when the output Doherty stage has a reasonable gain On the other

hand, when the output stage has low gain, the dual driver

approach is required to prevent significant efficiency reduction

Two DPA circuits at two different frequency ranges have been

fabricated in a 0.15-μm Gallium Arsenide (GaAs) process to verify

the concept The single driver DPA at 10 GHz achieves at a

measured gain of 19.2 dB and the maximum power of 27 dBm

The peak power added efficiency (PAE) and PAE at 6-dB power

back-off (PBO) are 43% and 32%, respectively On the other

hand, the dual driver DPA at 28 GHz exhibits 15 dB of gain, 28.2

dBm output power with an associated peak PAE of 37% To the

best of the authors’ knowledge, our DPA prototypes achieve the

highest gain of all reported DPAs at similar frequency ranges

Keywords— Doherty Power Amplifier, Gallium Arsenide, High

gain, Ka-band, MMIC, Optimized driver, X-band

I INTRODUCTION oherty amplifier is among the most critical components in

high peak to average power ratio (PAPR) wireless system

since it can dynamically change the load impedance and

maintains high efficiency at back-off levels [1] However, the

Doherty power amplifiers (DPA) typically have low gain due

to the input power splitter and output combining network losses

Most X-band, Ku-band DPAs have lower than 17 dB of gain

[2]-[5] and K-band, Ka-band DPAs have lower than 15 dB of

gain [6]-[10] The low gain ultimately results in low power

added efficiency and less usability in practical systems To be

effectively deployed in a system, a power amplifier is desired

to have more than 15 dB gain Furthermore, if the power

amplifier has high gain, the effect of previous stages on the

system efficiency and linearity can be minimized

In microwave/millimeter-wave monolithic integrated

circuit (MMIC) processes, it is preferable to have a multi-stage

high gain fully integrated Doherty amplifier since all the

mismatch effects, overall efficiency and size can be carefully

taken into account in one design [6], [11] Nevertheless, very

few analyses on DPA driver design have been reported to date

In [6], an optimized driver has been demonstrated in a K-band

DPA However, only 12.5 dB of gain is achieved at 24 GHz In

this paper, we present a novel approach to design optimized

drivers for Doherty amplifier Specifically, the driver is not

only chosen based on the gain requirement, but it can also be

optimally designed based on the output stage efficiency and

(a)

(b) Fig 1 High gain Doherty amplifier (a) single driver topology and (b) dual driver topology

gain To verify the proposed concept, two Doherty amplifiers

at 10 GHz and 28 GHz are fabricated in a 0.15-μm enhancement mode Gallium Arsenide (GaAs) process In each amplifier, the output stage has different characteristics, leading

to different driver topologies, respectively Experimental results show that with optimized driver stage for each case, both DPAs can achieve high gain and high efficiency while still maintaining compact chip size

II OPTIMIZED DRIVER FOR HIGH GAIN DPAS The two topologies to improve the Doherty amplifier gain are presented in Fig 1 In the first approach (Fig 1a), only one transistor is placed in front of the power splitter to boost the overall gain The transistor is matched to 50 Ω as the power splitter is typically a 50 Ω device The approach has an advantage of simple and consumes less die area However, the efficiency will be significantly degraded if the driver is not optimally chosen On the other hand, in the second solution, shown in Fig 1(b), in which two transistors are placed in front

of each amplifier, the DPA exhibits higher efficiency Nonetheless, the second approach poses a complicated design,

D

layout and control process Furthermore, the chip size would

be larger and requires more bias voltages

In both approaches, the driver needs to be carefully designed

to achieve the highest gain while maintaining good efficiency

The design procedure for each topology will be discussed in

the following sub-sections

A Single driver approach

In the single driver approach, the DPA and the driver can

be designed independently since each amplifier is matched to

50 Ω by employing separate matching networks However, the

driver performance can have a significant effect on the overall

efficiency, especially at back-off levels In a conventional

two-stage amplifier, the driver can be simply chosen to provide

enough power to drive the output stage and boost the overall

gain On the other hand, in a Doherty amplifier, designing the

driver stage requires much more attention so that the DPA can

maintain high power added efficiency at both maximum and

back-off levels

In practical circuits, due to the imperfect load modulation,

the low current of the class-C peaking amplifier, and gain

compression, the gain and efficiency of the DPA are different

from the ideal values in conventional analysis Fig 2 depicts

the difference in drain efficiency (η) and gain between a real

DPA and an ideal DPA At maximum drive level, the efficiency

is αη, and gain is γG At 6-dB PBO, the efficiency is βη Note

that η and G is the maximum drain efficiency and gain in the

ideal analysis, and α, β, and γ are the scaling factors and always

smaller than 1

Let’s denote the gain and drain efficiency of the Doherty

output stage are GDPA and ηDPA, and those of the driver stage

are GD and ηD, respectively The overall amplifier PAE at 6-dB

PBO can be given as:

1

As previously mentioned, at maximum drive level, due to

the class-C low current, the peaking transistor can only

generate δPout (δ < 1 and Pout is the maximum output power of

the carrier transistor) while consuming the same amount of dc

power Pdc Therefore, the DPA efficiency at maximum level

can be expressed as:

1

With that assumption, the PAE at maximum level will be:

1

B Dual driver approach

In the second approach, two transistors are deployed to

drive the carrier amplifier and peaking amplifier separately

The inter-stage matchings are required to match the input of the

power stage and the output of the driver stage Additionally,

the circuit needs more dc bias voltages to control two

independent drivers Both the driver stage and output stage of

the carrier amplifier are biased in class-AB, and those of the

peaking amplifier are biased in class-C However, the four

Fig 2 Non-ideal characteristic of a Doherty amplifier

Fig 3 Overall PAE as a function of driver stage efficiency at three different output stage gain levels (solid line: dual-driver DPA; dotted line with symbols: single-driver DPA)

biases are independently controlled to optimize the performance If we assume that the carrier and peaking amplifier employ identical driver stages and consume an equal amount of dc power, the using similar analysis, the overall PAE

of the dual driver approach at 6-dB PBO and maximum drive level can be expressed as:

1

1

It can be seen from (3) and (5), at maximum drive level, the two topologies give the same overall PAE On the other hand,

at 6-dB PBO, from (1) and (4), the dual driver approach always gives higher PAE than the single driver does due to an additional factor of 2 in the denominator of the second component However, the analysis points out that the PAE-6dB difference between the two approaches depends on GDPA, ηD, and β Let’s assume the DPA output stage efficiency

ηDPA = 45%, driver gain is 10 dB, and β = 0.9 (the values are deducted from simulations of a single stage Doherty amplifier

at 10 GHz using a 0.15-μm enhancement mode GaAs process) Fig 3 illustrates the overall PAE at 6-dB PBO as a function of driver efficiency at three different gain levels

The overall PAE is reduced when either the driver efficiency or the output stage gain drops Moreover, when the output stage has high gain, the driver efficiency has minimal

effect on the overall PAE, thus, the performance is strongly

determined by the output Doherty stage gain and PAE As a

result, if the output stage’s gain is large enough, the difference

in PAE between the two approaches is very minimal (only

around 1%) Therefore, the single driver topology can be

preferably deployed due to its simplicity and compactness On

the contrary, when the gain of the output stage is lower than

10 dB, the difference between the two topologies can be

noticeable In this case, the dual driver topology should be used

to avoid significant efficiency degradation

III DPA DESIGN AND VERIFICATION

(a)

(b) Fig 4 (a) Single driver 10 GHz DPA and (b) Dual driver 28 GHz DPA

(photo size is not for scale)

To verify the concept, two Doherty amplifiers at 10 GHz and

28 GHz are fabricated in a 0.15-μm GaAs process The chip

photos of two DPAs are shown in Fig 4 The first DPA at

10 GHz employs a single driver while the 28 GHz DPA utilizes

the dual driver topology The two different topologies are

chosen for the two DPAs since the 10 GHz output stage can

offer much higher gain than the 28 GHz output stage does By

employing the single driver topology, the total chip size of the

10 GHz DPA is smaller, which is only 3.3 mm x 1.2 mm

(0.0044λ2) as compared to 2.9 mm x 1.7 mm (0.043λ2) of the

28 GHz DPA (note that the 10 GHz DPA is much smaller in

terms of wavelength) Furthermore, single driver topology

requires only three gate bias voltages while still maintains high

overall PAE at 6-dB PBO On the other hand, because the

transistors have limited gain at Ka-band, the dual driver

topology must be used in the 28 GHz DPA to minimize the

effect of the driver’s PAE on the overall PAE It is also worth

noting that the 28 GHz DPA employs stacked-FET cells at the

output stage to improve the output power [12], and the two

DPAs can achieve similar power levels

BIAS CONDITION OF THE TWO PROPOSED DPAS

10 GHz Single

driver DPA

Main 4 V 0.35 V

Peaking 4 V 0.12 V

28 GHz Dual

driver DPA

Main 8 V 0.4 V 4 V 0.45 V

Peaking 8 V 0.05 V 4 V 0.05 V

(a)

(b) Fig 5 Measured small signal performance of (a) the 10 GHz single driver DPA, and (b) the 28 GHz dual driver DPA

(a)

(b) Fig 6 Measured output power versus gain and power added efficiency of (a) the 10 GHz single driver DPA, and (b) the 28 GHz dual driver DPA Fig 5 presents the measured small signals of the two DPAs

at the bias condition depicted in Table I The 10 GHz single driver DPA achieves 19.2 dB gain at 10 GHz and the 3-dB bandwidth covers from 8.75 to 11 GHz The 28 GHz has a measured gain of 14.3 dB at 28 GHz and maintains higher than

11 dB from 25.5 to 29.5 GHz According to simulation, the

output stage of the 28 GHz DPA can only provide 6.5 dB gain

while the output stage of the 10 GHz DPA can achieve up to

11 dB gain Therefore, based on our proposed analysis, the

single driver approach is only suitable for the 10 GHz amplifier

Fig 6 presents the measured PAE and gain of the DPAs at

10 GHz and 28 GHz, respectively The single driver DPA

achieves a peak PAE of 43% at 26.8 dBm output power and

32.5% PAE at 6-dB power back-off In this design, the driver

transistor is carefully chosen so that the driver stage starts to

have soft compression at the power level equivalent to around

3-dB power back-off of the DPA As a result, the driver can

still maintain high efficiency at 6-dB PBO at the cost of heavier

DPA gain compression From Fig 6(a), the DPA reaches its

peak PAE at 3.5 dB gain compression According to Fig 6(b),

in the 28 GHz DPA, the peak PAE of 37% is measured at

28.2 dBm output power which is also the 1-dB gain

compression point Utilizing the dual driver topology, the DPA

exhibits a PAE of 27% at 6-dB PBO without scarifying the

power gain flatness

Fig 7 presents the measured adjacent channel power ratio

(ACPR) of the two prototypes Without digital pre-distortion

(DPD), the 28 GHz dual driver DPA exhibits better linearity

than the single driver DPA since the dual driver has much less

gain compression However, with DPD, the ACPR of the

10 GHz DPA is lower and reaches almost -50 dBc This can be

explained by the fact that the DPD loop works much more

efficient at 10 GHz as compared to 28 GHz

(a)

(b) Figure 7: Measured ACPR with and without digital pre-distortion (DPD) of

the: (a) 10 GHz single driver DPA and (b) 28 GHz dual driver DPA

Table II summarizes the performance of the two prototypes

and compares with other state-of-the-art DPAs reported at

similar frequencies Using optimized drivers for each design,

our PAs achieve the highest gain while still maintaining high

PAE at 6-dB PBO

IV CONCLUSION

In this paper, detailed analysis and numerical comparison between two major approaches in implementing driver stages for DPAs have been demonstrated When the output stage has reasonable gain, a single driver is preferred since it reduces the chip size and complexity with only a small reduction in PAE

On the other hand, when the output stage provides low gain, the dual driver topology is required to prevent significant PAE drop Two DPA prototypes at 10 GHz and 28 GHz are fabricated and measured to verify the proposed concept To the best of the authors’ knowledge, both fabricated prototypes achieve the highest gain when compared to other reported DPAs at similar frequency ranges

TABLEII

COMPARISON TO OTHER HIGH-FREQUENCY DPAS

Ref (GHz)Freq Power (dBm) Gain (dB) PAE(%) peak PAE6-dB

PBO (%) Chip size (mm 2 )

[2] 10 36 9.2 47 31 8.74 [3] 9.5 29 7.2 37 33.5 7.74

(*) GaN technology; (†) Matching networks on PCB

REFERENCES [1] D P Nguyen, B L Pham, and A Pham, "A Compact Ka-Band Integrated Doherty Amplifier With Reconfigurable Input Network,"

IEEE Trans Microw Theory Techn., vol 67, no 1, pp 205-215, 2019

[2] M Coffey, P MomenRoodaki, A Zai, and Z Popovic, "A 4.2-W 10-GHz GaN MMIC Doherty Power Amplifier," in Proc IEEE Compound Semiconductor Integr Circuit Symp (CSICS), 2015, pp 1-4

[3] P Colantonio et al., "Increasing Doherty Amplifier Average Efficiency

Exploiting Device Knee Voltage Behavior," IEEE Trans Microw

Theory Techn., vol 59, no 9, pp 2295-2305, 2011

[4] S Y Lee et al., "Linear X-band GaN HEMT transformer-based Doherty power amplifier," Electronics Lett., vol 52, no 15, pp 1342-1343, 2016 [5] A N Stameroff et al., "Wide-Bandwidth Power-Combining and Inverse Class-F GaN Power Amplifier at X-Band," IEEE Trans Microw Theory

Techn., vol 61, no 3, pp 1291-1300, 2013

[6] R Quaglia, V Camarchia, T Jiang, M Pirola, S D Guerrieri, and B Loran, "K-Band GaAs MMIC Doherty Power Amplifier for Microwave

Radio With Optimized Driver," IEEE Trans Microw Theory Techn., vol

62, no 11, pp 2518-2525, 2014

[7] D P Nguyen et al., "A compact 29% PAE at 6 dB power back-off

E-mode GaAs pHEMT MMIC Doherty power amplifier at Ka-band," in

IEEE MTT-S Int Microw Symp Dig., 2017, pp 1683-1686

[8] C F Campbell et al., “A K-band 5 W Doherty amplifier MMIC utilizing 0.15 μm GaN on SiC HEMT technology,” in Proc IEEE Compound

Semiconductor Integr Circuit Symp (CSICS), Oct 2012, pp 1–4

[9] D P Nguyen, J Curtis, and A V Pham, "A Doherty Amplifier With

Modified Load Modulation Scheme Based on Load-pull Data," IEEE

Trans Microw Theory Techn., vol 66, no 1, pp 227-236, 2018

[10] D P Nguyen, T Pham, and A Pham, "A 28-GHz Symmetrical Doherty

Power Amplifier Using Stacked-FET Cells," IEEE Trans Microw

Theory Techn., vol 66, no 6, pp 2628-2637, 2018

[11] A Keerti et al., "RF Characterization of SiGe HBT Power Amplifiers Under Load Mismatch," IEEE Trans Microw Theory Techn., vol 55, no

2, pp 207-214, 2007

[12] D P Nguyen et al., "A Ka-band asymmetrical stacked-FET MMIC Doherty power amplifier," in IEEE Radio Freq Integr Circuits Symp

(RFIC), 2017, pp 398-401