Thumb Instructions ARM DDI 0100E Copyright © 1996-2000 ARM Limited. All rights reserved. A7-87 Notes Data abort For details of the effects of the instruction if a data abort occurs, see Effects of data-aborted instructions on page A2-17. Alignment If the memory address is not word-aligned and no data abort occurs, the value written to memory is UNPREDICTABLE. If an implementation includes a System Control coprocessor (see Chapter B2 The System Control Coprocessor) and alignment checking is enabled, an address with bits[1:0] != 0b00 causes an alignment exception (a type of data abort). Equivalent ARM syntax and encoding STR <Rd>, [<Rn>, #<immed_5> * 4] 31302928272625242322212019 1615 1211109876 210 111001011000 Rn Rd 00000 immed_5 00 Please purchase PDF Split-Merge on www.verypdf.com to remove this watermark. Thumb Instructions A7-88 Copyright © 1996-2000 ARM Limited. All rights reserved. ARM DDI 0100E 7.1.53 STR (2) This form of STR allows 32-bit data from a general-purpose register to be stored to memory. The addressing mode is useful for pointer + large offset arithmetic, and for accessing a single element of an array. Syntax STR <Rd>, [<Rn>, <Rm>] where: <Rd> Is the register that contains the word to be stored to memory. <Rn> Is the register containing the first value used in forming the memory address. <Rm> Is the register containing the second value used in forming the memory address. Architecture version All T variants Exceptions Data Abort Operation address = Rn + Rm if address[1:0] == 0b00 Memory[address,4] = Rd else Memory[address,4] = UNPREDICTABLE Notes Data abort For details of the effects of the instruction if a data abort occurs, see Effects of data-aborted instructions on page A2-17. Alignment If the memory address is not word-aligned and no data abort occurs, the value written to memory is UNPREDICTABLE. If an implementation includes a System Control coprocessor (see Chapter B2 The System Control Coprocessor) and alignment checking is enabled, an address with bits[1:0] != 0b00 causes an alignment exception (a type of data abort). 15 14 13 12 11 10 9 8 6 5 3 2 0 0101000 Rm Rn Rd Please purchase PDF Split-Merge on www.verypdf.com to remove this watermark. Thumb Instructions ARM DDI 0100E Copyright © 1996-2000 ARM Limited. All rights reserved. A7-89 Equivalent ARM syntax and encoding STR <Rd>, [<Rn>, <Rm>] 31302928272625242322212019 1615 1211109876543 0 111001111000 Rn Rd 00000000 Rm Please purchase PDF Split-Merge on www.verypdf.com to remove this watermark. Thumb Instructions A7-90 Copyright © 1996-2000 ARM Limited. All rights reserved. ARM DDI 0100E 7.1.54 STR (3) This form of STR allows 32-bit data from a general-purpose register to be stored to memory. The addressing mode is useful for accessing stack data. In this case, STR stores a word from register <Rd> to memory. Syntax STR <Rd>, [SP, #<immed_8> * 4] where: <Rd> Is the register that contains the word to be stored to memory. SP Is the stack pointer. Its value is used to calculate the memory address. <immed_8> Is an 8-bit value that is multiplied by 4 and added to the value of the SP to form the memory address. Architecture version All T variants Exceptions Data Abort Operation address = SP + (immed_8 * 4) if address[1:0] == 0b00 Memory[address,4] = Rd else Memory[address,4] = UNPREDICTABLE 15 14 13 12 11 10 8 7 0 10010 Rd immed_8 Please purchase PDF Split-Merge on www.verypdf.com to remove this watermark. Thumb Instructions ARM DDI 0100E Copyright © 1996-2000 ARM Limited. All rights reserved. A7-91 Notes Data abort For details of the effects of the instruction if a data abort occurs, see Effects of data-aborted instructions on page A2-17. Alignment If the memory address is not word-aligned and no data abort occurs, the value written to memory is UNPREDICTABLE. If an implementation includes a System Control coprocessor (see Chapter B2 The System Control Coprocessor), and alignment checking is enabled, an address with bits[1:0] != 0b00 causes an alignment exception (a type of data abort). Equivalent ARM syntax and encoding STR <Rd>, [SP, #<immed_8> * 4] 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 12 11 10 9 2 1 0 1110010110001101 Rd 00 immed_8 00 Please purchase PDF Split-Merge on www.verypdf.com to remove this watermark. Thumb Instructions A7-92 Copyright © 1996-2000 ARM Limited. All rights reserved. ARM DDI 0100E 7.1.55 STRB (1) This form of the STRB (Store Register Byte) instruction allows 8-bit data from a general-purpose register to be stored to memory. The addressing mode is useful for accessing structure (record) fields. With an offset of zero, the address produced is the unaltered value of the base register <Rn>. Syntax STRB <Rd>, [<Rn>, #<immed_5>] where: <Rd> Is the register whose least significant byte is stored to memory. <Rn> Is the register containing the base address for the instruction. <immed_5> Is a 5-bit immediate value that is added to the value of <Rn> to form the memory address. Architecture version All T variants Exceptions Data Abort Operation address = Rn + immed_5 Memory[address,1] = Rd[7:0] Notes Data abort For details of the effects of the instruction if a data abort occurs, see Effects of data-aborted instructions on page A2-17. Equivalent ARM syntax and encoding STRB <Rd>, [<Rn>, #<immed_5>] 15 14 13 12 11 10 6 5 3 2 0 01110 immed_5 Rn Rd 31302928272625242322212019 1615 121110987654 0 111001011100 Rn Rd 0000000 immed_5 Please purchase PDF Split-Merge on www.verypdf.com to remove this watermark. Thumb Instructions ARM DDI 0100E Copyright © 1996-2000 ARM Limited. All rights reserved. A7-93 7.1.56 STRB (2) This form of STRB allows 8-bit data from a general-purpose register to be stored to memory. The addressing mode is useful for pointer + large offset arithmetic, and for accessing a single element of an array. Syntax STRB <Rd>, [<Rn>, <Rm>] where: <Rd> Is the register whose least significant byte is stored to memory. <Rn> Is the register containing the first value used in forming the memory address. <Rm> Is the register whose value is added to <Rn> to form the memory address. Architecture version All T variants Exceptions Data Abort Operation address = Rn + Rm Memory[address,1] = Rd[7:0] Notes Data abort For details of the effects of the instruction if a data abort occurs, see Effects of data-aborted instructions on page A2-17. Equivalent ARM syntax and encoding STRB <Rd>, [<Rn>, <Rm>] 15 14 13 12 11 10 9 8 6 5 3 2 0 0101010 Rm Rn Rd 31302928272625242322212019 1615 1211109876543 0 111001111100 Rn Rd 00000000 Rm Please purchase PDF Split-Merge on www.verypdf.com to remove this watermark. Thumb Instructions A7-94 Copyright © 1996-2000 ARM Limited. All rights reserved. ARM DDI 0100E 7.1.57 STRH (1) This form of the STRH (Store Register Halfword) instruction allows 16-bit data from a general-purpose register to be stored to memory. The addressing mode is useful for accessing structure (record) fields. With an offset of zero, the address produced is the unaltered value of the base register <Rn>. Syntax STRH <Rd>, [<Rn>, #<immed_5> * 2] where: <Rd> Is the register whose least significant halfword is stored to memory. <Rn> Is the register containing the base address for the instruction. <immed_5> Is a 5-bit immediate value that is multiplied by two and added to the value of <Rn> to form the memory address. Architecture version All T variants Exceptions Data Abort Operation address = Rn + (immed_5 * 2) if address[1:0] == 0 Memory[address,2] = Rd[15:0] else Memory[address,2] = UNPREDICTABLE 15 14 13 12 11 10 6 5 3 2 0 10000 immed_5 Rn Rd Please purchase PDF Split-Merge on www.verypdf.com to remove this watermark. Thumb Instructions ARM DDI 0100E Copyright © 1996-2000 ARM Limited. All rights reserved. A7-95 Notes Data abort For details of the effects of the instruction if a data abort occurs, see Effects of data-aborted instructions on page A2-17. Alignment If the memory address is not halfword-aligned and no data abort occurs, the value written to memory is UNPREDICTABLE. If an implementation includes a System Control coprocessor (see Chapter B2 The System Control Coprocessor) and alignment checking is enabled, an address with bit[0] != 0 causes an alignment exception (a type of data abort). Equivalent ARM syntax and encoding STRH <Rd>, [<Rn>, #<immed_5> * 2] 31 30 29 28 27 26 25 24 23 22 21 20 19 16 15 12 11 10 9 8 7 6 5 4 3 1 0 111000011100 Rn Rd 00 immed [4:3] 1011 immed [2:0] 0 Please purchase PDF Split-Merge on www.verypdf.com to remove this watermark. Thumb Instructions A7-96 Copyright © 1996-2000 ARM Limited. All rights reserved. ARM DDI 0100E 7.1.58 STRH (2) This form of STRH allows 16-bit data from a general-purpose register to be stored to memory. The addressing mode is useful for pointer + large offset arithmetic and for accessing a single element of an array. Syntax STRH <Rd>, [<Rn>, <Rm>] where: <Rd> Is the register whose least significant halfword is stored to memory. <Rn> Is the register containing the first value used in forming the memory address. <Rm> Is the register whose value is added to <Rn> to form the memory address. Architecture version All T variants Exceptions Data Abort Operation address = Rn + Rm if address[1:0] == 0 Memory[address,2] = Rd[15:0] else Memory[address,2] = UNPREDICTABLE Notes Data abort For details of the effects of the instruction if a data abort occurs, see Effects of data-aborted instructions on page A2-17. Alignment If the memory address is not halfword-aligned and no data abort occurs, the value written to memory is UNPREDICTABLE If an implementation includes a System Control coprocessor (see Chapter B2 The System Control Coprocessor) and alignment checking is enabled, an address with bit[0] != 0 causes an alignment exception (a type of data abort). 15 14 13 12 11 10 9 8 6 5 3 2 0 0101001 Rm Rn Rd Please purchase PDF Split-Merge on www.verypdf.com to remove this watermark. [...]... 32-bit facilities ARM DDI 0100E Copyright © 1996-2000 ARM Limited All rights reserved Please purchase PDF Split-Merge on www.verypdf.com to remove this watermark A8-1 The 26-bit Architectures 8.1 Overview of the 26-bit architectures ARMv1, ARMv2, and ARMv2a are earlier versions of the ARM architecture which implement only a 26-bit address space, and are known as 26-bit architectures ARM architecture version... 1996-2000 ARM Limited All rights reserved Please purchase PDF Split-Merge on www.verypdf.com to remove this watermark ARM DDI 0100E The 26-bit Architectures 8.5 Backwards compatibility from 32-bit architectures As described in Overview of the 26-bit architectures on page A8-2, some 32-bit architectures include mandatory or optional backwards-compatibility support for 26-bit architectures Architecture. .. 32-bit address space and are known as 32-bit architectures For backwards compatibility: • except for ARMv3G, all variants of ARM architecture version 3 implement the 26-bit address space • all non-T variants of ARM architecture version 4 and above can optionally implement the 26-bit address space This chapter describes the differences between the 26-bit and 32-bit architectures, and how the backwards-compatibility... PC, CPSR (architecture version 4 and above) ARM DDI 0100E Copyright © 1996-2000 ARM Limited All rights reserved Please purchase PDF Split-Merge on www.verypdf.com to remove this watermark A8-9 The 26-bit Architectures Note The MRS and MSR instructions are supported in all cases, despite the fact that they do not exist in pure 26-bit architectures This is to assist conversion to a 32-bit architecture, ... in the 26-bit address space to be branched to A8-2 Copyright © 1996-2000 ARM Limited All rights reserved Please purchase PDF Split-Merge on www.verypdf.com to remove this watermark ARM DDI 0100E The 26-bit Architectures Together, these differences make up the fundamental distinction between 26-bit and 32-bit architectures: 26-bit architectures All process status (namely the condition flags, interrupt... and 32-bit architectures M[1:0] also have the same meaning in both architectures Abort, Undefined, and System mode are not supported in 26-bit architectures Aborts and Undefined Instruction exceptions have exactly the same actions in both modes, except that in 26-bit architectures, Supervisor mode is entered instead of Abort or Undefined mode The precise effect of an exception on a 26-bit architecture. .. Yes SWI Yes Yes TST ARM DDI 0100E v4T, v4TxM Yes Yes Copyright © 1996-2000 ARM Limited All rights reserved Please purchase PDF Split-Merge on www.verypdf.com to remove this watermark A7-105 Thumb Instructions A7-106 Copyright © 1996-2000 ARM Limited All rights reserved Please purchase PDF Split-Merge on www.verypdf.com to remove this watermark ARM DDI 0100E Chapter A8 The 26-bit Architectures This chapter... differences between the 26-bit and the 32-bit architectures: Program counter The 26-bit architectures implement only a 24-bit program counter in R15, which allows 64MB of program space The 32-bit architectures have a 30-bit program counter in R15 which allows 4GB of program space on 32-bit architectures Processor modes Only four processor modes are supported on 26-bit architectures: • User (0b00) • FIQ (0b01)... Split-Merge on www.verypdf.com to remove this watermark 3 0 Rm A7-103 Thumb Instructions 7.2 Thumb instructions and architecture versions Table 7-1 shows which Thumb instructions are present in each current ARM architecture version that supports Thumb Table 7-1 Thumb instructions by architecture Instruction v5T, v5TxM ADC Yes Yes ADD (all forms) Yes Yes AND Yes Yes ASR (both forms) Yes Yes B (both... 32-bit architecture The I, F and M[1:0] bits cannot be written directly when the processor is in User mode In User mode they are only changed by an exception occurring 8.2.1 Reading register 15 In 26-bit architectures, the value of R15 is read in five different ways: • Most importantly, if R15 has an UNPREDICTABLE value in the 32-bit architecture, it also has an when used in the same way in the 26-bit architecture . this watermark. Thumb Instructions ARM DDI 0100E Copyright © 1996-2000 ARM Limited. All rights reserved. A7-89 Equivalent ARM syntax and encoding STR <Rd>,. this watermark. Thumb Instructions ARM DDI 0100E Copyright © 1996-2000 ARM Limited. All rights reserved. A7-97 Equivalent ARM syntax and encoding STRH <Rd>,