Tài liệu The 8051 Microcontroller - CHAPTER 6 docx

The 8051 Microcontroller Third Edition... time a Base-level execution Main foreground Interrupt-level execution background b FIGURE 6-1 Main ISR 1 Main program

The 8051 Microcontroller

Third Edition

time

(a)

Base-level

execution Main

(foreground)

Interrupt-level

execution

(background)

(b)

FIGURE 6-1

Main

ISR

1

Main program

ISR

2

*Interrupt

ISR

**Return from interrupt instruction

Program execution with and without interrupts (a) Without interrupts (b) With interrupts

BIT DESCRIPTION BIT SYMBOL ADDRESS (1 = ENABLE, 0 = DISABLE)

IE.7 EA AFH Global enable/disable

IE.6 — AEH Undefined

IE.5 ET2 ADH Enable Timer 2 Interrupt (8052)

IE.4 ES ACH Enable serial port interrupt

IE.3 ET 1 ABH Enable Timer 1 interrupt

IE.2 EX1 AAH Enable external 1 interrupt

IE.1 ETO A9H Enable Timer 0 interrupt

IE.O EXO A8H Enable external 0 interrupt

TABLE 6-1

IE (interrupt enable) register Summary

TABLE 6-2

IP (interrupt priority) register summary

TABLE 6-3

Interrupt flag bits INTERRUPT FLAG SFR REGISTER AND BIT POSITION

External 0 IEO TCON.1 External 1 IE1 TCON.3 Timer 1 TF1 TCON.7 Timer 0 TFO TCON.5

Timer 2 TF2 T2CON.7 (8052) Timer 2 EXF2 T2CON.6 (8052)

<—— High

Individual

ITO

|

|

TFO —ơ ©—ơ©- %=Q—

I

I

ITI

¬ L > !

INT1 IEI —o~o of ° on

0

|

|

_TFI œ⁄©——ơo© —o—>

!

|

I

|

!

|

I

FIGURE 6-2

Global enable

Overview of 8051 interrupt structure

priority interrupt

<— Low priority interrupt

polling sequence

interrupt

Table 6-4

Interrupt vectors

INTERRUPT FLAG VECTOR ADDRESS

External 0 IEO 0003H Timer 0 TFO 000BH External 1 IE1 0013H Timer 1 TF1 001BH

Timer 2 TF2 or EXF2 002BH

External code FIGURE 6-3

> Main program

Reset and

> interrupt entry points

0000 LLJMP_MAIN

8031

P1.7

P1.6

FIGURE 6-4

Waveform example

HOT

COLD

INTO

INTI

8031

PI.7 F———> Furnace on

HOT COLD

P1.7 (b)

FIGURE 6-5

Furnace example (a) Hardware connections (b) Timing

Door

INTO

8031

P1.7

74L504

+5V

(a)

H—$——————— | Second _>

›z — |IIITIIIIIIIIIIIIII [II

ae Ay "

P1.7

(expanded view) —

(b)

Loudspeaker

FIGURE 6-6

Loudspeaker interface using interrupts

(a) Hardware connections (b) Timing

\

( ssPi | S5P2 | SóPI |

LU

A

Interrupts

sampled

FIGURE 6-7 Sampling of interrupts

on S5P2

`

`

`

`

`

`

\

S6P2_ˆ

———0.25 Is———>

time

| Cycle 1 | Cycle 27 Cycle 3 | Cycle 4 | Cycle 5 |

/ Interrupts Interrupt accepted \ Interrupts polled (PC pushed on stack) ISR

sampled begins

FIGURE 6-8 Must be last cycle of instruction

Polling of interrupts

T T T T H~

FIGURE 6-9

Interrupt latency

9 ps

Level 1 interrupt occurs

here (missed last chance before RETI instruction)