The MII management contains a set of optional attributes. With the MII control/status register the read or write operation to the MII is controlled.
Parameter
MII write access
This parameter shall contain the information, if a write access to the MII is allowed.
Read should be always enabled if MII management is supported.
Address offset
This parameter shall contain the information about the offset between port number and MII address.
Read operation
This parameter will be written from the master to start the read operation of 16 bits in the MII. This parameter will be read from the master to check if the read operation is finished.
Write operation
This parameter will be written from the master to start the write operation of 16 bits in the MII. This parameter will be read from the master to check if the write operation is finished. There is no consistence guarantee for write operation. A break down during write can produce inconsistent values and should be avoided omission critical operations.
Error command
This parameter shall contain the information if the last access to the MII was successful.
Busy
This parameter contains the information if an access operation is ongoing.
The attribute types of MII control/status are described in Figure 26.
typedef struct
{ unsigned WriteAccess: 1;
unsigned Reserved1: 6;
unsigned PHYoffset: 1;
unsigned ReadOperation: 1;
unsigned WriteOperation: 1;
unsigned Reserved2: 4;
unsigned WriteError: 1;
unsigned Busy: 1;
} TMIICONTROL;
Figure 26 – MII control/status type description The MII control/status coding is specified in Table 52.
Table 52 – MII control/status
Parameter Physical
address Data type Access
type
Access type
PDI Value/description
Write access 0x0510 Unsigned1 RW R 0x00: only read
access to MII 0x01: read and write access to MII
Access PDI 0x0510 Unsigned1 R R 0x00: Only ECAT
0x01: PDI access possible
Link Detection via MII management interface
0x0510 Unsigned1 R R 0x00: Not active
0x01: Active
PHYoffset 0x0510 Unsigned5 R R 0x00 (Default)
offset to be added to MII address Set up by local configuration
Parameter Physical
address Data type Access
type
Access type
PDI Value/description
Read operation 0x0511 Unsigned1 RW R 0x00: no read
operation requested (parameter write) or read operation not busy (parameter read)
0x01: read operation requested (parameter write) or read operation busy (parameter read) To start a new read operation there shall be a positive edge on this parameter
Write operation 0x0511 Unsigned1 RW R 0x00: no write
operation requested (parameter write) or write operation not busy (parameter read)
0x01: write operation requested (parameter write) or write operation busy (parameter read) To start a new write operation there shall be a positive edge on this parameter
reserved 0x0511 Unsigned3 R R 0x00
Read error 0x0511 Unsigned1 R R 0x00: no error on last
read operation 0x01: error on last read operation
Write error 0x0511 Unsigned1 R R 0x00: no error on last
write operation 0x01: error on last write operation
Busy 0x0511 Unsigned1 R R 0x00: operation is
finished
0x01: operation is ongoing
6.5.2 Actual MII address
The actual MII address register contains the actual address in the MII register of the slave which is accessed by the next read or write operation (by writing the MII control/status register).
Parameter Address PHY
This parameter shall contain the address of the PHY which is accessed by the next read or write operation.
Address PHY register
This parameter shall contain the address of the PHY register which is accessed by the next read or write operation. PHY registers can be found in Clause 22 of ISO/IEC 8802-3:2000.
The attribute types of MII address are described in Figure 27.
typedef struct
{ Byte PHYAddress;
Byte RegAddress;
} TMIIADDRESS;
Figure 27 – MII address type description The actual MII address coding is specified in Table 53.
Table 53 – Actual MII address
Parameter Physical
address Data type Access type
Access type
PDI Value/description
Address PHY 0x0512 Unsigned8 RW RW Address of the PHY
(0-63)
Address register 0x0513 Unsigned8 RW RW Address of the PHY
Registers
6.5.3 Actual MII data
The actual MII data register contains the data (16 bit) to be written in the MII with the next write operation or the read data (16 bit) with the last read operation.
Parameter Data
The master will write this parameter with the data to be written in the MII with the next write operation. The master will receive the last read data from the MII when reading this parameter.
The attribute type of MII data is described in Figure 28.
typedef struct
{ Word MIIData;
} TMIIDATA;
Figure 28 – MII data type description The actual MII data coding is specified in Table 54.
Table 54 – Actual MII data
Parameter Physical
address Data type Access type
Access type
PDI Value/description
Data 0x0514 Unsigned16 RW RW
6.5.4 MII access
The optional MII access registers mangages the MII access from ECAT and from PDI.
Parameter Access MII
The control of the MII management
Access State
The register reflects the current access state Access Reset
Reset Access State register
The attribute type of MII access is described in Figure 29.
typedef struct
{ unsigned MIIAccess: 1;
unsigned Reserved1: 7;
unsigned MIIAccessState: 1;
unsigned MIIAccessReset: 1;
unsigned Reserved2: 6;
} TMIIAccess;
Figure 29 – MII access type description The MII access coding is specified in Table 55.
Table 55 – MII access
Parameter Physical
address Data type Access type
Access type
PDI Value/description
MII Access 0x0516 Unsigned1 RW R 0: PDI control possible
1: No PDI control
reserved 0x0516 Unsigned7 R R
Access State 0x0517 Unsigned1 R RW 0: ECAT access active
1: PDI access active
Access Reset 0x0517 Unsigned1 RW R 0: no action
1: reset 0x0517.0
reserved 0x0517 Unsigned6 R R