The DLL parameters and times described below are used to monitor the DL-subnetwork operation in the DLL of the master. The monitoring times are measured either in seconds (s) or in the number of bus cycles.
4.7.1 PDL parameters
4.7.1.1 SPA_acknowledge_timeout TTO_SPA_ACK
there is a timeout, the local PDL shall attempt up to max_spa_retry-times to send the DLSDU to the remote PDL. If no attempt was successful, the PDL shall return a negative acknowledgement to the user. In addition, this communication relationship shall be locally disconnected and the PDL shall attempt to synchronize itself again with the corresponding PDL of the communication partner.
The SPA_acknowledge_timeout can be calculated as follows:
tTO_SPA_ACK = (DIST + add_wait) * tUP where
DIST is a constant number of 5 bus cycles;
add_wait is an additional redundancy of 1 to 4 bus cycles;
tUP is the update time.
4.7.1.2 max_spa_retry
This DLL parameter specifies the maximum number of repeated attempts to send SPA PDUs.
It can be parameterized by means of a PNM2_Set_Value.request primitive.
Value range : 0, 2, 4, 6 …14 4.7.1.3 max_swa_count
This DLL parameter specifies the maximum number of successive data cycles with errors which are allowed before the PDL protocol machine reports a multiple data cycle error and carries out a synchronization with the protocol machine of the remote device.
Value range : 0 … 255 4.7.2 BLL parameters 4.7.2.1 update_time tUP
The update time is the time which passes between two starts of bus cycles. By setting the update time with a PNM2_Set_Value.request primitive the time-equidistance of the DL-subnetwork can be obtained. The update time shall be greater or equal to the bus cycle time (except zero) and is preset by the system to the value zero (default).
The value zero means that the update time is not defined. Thus, the automatic start of a bus cycle merely depends on the end of the previous bus cycle and the complete processing of the PDL protocol machines and not of the timeout of the update timer. That means, the time aquidistance is deactivated by the default setting.
Parameter size: 4 octets Settable values: tUP × 0,1 ms 4.7.2.2 bus_timeout tTO_BUS
The bus timeout is the maximum time which may pass between two valid data cycles. If this time is exceeded, there is a fatal bus error, which could not be repaired independently (for example, environment with strongly interference or broken cable). The bus timeout can be parameterized with a PNM2_Set_Value.request primitive. If the bus timeout is set to the value zero, the bus monitoring is disabled.
Parameter size: 4 octets Settable values: tTO_BUS × 1 ms 4.7.3 MAC parameters 4.7.3.1 Device code
Figure 81 shows the structure of the device code:
b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
octet quantity of the parameter channel Data direction and/or
Device class Data width Messages
Figure 81 – Device code structure
Bits 0 and 1 have to be interpreted differently for devices with or without parameter channel.
For devices without parameter channel the bits indicate the direction of the user data. For devices with parameter channel the bits indicate the number of octets which are used for the parameter channel.
Bits 6 and 7 of the device code distinguish whether the device has a parameter channel or not. For devices with a parameter channel the bits 6 and 7 shall have only the value combination Bit6 =1 and Bit7 =1.
4.7.3.2 Data direction (bit 0 and bit 1 ≠ 1)
If bits 6 and 7 ≠ 1, the bits indicate whether the device occupies input and/or output addresses (see Table 56).
Table 56 – Data direction
Bit 1 Bit 0 Meaning
0 0 No data address (for example, bus coupler) 0 1 Only output addresses occupied
1 0 Only input addresses occupied 1 1 Input and output addresses occupied
4.7.3.3 Number of octets occupied in the parameter channel (bit 7 = 1 and bit 6 = 1) If bits 7 and 6 are both 1, bits 1 and 0 indicate how many octets of the parameter channel the device occupies (see Table 57).
Table 57 – Number of the occupied octets in the parameter channel
Bit 1 Bit 0 Number of occupied words of the parameter channel
0 0 4 octets
0 1 8 octets
1 0 Reserved
1 1 2 octets (standard)
4.7.3.4 Device class
Certain bit combinations of the bits 2 through 7 indicate the device class (see Table 58). The other combinations are reserved for the identification of device functions. These specifications should be described in device profiles.
Table 58 – Device class
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Device class
0 0 0 0 1 0 0 0 Bus coupler with local bus branch
0 0 0 0 1 1 0 0 Bus coupler with remote bus branch
0 0 0 0 1 0 1 1 Bus coupler with I/O data
0 1 1 1 1 1 x x Analog local bus device
1 0 1 1 1 1 x x Digital local bus device
1 1 0 1 1 1 x x Local bus device with parameter
channel
0 0 0 0 0 0 x x Digital remote bus device
0 0 1 1 0 0 x x Analog remote bus device
1 1 1 1 0 0 x x Remote bus device with parameter
channel where
x "don't care".
4.7.3.5 Control data
Bits 13 to 15 return control data from the device to the master (see Table 59).
Table 59 – Control data
Bit 15 Bit 14 Bit 13 Meaning
x x 1 Reserved
x 1 X CRC receive error
1 x X Reserved
where
x "don't care".
4.7.3.6 Data width
The data width specifies how many bits the device occupies on the bus. If a device has, for example, 16 bit inputs and 32 bit outputs, it occupies 32 bit (4 octets) in the ring (the higher value is decisive) (see Figure 82 and Table 60).
Data width = 6 octets
Process data channel 4 octets
Parameter channel 2 octets
Figure 82 – Relations between data width, process data channel and parameter channel Table 60 – Data width
Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Data width
0 0 0 0 0 0
0 1 1 0 0 1 bit
0 1 1 0 1 2 bits
0 1 0 0 0 4 bits
0 1 0 0 1 1 octet
0 1 0 1 0 12 bits
0 0 0 0 1 2 octets
0 1 0 1 1 3 octets
0 0 0 1 0 4 octets
0 0 0 1 1 6 octets
0 0 1 0 0 8 octets
0 0 1 0 1 10 octets
0 1 1 1 0 12 octets
0 1 1 1 1 14 octets
0 0 1 1 0 16 octets
0 0 1 1 1 18 octets
1 0 1 0 1 20 octets
1 0 1 1 0 24 octets
1 0 1 1 1 28 octets
1 0 0 1 0 32 octets
1 0 0 1 1 48 octets
1 0 0 0 1 52 octets
1 0 1 0 0 64 octets
1 0 0 0 0 Reserved
1 1 x x x Reserved
where
x = "don't care".
4.7.3.7 Control code
Figure 83 shows the structure of the control code:
b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
Invalid Medium control
Figure 83 – Structure of the control code 4.7.3.8 Invalid
Bit 15 defines whether the control code is effective. If bit 15 equals 0, the code is effective.
4.7.3.9 Medium control (Bit 8 to Bit 11)
Bits 8 to 11 control the MAU of the outgoing interfaces (see Table 61).
Table 61 – Medium control
Bit 11 Bit 10 Bit 9 Bit 8 Meaning
X x X 1 Reset of the ring segment which is connected to the outgoing interface 1
X x 1 X Reset of the ring segment which is connected to the outgoing interface 2
X 1 X X Outgoing interface 1 disabled 1 x X x Outgoing interface 2 disabled where
x "don't care".
NOTE The remaining bits of the control code are reserved.
Annex A (informative)
–
Implementation possibilities of definite PNM2 functions