BEFEREHCE: Ygartua, C.L. and Swaroop, R.B., "High Dose Arsenic Implant for Bipolar Buried Layers", Semiconductor Fabrication; Technology and Metrology, ASTM STP 990, Dinesh c. Gupta, editor, American Society for Testing and Materials, Philadelphia 1989.
ABSTRACT: The use of arsenic ion implant for a low sheet resistance and deep junction buried layer pro- cess was investigated. Appropriate ion doses and energy were found to obtain the desired buried layer profile using a pre-implant oxide. A low temperature (1050°C) oxidation was employed to remove the highly damaged surface region after diffusion/anneal of the arsenic implant. Damage was characterized after the buried layer process and epitaxial growth. The elec- trical performances and relative yield of the bipolar devices made from implanted and deposited (solid- source) arsenic buried layer were compared. The re- sults indicated that implanted buried layer produced almost defect free epitaxial layer in the subsequent processing.
KEY WORDS: Arsenic Implant, Buried Layer, Epitaxial Defects.
A buried layer process in silicon wafers must result in a surface that is free of crystallographic defects for a high quality epitaxial film to be deposited. Metallic precipitates in the buried layer will cause stacking faults in the epi layer and dislocation loops will be propagated into the Epi layer, i.e. any disorder or con- tamination will cause disorder in the epi layer that could eventually result in failure of a device (1). The major failure mechanism is due to metallic precipitation at the point detects if these defect precipitation
Mr. Ygartua is a Senior Engineer at National Semicon- ductor (formerly Fairchild) 545 Whisman Rd., (M/S 2-200), Mountain View, California 94039. Dr. Swaroop is Director of Technology at ASYST Technologies Inc., 1745 McCandless Dr., Milpitas, CA 95035. Formerly he was with National Semiconductor (Fairchild) when this work was performed.
clusters happen to be in an active region of a device such as p-n junction depletion region.
The high diffusivity (and possible good crystal fit factor) of arsenic makes it desirable for a low sheet re- sistance deep junction buried layer. It is heavy enough ion to cause extensive damage to the implanted region if the buried layer is achieved via implant method. Anneal- ing and/or removal of the damaged layer is therefore necessary. Some annealing takes place during implanta- tion due to heating of the wafers from stopping of the ion beam (2). This generally results in partial anneal- ing which is not desirable since re-crystallization by epitaxial type growth in the damaged layer occurs opti- mally when the implanted layer is completely amorphous.
An energy of 80 KEV was chosen to maximize damage to the silicon, since at this energy nuclear stopping pre- dominates for Arsenic. We have investigated the use of a pre-implant oxide in order to trap metallic impurities.
The source of metallic impurities trapped by the pre- implant oxide is conjectured to be sputtered ions from the implant chamber. The disadvantage of the pre-implant oxide is recoil-implanted oxygen (3), but the damage re- sulting from this is shallow enough (less than 1200A'' (3)) to be removed during the post-diffusion oxidation. In order to compensate for the arsenic that is stopped by the oxide a significantly higher dose: (1.0 x 10 ) cm
15 -2
vs. (5.0 X 10 ) cm is used to obtain the same sheet resistance.
Oxidation during annealing was kept to a minimum to prevent excessive oxide-defect complexes and formation of oxidation induced stacking faults (SF) (3). This study indicates that using the proper pre-implanted oxide thickness and damage anneal removal method, we are able to produce a defect free silicon epitaxial film over a heavily doped implanted arsenic buried layer.
EXPERIMEaTOAL PROCEDURE AND EVALUATION
The silicon wafers used for these experiments were P-type <111> with resistivity of (1.5-3) ohm-cm. Wafers were implanted with a Varian OF 3000 implanter with elec- trostatic scan at 80 KEV with Way-Flow cooling. Implant current was approximately 350uA, with doses varying be- tween S.OXIO-'-^ cm"'^ to LOXIO-"-^ cm"*^. Wafers were im- planted both with and without a pre-implant oxide. The pre-implant oxide thickness was either 300A° or 600A°.
The details of experimental process steps are given in Figure 1.
After implantation wafers with pre-implant oxide were etched with HF to remove the oxide in some cases. In
other cases the oxide was left on. Wafers then received a diffusion/anneal process to obtain the desired sheet resistance and junction depth.
Diffusion/anneal consisted of 400 min. dry N- cycle at 1250''C which was more than sufficient for re-crystalli- zation of the damaged layer. The actual ramping was done in Nj/O, environment in order to avoid the N2 pitting (see Figure 1).
After diffusion/anneal a lower temperature lOSO'C dry 0- oxidation was performed to remove the remaining
damage. Oxide was then removed and an epitaxial layer was deposited using a barrel type radiation heated re- actor at 1200''C with SiCl. as a deposition source in H- carrier. The epitaxial layer was doped with phosphorous and a two minutes insitu HCl etch was performed prior to epi deposition. The epitaxial layer thickness used for study of defects was ~15vim with 3 - 5 ohm-cm resistivity.
A buried layer with a junction depth of 6-8ym was ob- tained after the high temperature (laSO'C) diffusion/
anneal. Implantation damage was examined using a pre- ferential etch after diffusion/anneal and after the low temperature oxidation. Epitaxial defects associated with implant damage and/or anomalous metallic contamination were also examined with preferential etch. The buried layer dopant profile was evaluated using spreading resist- ance profile (SRP) method. The latter measures carrier distribution (on a bevelled specimen) associated with the atomic profile.
The remaining bipolar device process steps were then performed and the finished devices were tested. Device yield was compared to an established process using a solid source (ASjOo) process.
RESULTS
1. Sheet Resistance Uniformity
Table 1 shows the results of sheet resistance uniform- ity across the wafer and wafer to wafer obtained through implant and solid-source deposition processes.
The Sigma (6) value given in this table is a standard deviation calculated for 5 positions on each wafer. A sample of 25 wafers was used. The within wafer 5 is the standard deviation of the averages of each wafer.
The wafer to wafer 6 is the standard deviation of the average of each wafer. The % variance within wafer is the ratio of the 5 within wafer to the average of all the measurements. The % variance wafer to wafer is the ratio of the 5 wafer to wafer to the average of all the measurements. It is apparent that the implant method produces excellent uniformity compared with the
solid-source deposition process.
Post Anneal/Diffusion
Extensive surface damage was observed both with and without pre-implant oxide after anneal/diffusion in the buried layer areas. Sirtl etching resulted in numerous etch pits of various sizes. The etch pits tended to be larger for the process without a pre- implant oxidation (Figure 2) than for the process with 600 A" pre-implant ox (Figure 3).
Post Oxidation:
A 2000 A' dry Oj oxidation (at 1050"C) following the high temperature (1250''C) diffusion/anneal was suf- ficient to essentially consume the damaged silicon surface. Very few etch pits (after Sirtl etching) were observed for wafers with or without a pre-implant oxidation (Figures 4 and 5). This indicated that the damaged region extended less than 1000 A" into the silicon.
Post Epi:
Stacking faults were observed most frequently with the process that has no pre-implant oxide (Figure 6).
Wafers that had 300 A° and 600 A" pre-implant oxide but deglaze after implant also produced SF in the epitaxial layer (deglaze is etching of oxide in a diluted (6:1) HF solution for a given time). Figure 7 shows an example with a 600 A" pre-implant oxide that had no post implant deglaze. The least occurrence of SF were found with the process that had a 600 A° pre- implant oxide with the implant followed by a deglaze (Figure 8). An unacceptable number of SF were found with the 300 A" pre-implant oxide that also had a post implant deglaze (Figure 9). An acceptable number of SF for the product line investigated was less than 200 per cm .
Figure 10 shows the dopant profile of the Epi-buried layer structure obtained with the arsenic implant pro- cess for a 3um epi process. The profile shows minimal autodoping with a sharp transition region.
In Table 2 the approximate defect density after epi deposition for each process is shown. Devices were fabricated with the processes that had 300 A° and 600 A" pre-implant oxide with a deglaze following the im- plant. Table 3 shows a summary of the relative yield compared to the standard process (solid-source depo- sition) . The 600 A" pre-implant oxide process re- sulted in a yield that was equivalent to the standard yield which correlates with the lower defect density.