Figure 12.1 shows the radio data demodulator/decoder in relation to the other parts of a VHF/FM receiver equipped to use the Radio Data System. The decoder accepts the multiplex signal from the output of the FM discriminator as its input, and feeds its output to a microprocessor. This microprocessor drives a display, controls the tuning of the receiver, and also performs some of the later stages of decoding the radio data signal. Microprocessor systems are, of course, most commonly incorporated in many of the more sophisticated modern receivers, employing frequency synthesised tuning (PLL) to control these tuning functions and the presets chosen by the user. The RDS decoder
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can therefore be regarded as a logical extension. Such a control processor makes it possible to achieve better functionality and user friendliness, and eventually it will become an integrated part of the receiver.
Considering the functions of the radio data demodulator/decoder in a lit- tle more detail, six principal stages in the radio data demodulation/decoding process can be identified:
1. Demodulation of the 57 kHz suppressed-carrier amplitude modu- lated signal;
2. Decoding of the biphase symbols;
3. Recovery of the bit rate clock;
4. Recovery of group and block synchronisation;
5. Application of error detection and/or correction;
6. Decoding of address information and message codes.
All these stages can be implemented by a single microprocessor system.
The techniques used to perform these functions are described in quite some detail in the relevant annexes of the RDS/RBDS specifications.
As an example of how this concept was implemented in a 1995 high-end car radio designed by one large European manufacturer, the following informa- tion may be of some interest. This example uses a powerful 8-bit single-chip microcomputer from Motorola’s 68HC11 family (with PLL clock system, 32 KB of ROM, 1,024 bytes of RAM and 640 bytes of nonvolatile EEPROM, powerful timers, etc.) and a single-chip RDS demodulator with integrated
218 RDS: The Radio Data System
Figure 12.1 Typical block diagram of an RDS radio. (Source: EBU.)
57 kHz bandpass from either Philips or SGS/Thomson to obtain and process the continuous synchronous data stream and the clock frequency of 1.1875 kHz (57 kHz/48). The relatively high power of the microprocessor is necessary because, apart from the RDS functions, it must control the PLL tuning system, the display of a car radio, the functional keys of the radio, the sophisticated man/machine interface, the digitally controlled audio processor, the cassette player, the remote controlled CD changer, the traffic announcement recording system, the clock, and so on. Nearly all these operations must be done in real time. Multitasking capability is therefore necessary for the different logical devices, because some devices must run simultaneously.
Every 842às (1000000/1187.5),the microprocessor will receive a new bit from the continuous RDS data stream delivered by the RDS demodulator chip, load it into a 26-bit software shift register, and process the RDS data in a 26-bit sequence. However, this is only true if the data stream is truly synchronous; that is, the position of each bit in the data stream can be clearly interpreted. Loss of only one bit means that the microprocessor is getting asyn- chronous data. In that case, a more time-consuming task needs to be done to obtain block and group synchronisation.
To acquire group and block synchronisation at the receiver (for example, when the receiver is first switched on, or tuning to a new station, or after a pro- longed signal fade), the syndrome (see Appendix B) must be calculated for each received 26-bit sequence. That is, on every data clock pulse, the syndrome of the currently stored 26-bit sequence (with the most recently received data bit at one end and the bit received 26 clock pulses ago at the other) is calculated on every clock pulse. Then, with every new incoming bit (842 às), a complete multiplication with the H-matrix (see Appendix B) has to be performed with all the 26 bits in the shift register. As a result, the 10-bit syndrome will be obtained. It must then be compared with the six known syndromes of the specified offsets A (block 1), B (block 2), C (block 3 for group type A), C’
(block 3 for group type B), D (block 4), and E (occurs only with RBDS and detects MMBS data blocks in multiples of 4 in the RDS data stream). If a match occurs with a consecutive syndrome, 26 bits later (26ì842às) after 22 msec, then the microprocessor is synchronised with the data stream. RDS syn- chronisation thus occurs when two consecutive RDS blocks in series have been detected.
If RDS reception quality is poor, this task requires a lot of processing power; but if the reception is good, the decoding task is, of course, much shorter. With mobile data reception, the RDS data stream can be full of errors, and a temporary 50% error rate is not uncommon. This is usually caused by the low RDS injection level used by the broadcaster (±1.2 kHz in some critical cases, while±2.0 kHz is typical for the large majority of RDS implementations).
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Another cause can be the simultaneous use of the ARI system (see also Appen- dix C, giving more detail about RDS data reception reliability). However, since the sequence of the syndromes is known, the decoding process can work as a “flywheel” mechanism, which is separately explained below. If an unknown syndrome is detected, the respective block is bad; but if block 2 is bad, the whole data group may be unusable unless error correction is used. However, the latter has to be used with caution because before it can be applied, the type of error has to be identified before it can attempt any corrections—and even then it can generate an error, which is less problematic for data used for display only (e.g., PS and RT).
It is very important to detect loss of synchronisation as soon as possible.
One possibility is to check the syndrome continuously for acquisition of syn- chronisation. However, errors in the channel will make it difficult to continu- ously receive the expected syndromes, and therefore the decision must be based on the information from several blocks (e.g., up to 50 blocks). Another possi- bility is to check the number of errors in each block and base the decision on the number of errors in 50 blocks.
One possibility for detecting block synchronisation slips of one bit is to use the PI code, which does not usually change on any given transmission. If the known PI code is received correctly but is found to be shifted one bit to the right or to the left, then a one-bit clock slip is detected. The decoder can then immediately correct the clock slip.