The behaviour of a real device is distributed by nature; therefore, a good equivalent circuit can at best be an approximation. In general, the higher the number of elements in the equivalent circuit, the better is the approximation; however, the number of elements should be kept as low as possible, both for practical model extraction and for physical meaningfulness of the circuit elements. On the one hand, the evaluation of the element values should be as easy and straightforward as possible, and this is seriously hampered by an excessive number of elements in the circuit. On the other hand, the behaviour of the elements must satisfy the physical constraints (see previous paragraph) that are best fulfilled by elements with a clear correspondence to actual physical effects inside the device. Moreover, when physically meaningful, the equivalent circuit gives interesting information on the structure of the device, both as a feedback to technology and for a qualitative evaluation of the device performances by the designer.
As an example, the correspondence between a simple equivalent circuit of an MESFET and its physical structure is shown in Figure 3.42.
Several similar topologies are available for most active devices at microwave and millimetre-wave frequencies, like MESFETs, HEMTs, MOSFETs, BJTs and HBTs. In
Gate
Source
Drain
Source
Rg Rd
Ri Rds
Rs Ls
Cds gm t
Cgd Cgs
Lg Ld
(b) (a)
Source Gate Drain
Figure 3.42 The physical structure of an MESFET with the equivalent-circuit elements
general, they fit the wide-band small-signal (linear) parameters of the device for a given bias point; when this changes, the values of the intrinsic elements change too, while parasitics are unchanged. If this is true and the fit to wide-band small-signal parameters is still good, the equivalent circuit is a valid candidate for nonlinear applications. Then, the dependence of the values of the intrinsic elements on the applied voltages is modelled by some fitting functions, with the limitations described in the previous paragraph; if this is true, the model is a good nonlinear model.
Let us illustrate this procedure with an example. The circuit in Figure 3.43 is an equivalent circuit suitable for fitting MESFETs and HEMTs in a wide-frequency band.
As an example, the measured S-parameters from 0.1 GHz to 40.1 GHz are shown in Figure 3.44, together with the S-parameters computed from the equivalent circuit, in a range of bias points (Vds=2.5 V,Vgs= −1.8÷0.5 V).
In Figure 3.45, the values of the intrinsic elements are plotted as a function of the gate–source voltage Vgs and of the drain–source voltageVds, together with a fitting function, in this case a neural network model [76].
The topology of the equivalent circuit together with the fitting functions identifies a large-signal equivalent-circuit model.
Let us now describe how the values of the elements of the equivalent circuit are extracted from small-signal data for a practical device. Two main approaches are available: a wide-band fit of the equivalent circuit to the small-signal measured data by means of numerical optimisation routines and the selective identification of groups of parameters by analytical means at special bias points.
A wide-band fit of the equivalent circuit to small-signal data is performed by means of any commercial CAD package. The optimisation variables are the values of
Cpgd
Cpds
Cpd Cpgs
Cpg
Cgd
Cgs Ci
Vi Vigme−jwt
Lg Ld
Ls
Intrinsic
Rgd Rd
Rg
Ri Rds Cds
Rs
Figure 3.43 The equivalent circuit of an FET
150 120
90
60
30 3
2 1
S21
50
10 120
90 03
60 0.2
0.1 30
33c S12
0 0.2 0.5 1 2 5
−j0.05
−j 0.5 −j 2
−j 5
−i1 S11
−j 0.5
−i1
−j 2
−j 5
S22
0.2 0.5 1 2 5
Figure 3.44 Measured and modelled S-parameters at many bias points (Vds=2.5 V, Vgs=
−1.8÷0.5 V)
the elements of the equivalent circuit at a given bias point; the optimisation routine varies them until theS-parameters of the equivalent circuit are as close as possible to the measured ones, in the whole frequency band of interest. Alternatively, Y-parameters or any other linear equivalent parameters can be fitted. The optimisation can be performed for each bias point separately or for all the data from all bias points of interest at once [29].
In the former case, the risk is that the optimised values of the parasitic elements vary from bias point to bias point, contrary to the assumption: this is an indication of bad topology or bad optimisation. In the latter case, the parasitics are forced to have the same values at all bias points; however, the numerical burden greatly increases. In both the cases, the optimisation algorithm risks to get trapped in local minima, never reaching the absolute minimum. The goal function is usually not very sensitive to some elements, whose values are therefore rather uncertain. This can be a problem for some applications: for example, the gate resistance in an FET is difficult to extract from normal, operating-point S- parameters, but its value is meaningful for the evaluation of the noise performances of the device. If this is the case, it is wise to adopt the global fitting procedure, also including special bias point as in the ‘two-tier’ procedure (see below). On the other hand, this approach has a remarkable advantage: it is very easy to change or adjust the topology of the equivalent circuit and have a fast feedback on its fitting accuracy. In addition, it is not restricted or dedicated to any topology or device, and there is no need to develop dedicated software.
160 140 120 100 80 60 40 20 0.50 0
2
4 −0.5−1−1.5−2
Cgs 6 4 4 2 0 0−0.5 −0.5−1−1.5
2 0 −2 −4 6
Ri gm 40 30 20 10 0 0246 −10 0.5−0.5−1.5−2−10
−2−30−20
−10
10
20
Rgd −1.5 −0.5 0.5−1 0
0 6
4
2
0 5 4 3 2 1 0 −1 6 4 2 0 0.50−0.5−1.5−2 −1
TauCin 15 10 5 0 0
0 2 4 6
−5 −10 −2−1.5−0.5 −1 Figure3.45ExtractedvaluesoftheintrinsicelementsofthecircuitinFigure3.34asafunctionofVgsandVds
The alternative approach, that is, the selective identification of the elements of the equivalent circuit, is based on the bias-independence of the parasitics. A ‘two-tier’
extraction procedure is performed: parasitics are first evaluated at special, suitable bias conditions, and their values are not changed afterwards; then, the intrinsic elements are evaluated at each normal, operating bias point within the region of interest. This approach has a clear advantage: the values of the elements are extracted by means of simple, ana- lytical formulae without any optimisation. Usually, a better understanding of the structure of the equivalent circuit is also gained.
A great variety of bias conditions has been proposed for parasitics evaluation [77–
87], but almost all require some measurements on a ‘cold’ device, that is, zero drain or collector voltage. This condition greatly simplifies the behaviour of the inner device, and parasitics are better evaluated. Basically, the measured small-signal parameters of the ‘cold’ device are equated to the corresponding analytic expressions of the small- signal parameters of the model; the equations are then explicitly solved for the values of the elements. Measurements at a single frequency can be used for the evaluation of the parameters, but averaging over frequency in a suitable band allows for reduction of random measurement errors. In general, diversity in frequency is a useful tool for improving the meaningfulness of the extraction.
A two-port S-parameter measurement at a ‘cold’ bias condition provides three complex equations, yielding six real values; if the parasitic elements are more than six, more than one ‘cold’ bias condition must be used. Moreover, not all equations yield reliable results, and it is usually better to have redundant data.
Let us illustrate the procedure by an example concerning an FET [83, 87]; the procedure described hereafter is by no means the only possible one and not necessarily the best: it is only one of the many proposed so far. In fact, it often turns out that a spe- cific device may require modifications of the procedure, because of minor but important differences in the structure of the device; however, the approach is usually similar.
Three ‘cold’ bias conditions are used in this example: depleted channel, that is, pinched-off FET (Vds=0, Vgs< Vpo), open channel (Vds=0, Vpo< Vgs< Vbi)and gate- channel junction in weak forward conduction (Vds=0, Vbi< Vgs). The intrinsic device behaves very differently in the three conditions in such a way that different parasitic elements are relevant in each bias condition. Somehow, this is similar to what is required from different calibration standards; in fact, in this case also, access elements of a device under investigation (in this case the intrinsic device) must be identified and removed. The equivalent circuits of the device in the three ‘cold’ conditions are shown in Figure 3.46.
In the case of pinched-off device, the measured S-parameters are converted to admittance Y-parameters, which are easier to express analytically for the equivalent cir- cuit. If we limit ourselves to a suitably low-frequency range, the inductances can be neglected, and the simplified equations read as follows:
Im(Y11)po=ω(Cpg+Cpgs+Cgs+Cpgd+Cgd) (3.69a)
Im(Y12)po=ω(Cpgd+Cgd) (3.69b)
Im(Y22)po=ω(Cin+Cds+Cpds+Cpd+Cpgd+Cgd) (3.69c)
Cpgd
Cgd
Cpg
Rs Cpgs
Cgs
Cds
Cpds
Cpd Rg
Lg
Ci
Rd Ld
Ls
Intrinsic
(a)
Cds
Cpds
Cpd Cpg
Rg
Rs Cpgs
Cpgd
Rd
Rch
Ld Lg
Ls
Intrinsic Cj
(b)
Figure 3.46 The equivalent circuits of a ‘cold’ FET: pinch-off (a), open channel (b) and weak forward conduction of the gate junction (c)
We consider only the imaginary part of the parameters for the extraction, since the real parts are not always found to give reliable results in this bias condition. When plotted against frequency, the measured parameters exhibit a linear behaviour at low frequencies, confirming the negligible effect of inductances in that frequency range; in Figure 3.47, the imaginary part of the Y11 parameter versus frequency is shown forVgs= −2 V.
Lg
Ls
Rj
Rd Ld
Rg
Cj
Rs
Cds Cpg
Cpgs
Cpgd
Cpd Cpds Rch
Intrinsic
(c)
Figure 3.46 (continued)
0 0.12 0.1 0.08
Im(Y11) 0.06
0.04 0.02
5 10 15 20
Frequency (GHz)
Figure 3.47 The imaginary part of theY11parameter for a pinched-off FET and the fitted capac- itive susceptance
The slope of the measured curve in the low-frequency range yields the values of the capacitances. If the measurement is repeated for decreasing gate–source voltages, the channel is more and more depleted; the values of the intrinsic capacitances tend to zero, and a plot of the extracted capacitance value versus gate–source voltageVgscan be extrapolated toVgs= −∞to eliminate their contribution (Figure 3.48).
0 3
2.5
2
Im(Y11)
1.5
1
0.5
−4
−4.5 −3.5 −3 −2.5 −2
Vg
× 10−3
Figure 3.48 Extrapolation of the extracted capacitance toVgs= −∞
In this way, the parasitic capacitances are found. In fact, the model shown in Figure 3.43 has five parasitic capacitances, while we have used only three measurements.
The additional informations required for complete identification are usually obtained from measurement of transistors of the same type but with different gate periphery.
This approach allows not only a more reliable extraction, but also the availability of a scalable model. However, in the case that the gate–source and drain–source parasitic capacitancesCpgs andCpds are negligible, the measurements are sufficient.
When pinched off, the intrinsic device behaves as a high impedance. Now, the dif- ferent condition of weak forward-biased gate-channel junction is considered: the intrinsic device behaves as a low impedance. It is neither necessary nor advisable to bias the junction in full conduction in order to avoid junction degradation: a small gate currentIg
is sufficient to open a conductive path from the gate to the channel. The expressions of the impedanceZ-parameters of the equivalent circuit read as follows:
Re(Z12)wfb=Rs+ Rch
2 − Rch2
12nVT ãIg (3.70a)
Im(Z12)wfb=ω
Ls+K1+K2
Ig
(3.70b) Re(Z22)wfb=Rs+Rd+Rch (3.70c) Im(Z22)wfb=ω(Ls+Ld+K3) (3.70d)
where Ig is the gate current, andK1, K2 and K3 are functions of resistances and capac- itances [87, 88]; their expressions are given in Appendix A.2. As in the previous case, not all equations have been considered: theZ11parameter does not usually yield reliable results. Plotting the measured data versus frequency, a suitable frequency range is iden- tified for the extraction of the parameter; for example, the real part of theZ12parameter is better evaluated at relatively high frequency (Figure 3.49).
The extracted value depends on the value of the gate currentIg: the corresponding term can be eliminated by repeating the measurement for several current values and extrapolating toIg→0 (Figure 3.50).
From this bias condition, the source and drain inductances are found, and two equations in the three unknown resistancesRs, Rd andRchannel are found.
The third ‘cold’ bias condition is somehow in between the other two: the channel is open, and controlled by the gate–source voltage. The equations relative to the impedance Z-parameters are
Re(Z11)oc = Cg2
Rg+Rs+γ Rch
3
+Cp2(Rs+Rd+γ Rch) +2CgCp
Rs+Rch
2
(Cg+Cpg+Cp)2 (3.71a)
Im(Z11)oc = − 1
ω(Cg+Cp+Cpg)+ω(Lg+K4Ls+K5) (3.71b)
0 4.5 4
2.5 2 3.5 3
Re(Z12)
1.5 1 0.5
10
5 15 20
Frequency (GHz)
Figure 3.49 The real part of theZ12parameter for a pinched-off cold FET and the fitted resistance
00 3
2.5
2
Re(Z12) 1.5
1
0.5
0.1 0.2 0.3 0.4 0.5
lg(mA)
0.6 0.7 0.8 0.9
Figure 3.50 Extrapolation of the extracted resistance toIg=0
Re(Z22)oc=Rs+Rd+γ Rch (3.71c)
γ =
1− Vb−Vgs
Vb−Vp
−1
(3.71d) where all capacitances except the gate-channel capacitance Cg are known, and K4 and K5 are functions of the resistances and capacitance [87, 88]; their expressions are given in Appendix A.2. Once more, a plot of the measured data versus frequency indicates the best frequency range for the extraction. For example, the real part of theZ11parameter is shown in Figure 3.51, suggesting a moderate- to high-frequency range for the evaluation.
The extracted value depends on the value of the gate–source voltage via a linear dependence on the γ parameter (Figure 3.52): the extrapolated value toγ →0 and the slope versusγ yield two equations.
Similarly, three other equations are given by the other parameters. In all, five equations in eight unknownsRg, Rs, Rd, Rchannel, Lg, Ls, Ld, andCgare obtained. Together with the weak forward-biased junction condition, we have now eight equations in as many unknowns: the system is easily solved, and the parasitics are extracted. Their values will not be changed by successive steps of the extraction.
Now the intrinsic, bias-dependent elements must be evaluated at normal oper- ating points. At each bias point, the S-parameters are measured and then de-embedded from the already evaluated parasitics. This is accomplished by successive transformations
00
5 10
Frequency (GHz) Re(Z11)
15 20
8
7
6
5
4
3
2
1
Figure 3.51 The real part of theZ11 parameter for a cold FET with the gate junction in weak forward conduction and the fitted resistance
00 7
6
5
4 Re(Z11)
3
2
1
1 2 3 4 5
g 6 7 8 9
Figure 3.52 Extrapolation of the extracted resistance toγ =0
to Z- and Y-matrices, from which series and shunt parasitic elements respectively are subtracted [83] (Figure 3.53); the de-embedded data correspond to the equivalent circuit shown in Figure 3.54.
The analytical expressions of the admittanceY-parameters of this intrinsic equiv- alent network read
Y11=ω2(RgdCgd2 +RiCgs2)+iω(Cgd+Cgs) Y12=ω2[RiCiCgs−RgdCgd(Cgd+Ci)]−iωCgd
Y21=gm−iω[Cgd+gm(τ+RiCgs)]
Y22=gds+i(Ci+Cgd−gmRiCi) (3.72)
[S ]measured Z11−jwLg Z12
Z21 Z22−jwLd
[Z ]measured [Y ]
[Y ] Z11−Ls Z12−Ls
Z21−Ls Z22−Ls Y11−jw(Cpg+ Cpgd)
Z21− jwCpgd
Z12−jwCpgd Z22+ jw(Cpd− Cpgd)
[Z ]
Z11−Rg− Rs Z21− Rs
Z12−Rs Z22− Rd− Rs
[Z ]intrinsic [Y ]intrinsic Y11−jwCpgs Y12
Y21 Y22−jwCpds
[Z ]
Figure 3.53 Procedure for the de-embedding of the parasitic elements from measured S-para- meters
Intrinsic Rds Rgd
Ri Vi
Vigme−jωτ Cgs
Cgd
Ci
Figure 3.54 Equivalent circuit of the intrinsic FET
and must be equated to the de-embedded measured data. By analytically solving for the intrinsic elements,
Cgs∼= Im(Y11+Y12) ω Cgd∼= −Im(Y12)
ω Cin∼= Im(Y12+Y22)
ω Rgd∼= 1
ω2 ã CinãRe(Y11)−CgsãRe(Y12) CinãCgd2 −CgsãCgdã(Cgd+Cin) gm=
(Re(Y21−Y12))2+(Im(Y21−Y12))2
τ = atanh
−Re(Y21−Y12) Im(Y21−Y12)
ω Ri∼= Re(Y11)−Rgdω2Cgd2
ω2Cgs2 Rds∼= 1
Re(Y22) (3.73)
The values of the intrinsic elements are found by averaging the above expressions over frequency in a low-to-medium frequency band. After evaluation, the measured and de-embedded intrinsic Y-parameters can be plotted versus frequency and compared to the extracted equivalent-circuit data for verification of the extraction. As an example, the real and imaginary parts of theY21parameter are shown in Figure 3.55 for the operating point Vgs= −0.6 V,Vds=5 V.
Alternatively, the extracted values of the elements are plotted versus frequency; as an example, the transconductancegm and the transit timeτ are plotted versus frequency in Figure 3.56.
From the plotted data, it is apparent that the elements of the intrinsic equivalent circuit are constant with frequency, fulfilling the basic hypothesis and confirming the validity of the topology and extraction procedure of the equivalent circuit for this device.
The extraction of the intrinsic elements is now repeated for all operating points of interest, and a table with the extracted values is available for nonlinear model construction, as explained in the previous paragraph.