Pseudonoise (PN) sequences are used as spectrum-spreading modulations for direct sequence SS designs, as hopping pattern sources in frequency and/or time hopping systems, and as filter section controllers in matched fil- ter SS systems. Ideally, most of the PN sequence design problems would be solved if it were possible to produce a sample of a sequence of independent random variables, uniformly distributed on the available alphabet, for use at the SS transmitter, and an identical sample sequence at the receiver for use in the detection process. This is the SS equivalent of the one-time pad used in cryptographic systems requiring the highest level of security.
Unfortunately, the generation, recording, and distribution of these sample sequences at a rate (per information bit to be communicated) equal to the processing gain of the SS system, is generally not feasible.
Once the one-time pad is discarded as a viable approach, the designer must come to grips with the problem of storing/generating a signal which looks random (e.g., like a one-time pad), despite the fact that it must be done with a real system possessing finite storage capacity/generating capability.
Let’s illustrate the possibilities by considering methods for the generation of a specified binary (0 or 1) sequence (bn,n1, 2, . . . ,N}. If Nbits of the random sequence are not sufficient to complete the communication process, the sequence must be reused, i.e.,
(5.1) where N is the period of the extended sequence. Any other method of reusing the stored sequence other than periodic extension as indicated above, will require additional memory to supervise the reuse algorithm.
Two approaches, in which the complete sequence is stored simultaneously within the generator, are shown in Figure 5.1. One is ROM-based, the other a simple cyclic shift register. Both have the property that they work equally well with any desired sequence {bn}. Obviously, the price for this versatility is memory:Nbinary storage elements and supporting hardware are needed.
bnNbn for all n,
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The storage requirements indicated by these designs can be reduced by the insertion of Boolean functions at the proper places. The ROM in Figure 5.1(a) can be replaced by a boolean function which calculates bn directly from the address an. Similarly, all but Mof the binary memory elements of the cyclic shift register in Figure 5.1(b) can be eliminated if a Boolean func- tion can be mechanized which, for all n, computes bnMfrom the stored val- ues bnj,j 0, 1, . . . ,M 1. The following two examples illustrate these procedures.
Example 5.1. A ROM-based generator for the sequence 1010110010110010
having period 16 can be specified as follows. For simplicity assume the address generator is a 4-bit binary counter producing consecutive addresses in the range 0 to 15, that is,
(5.2) where ( . . . )2is the binary representation of n. Table 5.1 identifies the map- ping which has to be accomplished by the ROM or its replacement function.
One possible implementation of this Boolean function is
(5.3) where and represent arithmetic modulo 2,being the EXCLUSIVE OR and being the AND logic functions. The resulting PN generator is shown in Figure 5.2.
bnan102an112#a
n122an122#a
n132
1an102an112an122an13222 nanan102an112#2a
n122#22a
n132#23
The Storage/Generation Problem 265
Figure 5.1. Sequence generators based on complete sequence storage.
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Notice that the function (5.3) in Example 5.1 is described in terms of two operations,and modulo 2, on the pair of elements 0 and 1. This struc- ture has all the mathematical properties of a field, and is usually referred to as the Galois field GF(2) of two elements. Complete mastery of the tech- niques used to design PN generators will require knowledge of the finite field GF(2) and of the larger finite fields containing GF(2), namely GF(q), where the number qof elements in the field is a power of 2. The reader is
266 Pseudonoise Generators
Table 5.1 Address-to-bit mapping
n bn
1 1 0 0 0 1
2 0 1 0 0 0
3 1 1 0 0 1
4 0 0 1 0 0
5 1 0 1 0 1
6 0 1 1 0 1
7 1 1 1 0 0
8 0 0 0 1 0
9 1 0 0 1 1
10 0 1 0 1 0
11 1 1 0 1 1
12 0 0 1 1 1
13 1 0 1 1 0
14 0 1 1 1 0
15 1 1 1 1 1
16 0 0 0 0 0
an132 an122
an112 an102
Figure 5.2. Counter-based PN generator.
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referred to Appendix 5A for a tutorial description of finite fields and their properties.
A completely specified Boolean function can be determined from tabu- lated values in at least two ways:
(a) The Quine-McClusky algorithm [1]—[3], applied to the completely spec- ified Boolean function of Table 5.1, will yield a minimum second-order realization of the function in terms of the logical operations AND, OR, and NEGATION.
(b) The sequences , each of length 2k, along with the all-ones sequence of length 2k, are the basis for a first-order Reed- Muller code [4]—[6]. Determination of the function described in Example 5.1 can be viewed as the result of decoding the 16-tuple, viewed as a codeword from a 4-th order Reed-Muller code of word length 16.
On the average, either of these techniques will produce rather complicated logical structures when applied to a random sequence of binary symbols. The expected number of terms in the resultant function determined by the Reed-Muller approach is half the sequence length. Hence, for a k-bit clock used to produce a randomly selected PN sequence of length 2k, one would expect on the average the necessary of 2k1multiple input AND gates and an EXCLUSIVE OR capable of handling 2k1inputs. Being optimal, one would expect the Quine-McCluskey approach to require somewhat fewer operations, but nevertheless, the expected number of operations probably will still be a linear function of the period 2k.
Although, on the average, the complexity of PN generators using counters is high, could there be a few exceptionally good designs of this type? There are strong reasons to believe that counters are always poor sources for inputs to functions generating PN sequences. First, the individual sequences have periods which are divisors of the desired period, and do not individu- ally have a “random appearance.” Furthermore, very few of the input sequences change value at any one time, i.e., changes every 2i-th bit, thereby forcing the use of rather complicated logic to emulate a PN sequence which, on the average, changes every other bit.
Example 5.2. The sequence
001100111010110111110
with period 21 has a particularly simple mechanization based on a shift reg- ister with feedback logic. Since all five-tuples (bn,bn1,bn2,bn3,bn4),n 1, 2, . . . , 21, are distinct, it follows that bn5can be determined uniquely from these previous five symbols. Hence, the designer must find a simple Boolean function which mechanizes the mapping shown in Table 5.2. One possible result, employing GF(2) arithmetic, is
(5.4) with the corresponding mechanization shown in Figure 5.3.
bn5bnbn1#b
n2
5an1i26
5an1i26 an1i2, i0, 1, 2,p, k1
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The approach to determining the feedback function in Example 5.2 can be identical to that used in Example 5.1. The fact that Table 5.2 is incom- plete, i.e., the Boolean function’s values are specified for only 21 of the 32 possible input binary 5-tuples, may yield some flexibility in the design process. Obviously, then, knowledge of the desired function in incomplete tabular form is not sufficient for determining the behavior of the PN gen- erator when its register is loaded with a 5-tuple not in the table. Using the
268 Pseudonoise Generators
Table 5.2 Feedback logic function
n bn bn1 bn2 bn3 bn4 bn5
1 0 0 1 1 0 0
2 0 1 1 0 0 1
3 1 1 0 0 1 1
4 1 0 0 1 1 1
5 0 0 1 1 1 0
6 0 1 1 1 0 1
7 1 1 1 0 1 0
8 1 1 0 1 0 1
9 1 0 1 0 1 1
10 0 1 0 1 1 0
11 1 0 1 1 0 1
12 0 1 1 0 1 1
13 1 1 0 1 1 1
14 1 0 1 1 1 1
15 0 1 1 1 1 1
16 1 1 1 1 1 0
17 1 1 1 1 0 0
18 1 1 1 0 0 0
19 1 1 0 0 0 1
20 1 0 0 0 1 1
21 0 0 0 1 1 0
Figure 5.3. A shift-register generator using feedback logic.
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implemented function (5.4), it can be seen that the device diagrammed in Figure 5.3 supports three other periodic sequences, namely 0 (period 1), 10000 (period 5), and 01010 (period 5). On the other hand, if the imple- mented function had the value 1 for each of the ten input 5-tuples missing from Table 5.2, the resulting device would support no other periodic sequences, and regardless of the initial register contents, the output sequence would eventually become the specified period 21 sequence.
Pseudonoise generators are similar to oscillators in the sense that they pro- vide an output signal but are not driven by an input signal, their next mem- ory state being a prescribed function of their present memory state. The period Nof the output sequence, therefore, is upper bounded by the num- ber of distinct states, that number being 2mwhen the memory is composed of mbinary storage elements. Hence, when implemented in binary, the min- imum number mof memory elements necessary to support period Noper- ation is given by
(5.5) where <x=denotes the smallest integer greater than or equal to x. If design- ing a PN generator for a specified, randomly selected sequence, using a shift register design with feedback logic as in Example 5.2, one can typically expect that the number of binary memory elements needed will be approx- imately twice the minimum number given by (5.5).
It is worth noting that the period of a sequence should be long enough to preclude the possibility that natural delays caused by multipath or artificial delays created by repeater jamming result in a signal delay of an integral number of periods. Such integral period delays could result in situations in which an SS receiver could not discriminate between the desired SS signal and the multipath or jammer interference. It is possible to size the minimum memory requirements needed to preclude this situation by evaluating (5.5).
As indicated by Table 5.3, it clearly is within the realm of possibility to achieve a practically non-repetitive PN generator with a modest investment in memory.
m <log21N2 =
The Storage/Generation Problem 269
Table 5.3
Memory requirements (measured in binary storage elements) for memory-efficient PN generators operating at 106or 109bits/sec.
Memory Memory Requirement Requirement
Period (106bits/sec) (109bits/sec)
1 second 20 30
1 minute 26 36
1 hour 32 42
1 day 37 47
1 year 45 55
1 century 52 62
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270 Pseudonoise Generators
Figure 5.4.A linear feedback shift register with feedforward logic.
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There do indeed exist shift registers which, along with a minimal amount of feedback logic, produce binary sequences possessing very large period and excellent pseudo-randomness properties. However, an extreme mea- sure of luck would be necessary to randomly pick a sequence producible by a generator possessing relatively simple structural properties; analytical techniques must be used to determine structures which will serve ade- quately as PN generators. The PN generators to be explored in this chap- ter all are variations of a linear-feedback shift register (LFSR) with non-linear feedforward output logic (see Figure 5.4). LFSRs are amenable to analysis, and provide a register through which flows a steady stream of pseudorandom bits. Non-linear feedforward logic is added for several rea- sons; it suffices to say that the effect of this addition is to make the struc- ture of the shift register difficult to determine rapidly from observations of the output sequence.