Computer Engineering – CSE – HCMUT Digital Design with the Verilog HDL Chapter 1: Digital Design Review Dr.. Phạm Quốc Cường 1 CuuDuongThanCong.com https://fb.com/tailieudientucntt...
Trang 1Computer Engineering – CSE – HCMUT
Digital Design with the Verilog HDL Chapter 1: Digital Design Review
Dr Phạm Quốc Cường
1
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Trang 2Technology Tradeoffs
2
Full-Custom IC
Non-Recurring Engineering (NRE) Cost Process complexity
Density, speed, complexity PLDs
Market Volume
to Amortize
Time to Prototype
Standard Cells FPGAs, Gate
Arrays
Trang 3Post-Synthesis Design Validation
Post-Synthesis Timing Verification
11
Extract Parasitics
13
Pre-Synthesis Sign-Off
Verilog-based
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Trang 4Combinational – Sequential Logic
• Combinational logic:
– The outputs at any time,
t, are a function of only
the inputs at time t
• Sequential logic:
– The outputs at time t are
a function of the inputs
at time t and the
Sequential Circuit
Trang 6nMos Pull-down network
Output Input
Invert gate NAND gate
NOR gate
Trang 7Parallel and Serial
a
b
0 1
a
b
1 0
a
b
1 1 OFF OFF OFF ON
a
b
0 1
a
b
1 0
a
b
1 1
ON OFF OFF OFF
(c)
a b
a b
OFF ON ON ON
a b 0
a b 1
a b
1
a b
0 0
a b 0
a b 1
a b
1
a b
7
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Trang 8The “Conduction Complement” Rule
• CMOS gate’s output is always either 0 or 1
• For example: NAND
– Y=0 if and only if both inputs are 1
– Y=1 if and only at least one input is 0
– pMos transistors are parallel while nMos transistors are
serial
• The “Conduction Complements” rule
– The pull-up network always complements the pull-down network
– Parallel → Serial, Serial → Parallel
8
A B
Y
Trang 12Y
Trang 13ON ON
OFF
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Trang 14OFF ON
ON
Trang 15ON OFF
OFF
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Trang 16OFF OFF
ON
Trang 1818
3-input NAND Gate
• Y is 0 if and only if ALL inputs are 1
• Y is 1 if and only if AT LEAST one input is 0
A B
Y
C
Trang 1919
Design CMOS Gates
– Using the CMOS Technology, draw transistor structure of
a 4-input NOR gate
A B C
D
Y
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Trang 20Design CMOS Gate (cont.)
– Using the CMOS Technology, draw transistor structure of
a 4-input NAND gate
20
Trang 22Example: AOI22
Y =
22
A B
C D
A B
C D
B D Y A
C
A C
A B
C D
B D
) ( A • B + C • D
Trang 24Example: O3AI
24
Y C
D
D C
B A
D C
B A
Trang 2525
Standard Cells
• Library of common gates and structures (cells)
• Decompose hardware in terms of these cells
• Arrange the cells on the chip
• Connect them using metal wiring
…
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Trang 2626
FPGAs
• “Programmable” hardware
• Use small memories as truth tables of functions
• Decompose circuit into these blocks
• Connect using programmable routing
• SRAM bits control functionality
P
P1 P2 P3 P4 P5 P6 P7 P8
I1 I3 I2
OUT
FPGA Tiles