Tài liệu Semiconductor Memories doc

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Digital Integrated Circuits

A Design Perspective

Semiconductor Memories

Jan M Rabaey Anantha Chandrakasan Borivoje Nikolic

December 20, 2002

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Semiconductor Memory Classification

Read-Write Memory Non-Volatile Read-Write

Memory

Read-Only Memory

EPROM

E2PROMFLASH

Random Access

Non-Random Access

SRAM DRAM

Mask-ProgrammedProgrammable (PROM)FIFO

Shift RegisterCAMLIFO

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Memory Timing: Definitions

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Memory Architecture: Decoders

Word 0 Word 1 Word 2

WordN22 WordN21

Storage cell

WordN22 WordN21

Storage cell

S0

Input-Output

(M bits)

Intuitive architecture for N x M memory

Too many select signals:

N words == N select signals K = log 2 N

Decoder reduces the number of select signals

Input-Output

(M bits)

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Array-Structured Memory Architecture

Problem: ASPECT RATIO or HEIGHT >> WIDTH

Amplify swing to rail-to-rail amplitude

Selects appropriate word

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Hierarchical Memory Architecture

Advantages:

1 Shorter wires within blocks

2 Block address activates only 1 block => power savings

Global amplifier/driver

Control circuitry

Global data bus Block selector

Block 0 Row

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Block Diagram of 4 Mbit SRAM

Clock generator

CS, WE buffer bufferI/O controllerx1/x4 Y-addressbuffer X-addressbuffer

Z-address

buffer X-addressbuffer

Predecoder and block selector

Bit line load

Transfer gate Column decoder Sense amplifier and write driver

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Memory Timing: Approaches

DRAM Timing Multiplexed Adressing SRAM Timing Self-timed

Address transition initiates memory operation Address

Column Address

CAS

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Read-Only Memory Cells

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MOS OR ROM

WL[0]

V DD BL[0]

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MOS NOR ROM

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MOS NOR ROM Layout

Programmming using the Active Layer Only

PolysiliconMetal1DiffusionMetal1 on Diffusion

Cell (9.5 x 7)

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MOS NOR ROM Layout

PolysiliconMetal1DiffusionMetal1 on Diffusion

Cell (11 x 7)

Programmming using the Contact Layer Only

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MOS NAND ROM

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MOS NAND ROM Layout

No contact to VDD or GND necessary;

Loss in performance compared to NOR ROM drastically reduced cell size

PolysiliconDiffusionMetal1 on Diffusion

Cell (8 x 7)

Programmming using the Metal-1 Layer Only

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NAND ROM Layout

Cell (5 x 6)

Polysilicon

Threshold-alteringimplant

Metal1 on Diffusion

Programmming using Implants Only

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Equivalent Transient Model for MOS NOR ROM

 Word line parasitics

 Wire capacitance and gate capacitance

 Wire resistance (polysilicon)

 Bit line parasitics

 Resistance not dominant (metal)

 Drain and Gate-Drain capacitance

C bit

r word

c word WL

BL

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Equivalent Transient Model for MOS NAND ROM

 Word line parasitics

 Similar to NOR ROM

 Bit line parasitics

 Resistance of cascaded transistors dominates

 Drain/Source and complete gate capacitance

Model for NAND ROM

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Decreasing Word Line Delay

(b) Using a metal bypass

(a) Driving the word line from both sides

Metal word line

WL

(c) Use silicides

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Precharged MOS NOR ROM

PMOS precharge device can be made as large as necessary,

but clock driver becomes harder to design.

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Non-Volatile Memories

The Floating-gate transistor (FAMOS)

Floating gate Source

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Floating-Gate Transistor Programming

0 V

D S

Removing programming voltage leaves charge trapped

5 V

D S

Avalanche injection

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 2 transistor cell

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n1source programming n1drain

Many other options …

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Cross-sections of NVM cells

EPROM Flash

Courtesy Intel

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Basic Operations in a NOR Flash Memory― Erase

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Basic Operations in a NOR Flash Memory― Write

12 V

6 V G

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Basic Operations in a NOR Flash Memory― Read

5 V

1 V G

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NAND Flash Memory

FG Gate

Oxide

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NAND Flash Memory

Word lines Select transistor

Bit line contact Source line contact Active area

STI

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Characteristics of State-of-the-art NVM

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Read-Write Memories (RAM)

Periodic refresh required Small (1-3 transistors/cell) Slower

Single Ended

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6-transistor CMOS SRAM Cell

Q Q

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CMOS SRAM Analysis (Read)

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CMOS SRAM Analysis (Read)

0 0 0.2 0.4 0.6 0.8 1 1.2

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CMOS SRAM Analysis (Write)

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CMOS SRAM Analysis (Write)

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6T-SRAM — Layout

VDD

GND

QQ

WL

BLBL

M1 M3

M4 M2

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Resistance-load SRAM Cell

Static power dissipation Want RL large Bit lines precharged to VDD to address tp problem

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SRAM Characteristics

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3-Transistor DRAM Cell

No constraints on device ratios Reads are non-destructive

Value stored at node X when writing a “1” = V WWL -V Tn

BL1 X RWL WWL

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M1

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1-Transistor DRAM Cell

Write: C S is charged or discharged by asserting WL and BL.

Read: Charge redistribution takes places between bit line and storage capacitance

Voltage swing is small; typically around 250 mV.

sensing BL

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DRAM Cell Observations

 1T DRAM requires a sense amplifier for each bit line, due

to charge redistribution read-out.

 DRAM memory cells are single ended in contrast to

SRAM cells.

 The read-out of the 1T DRAM cell is destructive; read

and refresh operations are necessary for correct

operation.

 Unlike 3T cell, 1T cell requires presence of an extra

capacitance that must be explicitly included in the design.

 When writing a “1” into a DRAM cell, a threshold

voltage is lost This charge loss can be circumvented by bootstrapping the word lines to a higher value than VDD

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Sense Amp Operation

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1-T DRAM Cell

Uses Polysilicon-Diffusion Capacitance

Expensive in Area

M 1 word line

Diffused bit line

Polysilicon gate

Polysilicon plate

n+ n+

Inversion layer induced by plate bias Poly

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SEM of poly-diffusion capacitor 1T-DRAM

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Advanced 1T DRAM Cells

Isolation Transfer gate

Storage electrode

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Static CAM Memory Cell

CAM

Bit Word

Bit

••• CAM Bit Bit

CAM Word

Wired-NOR Match Line

M2

M7 M6

M3 int S

Word

••• CAM

S

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CAM in Cache Memory

CAM

ARRAY

Input Drivers

Tag Hit Address

SRAM

ARRAY

Sense Amps / Input Drivers

Data R/W

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Multi-stage implementation improves performance

NAND decoder using 2-input pre-decoders

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4-input pass-transistor based column

decoder

Advantages: speed (t pd does not add to overall memory access time)

Only one extra transistor in signal path

Disadvantage: Large transistor count

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4-to-1 tree based column decoder

Number of devices drastically reduced Delay increases quadratically with # of sections; prohibitive for large decoders

buffers progressive sizing Solutions:

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Decoder for circular shift-register

f

• • •

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Idea: Use Sense Amplifer

output input

s.a.

small transition

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Differential Sense Amplifier

Directly applicable to SRAMs

SE

Out y

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Differential Sensing ― SRAM

SE

Output SE

x

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Latch-Based Sense Amplifier (DRAM)

Initialized in its meta-stable point with EQ

Once adequate voltage gap created, sense amp enabled with SE

Positive feedback quickly forces output to a stable operating point.

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Charge-Redistribution Amplifier

0.5 1.0 1.5 2.0 2.5

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Column decoder

EPROM array

BL WL

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Open bitline architecture with

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DRAM Read Process with Dummy Cell

3 2 1

0

0 1 2 3

BL BL

t (ns)

reading 0

3 2 1

0

0 1 2 3

BL BL

t (ns)

reading 1

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Voltage Regulator

+

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DRAM Timing

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RDRAM Architecture

memory array

Data bus Clocks

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Address Transition Detection

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Reliability and Yield

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Sensing Parameters in DRAM

From [Itoh01]

4K

101001000

64K 1M 16M 256M 4G 64GMemory Capacity (bits/chip)

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Noise Sources in 1T DRam

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Open Bit-line Architecture —Cross Coupling

Sense Amplifier C

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Folded-Bitline Architecture

Sense Amplifier C

WL1

C C

WL D

BL C BL

EQ x

x

y

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Transposed-Bitline Architecture

SA

Ccross

(a) Straightforward bit-line routing

(b) Transposed bit-line architecture

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Alpha-particles (or Neutrons)

1 Particle ~ 1 Million Carriers

WL BL

22222

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Yield

Yield curves at different stages of process maturity(from [Veendrick92])

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MemoryArray

Column Decoder

Redundantrows

Redundant

columns

RowAddress

ColumnAddress

FuseBank:

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= 3

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Redundancy and Error Correction

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Sources of Power Dissipation in

Memories

PERIPHERY

ROW DEC

selected

non-selected CHIP

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Data Retention in SRAM

1.30u 1.10u 900n 700n 500n 300n 100n

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Suppressing Leakage in SRAM

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Data Retention in DRAM

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Case Studies

 Programmable Logic Array

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PLA versus ROM

structured approach to random logic

“two level logic implementation”

NOR-NOR (product of sums) NAND-NAND (sum of products) IDENTICAL TO ROM!

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Programmable Logic Array

GND

GND GND

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Clock Signal Generation

for self-timed dynamic PLA

(a) Clock signals (b) Timing generation circuitry

Dummy AND row

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4 Mbit SRAM

Hierarchical Word-line Architecture

Global word line

Sub-global word line

Block 0

•••

Localword line

Block 1

•••

Block 2

•••

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Bit-line Circuitry

Bit-line load

Block select ATD

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Sense Amplifier (and Waveforms)

BS I/O I /O

DATA

Block select ATD

SEQ

DATA

Vdd GND

SA, SA Vdd GND

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1 Gbit Flash Memory

Sense Latches(10241 32)3 8

Data Caches(10241 32)3 8

Sense Latches (10241 32)3 8 Data Caches (10241 32)3 8

Block0Block1023Bit Line Control CircuitBLT1

I/O

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Writing Flash Memory

(a) 3V 4V

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125mm 2 1Gbit NAND Flash Memory

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 Technology 0.13m p-sub CMOS triple-well

1poly, 1polycide, 1W, 2Al

 Program time 200s / page

 Erase time 2ms / block

 Technology 0.13m p-sub CMOS triple-well

1poly, 1polycide, 1W, 2Al

 Program time 200s / page

 Erase time 2ms / block

From [Nakamura02]

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Semiconductor Memory Trends

(up to the 90’s)

Memory Size as a function of time: x 4 every three years

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(updated)

From [Itoh01]

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Trends in Memory Cell Area

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Technology feature size for different SRAM generations

Tiêu đề	Semiconductor Memories
Tác giả	Jan M. Rabaey, Anantha Chandrakasan, Borivoje Nikolic
Trường học	Digital Integrated Circuits
Chuyên ngành	Semiconductor Memories
Thể loại	Tài liệu
Năm xuất bản	2002

Định dạng
Số trang	107
Dung lượng	5 MB