Tài liệu ime Control of a Three Phase 4 Wire PWM Inverter with Variable DC Link Voltage and Battery Storage for PV Application doc

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Figure 2 It c

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contains the

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nk control is

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discrete sys

Figure

trol strategy

s in [1], [2],

or three phas current min control loop

s intended si

f the VSI is stem in the sy

e 2 principle

for single ph [3], [5] and

se 4 wire VS nor loop, volt

p Here only ince to descr designed in ynchronized

,

e of the cont

hase inverter [7], the dead

SI The contr tage major lo

y a brief desc ribe them in the synchro

d dq0 frame.

(1)

(2)

,

trol method

r was discus

d beat contro rol proposed oop, the DC cription of th details will

onized dq0 fr

,

,

ssed in [4], [6

ol in [1] and

d of the VSI i

C link referen

he current an exceed the l rame Equati

6] and [8] an [2] is adopte

is illustrated nce estimatio

nd voltage as imits of the ion (1) and (

nd

ed

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on

s (2)

F

t

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Equation (3)

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by the matrix

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beat controll

Figure 3

,

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(4)

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op

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)

ch other whe pacitor volta

ments b and d

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ngs are need

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tain referenc

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) The digita

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ctor

ply the load implemented

oad current is

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/DC converte

al control is i which is given

current IL to

d, as shown

s provided a ucted in the s rrents and vo

er in the con implemented

n by

o compensate

in figure 2,

and thus the c same manner oltages excep

ntinuos cond

d [11] so tha

(8)

e the disturb

so that the p

computation

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pt that, in the

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at the DC lin

(7)

ance of the l predicted loa

(6)

n time delay dead beat

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nk voltage wi

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d

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Figure

Figure 4 sho

dc link volta

linear region

the output fi

controlled I

(Ru=Rv=60Ω

sub diagram

as the distur

reduces grad

diagram

4 inverter c

(R u =

ows the simu

age The dist

n of the PWM

ilter is also d

It shows the

Ω , Rw=2000

m This show

rbance of the

dually as a re

current and

=R v =20Ω ,R w

ulation result tortion in the

M modulator distorted Fig capacitor vo 0Ω ) to (Ru=R

s the high dy

e output volt esult of the c

capacitor vo

w =2000Ω ) a

ts of the dea

e inverter cu

r due to load gure 5 shows oltage of the Rv=20Ω , Rw ynamic perfo age is quick controllable

oltage of the and uncontro

ad beat contro urrents occur

d unbalances

s the simulat output filter w=2000Ω ) a ormance of t kly compensa

dc link volta

e output filte olled DC lin

ol for unbala

r when the co

s As a result tion results w

r when the lo

as indicated b the introduce ated The dis age as indica

er with unba

nk voltage

anced load w ontrol signal

t, the capacit when the DC oad changes

by an arrow

ed dead beat stortion of th ated in the ri

alanced load

with uncontro

ls exceed the tor voltage o C-link voltag from

in the lift ha

t control met

he output vol ight hand sub

d

olled

e

of

ge is and thod ltage

b

Figure 5 5 capacitor v voltage of the output filt

vo

ter with unb oltage

alanced load d and contro olled DC lin nk

Figure 6 DC link Voltage

Diagram 6 shows the dc link voltage when the load changes and distortion in the output voltage occurs The dc link voltage increases to reduce the output voltage distortion The oscillations in the

dc link voltage are due to the filter effect in the DC link reference estimation given by equation (8) However; the oscillation portion is relatively small compared to the dc voltage portion, so that it does not affect the output voltage

[1] Takao Kawabata, Takeshi Miyashita and Yushin Yamamoto, "Digital Control of three-Phase Inverter with LC Filter", IEEE Transactions on Power Electronics, Vol 6, No 1, January 1991, pp 62-72

[2] Takao Kawabata, Takeshi Miyashita and Yushin Yamamoto, "Dead Beat Control of three-Phase PWM Inverter", IEEE Transactions on Power Electronics, Vol 5, No 1, January 1990, pp 21-28

[3] Osman Kükrer, "Deadbeat Control of a Three-Phase Inverter with an Output LC Filter", IEEE Transactions on Power Electronics, Vol 11, No 1, January 1996, pp 16-23

[4] Chihchiang Hua and Richard G Hoft, "Hight Performance Deadbeat Controlled PWM

Inverter using a Current Source Compensator for nonlinear loads", IEEE/PESC 23rd Anual, Toledo, Spain 1992, pp 443-450

[5] Tomoki Yokoyama and Atsuo Kawamura, "Disturbance Observer Based Fully Digital

Controlled PWM Inverter for CVCF Operation", IEEE Transactions on Power Electronics, Vol 9,

No 5, September 1994, pp 473-480

[6] Atsuo Kawamura and Tomoki Yokoyama, "Comparison of Five Control Methods for Digitally Feedback Controlled PWM Inverters", EPE Firenze 1991, Vol 2, pp 35-40

[7] Youichi Ito and Shoichi Kawauchi, "Microprocessor-Based Robust Digital Control for UPS with Three -Phase PWM Inverter", IEEE Transactions on Power Electronics, Vol 10, No 2, March

1995, pp 196-204

[8] Atsuo Kawamura, Toshimasa Haneyoshi and Richard G Hoft, "Deadbeat Controlled PWM Inverter with Parameter Estimation Using Only Voltage Sensor", IEEE Transactions on Power Electronics, Vol 3, No 2, April 1988, pp 118-125

[9] P R K Chetty "Current Injected Equivalent Circuit Approach to Modeling and Analysis of Current Programmed Switching DC-DC Converters (Discontinuous Inductor Conduction Mode)", IEEE Transactions on Industrial Applications, Vol IA-18, No 3, May/June 1982, pp 295-299 [10] Francisco Guinjoan, Javier Calvente, Alberto Poveda and Luis Martinez, "Large-Signal Modeling and Simulation of Switching DC-DC Converter", IEEE Transactions on Power

Electronics, Vol 12, No 3, May 1997, pp 485-494

[11] F Al-Hosini, ABB Corporate Research, Sweden, "An Aproximate Dead-Beat Control stratigy for the disign of functions regulators in DC/DC Converters", EPE Trondheim 1997, Vol 3,

pp 155-160