cmos analog integrated circuits amplifers comparators multipliers filters and oscillators pdf

76 Bibliography 81 3 Bias and Current Reference Circuits 83 3.1 Current mirrors.. Advances in packaging technologywill be required to support high-performance ICs.Chapter 3 Bias and Curr

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Preface xi

New to this edition xii

Content overview xii

Acknowledgments xiv

1 MOS Transistors 1 1.1 Transistor structure 2

1.1.1 I-V characteristics of MOS transistors 3

1.1.2 Drain current in the strong inversion approximation 4 1.1.3 Drain current in the subthreshold region 7

1.1.4 MOS transistor capacitances 10

1.1.5 Scaling eﬀects on MOS transistors 12

1.2 Transistor SPICE models 13

1.2.1 Electrical characteristics 13

1.2.2 Temperature eﬀects 19

1.2.3 Noise models 20

1.3 Drain-source current valid in all regions of operation 23

1.4 Small-geometry eﬀects 32

1.5 Design-oriented MOSFET models 34

1.5.1 Small-signal transconductances 37

1.5.2 Transistor parameters in various CMOS technologies 37 1.5.3 Capacitances 38

1.6 Summary 48

1.7 Circuit design assessment 48

Bibliography 55 2 Physical Design of MOS Integrated Circuits 57 2.1 MOS transistors 58

2.1.1 MOS ﬁeld-eﬀect transistor 58

2.1.2 Fin ﬁeld-eﬀect transistor 59

2.2 Passive components 61

2.2.1 Capacitors 61

2.2.2 Resistors 64

2.2.3 Inductors 65

2.3 Integrated-circuit (IC) interconnects 67

v

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2.4 Physical design considerations 69

2.5 IC packaging 75

2.6 Summary 75

Bibliography 81 3 Bias and Current Reference Circuits 83 3.1 Current mirrors 84

3.1.1 Simple current mirror 84

3.1.2 Cascode current mirror 86

3.1.3 Low-voltage active current mirror 99

3.2 Current and voltage references 100

3.2.1 Supply-voltage independent current and voltage refe-rences 103

3.2.2 Bandgap references 107

3.2.2.1 Low-voltage bandgap voltage reference 110

3.2.2.2 Curvatucompensated bandgap voltage re-ference 112

3.2.3 Floating-gate voltage reference 114

3.3 Summary 116

Bibliography 125 4 CMOS Amplifiers 127 4.1 Diﬀerential ampliﬁer 128

4.1.1 Dynamic range 129

4.1.2 Source-coupled diﬀerential transistor pair 131

4.1.3 Current mirror 133

4.1.4 Slew-rate limitation 134

4.1.5 Small-signal characteristics 135

4.1.6 Oﬀset voltage 140

4.1.7 Noise 143

4.1.8 Operational ampliﬁer 145

4.2 Linearization techniques for transconductors 148

4.3 Transconductor operating in the subthreshold region 163

4.4 Single-stage ampliﬁer 165

4.5 Folded-cascode ampliﬁer 167

4.6 Fully diﬀerential ampliﬁer architectures 172

4.6.1 Fully diﬀerential folded-cascode ampliﬁer 172

4.6.1.1 Basic structure 172

4.6.1.2 Gain-enhanced structure 175

4.6.2 Telescopic ampliﬁer 180

4.6.3 Common-mode feedback circuits 183

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4.6.3.1 Continuous-time common-mode feedback

circuit 185

4.6.3.2 Switched-capacitor common-mode feedback circuit 189

4.6.4 Pseudo fully diﬀerential ampliﬁer 192

4.7 Multistage ampliﬁer structures 194

4.7.1 Output stage 195

4.7.2 Two-stage ampliﬁer 206

4.7.3 Optimization of a two-pole ampliﬁer for fast settling response 213

4.7.4 Three-stage ampliﬁer 216

4.8 Rail-to-rail ampliﬁers 231

4.8.1 Ampliﬁer with a class AB input stage 232

4.8.2 Two-stage ampliﬁer with class AB output stage 235

4.8.3 Ampliﬁer with rail-to-rail input and output stages 235

4.9 Ampliﬁer characterization 239

4.9.1 Finite gain and bandwidth 239

4.9.2 Phase margin 240

4.9.3 Input and output impedances 240

4.9.4 Power-supply rejection 240

4.9.5 Slew rate 241

4.9.6 Low-frequency noise and dc oﬀset voltage 242

4.9.6.1 Auto-zero compensation scheme 245

4.9.6.2 Chopper technique 248

4.10 Summary 253

Bibliography 275 5 Nonlinear Analog Components 281 5.1 Comparators 282

5.1.1 Ampliﬁer-based comparator 282

5.1.2 Comparator using charge balancing techniques 289

5.1.3 Latched comparators 290

5.1.3.1 Static comparator 291

5.1.3.2 Dynamic comparator 295

5.2 Multipliers 307

5.2.1 Multiplier cores 309

5.2.1.1 Multiplier core based on externally controlled transconductances 310

5.2.1.2 Multiplier core based on the quarter-square technique 315

5.2.1.3 Design issues 322

5.2.2 Design examples 322

5.3 Summary 325

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Bibliography 335 6 Continuous-Time Circuits 339 6.1 Wireless communication system 340

6.1.1 Receiver and transmitter architectures 342

6.1.2 Frequency translation and quadrature multiplexing 345

6.1.3 Architecture of a harmonic-rejection transceiver 351

6.1.4 Ampliﬁers 352

6.1.4.1 Power ampliﬁer 353

6.1.4.2 Low-noise ampliﬁer 362

6.1.5 Mixer 374

6.1.6 Voltage-controlled oscillator 377

6.1.7 Automatic gain control 394

6.2 Continuous-time ﬁlters 401

6.2.1 RC circuits 403

6.2.2 MOSFET-C circuits 405

6.2.3 gm-C circuits 407

6.2.4 gm-C operational ampliﬁer (OA) circuits 409

6.2.5 Summer circuits 412

6.2.6 Gyrator 413

6.3 Filter characterization 415

6.4 Filter design methods 416

6.4.1 First-order ﬁlter design 418

6.4.2 Biquadratic ﬁlter design methods 420

6.4.2.1 Signal-ﬂow graph-based design 420

6.4.2.2 Gyrator-based design 423

6.4.3 Ladder ﬁlter design methods 426

6.4.3.1 LC ladder network-based design 426

6.4.3.2 Signal-ﬂow graph-based design 430

6.5 Design considerations for continuous-time ﬁlters 434

6.5.1 Automatic on-chip tuning of continuous-time ﬁlters 434

6.5.2 Nonideal integrator 435

6.6 Frequency-control systems 437

6.6.1 Phase-locked-loop-based technique 437

6.6.1.1 Operation principle 437

6.6.1.2 Architecture of the master: VCO or VCF 438

6.6.1.3 Phase detector 438

6.6.1.4 Implementation issues 439

6.6.2 Charge comparison-based technique 440

6.7 Quality-factor and bandwidth control systems 442

6.7.1 Magnitude-locked-loop-based technique 442

6.7.2 Envelope detection-based technique 444

6.8 Practical design considerations 448

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6.9 Other tuning strategies 450

6.9.1 Tuning scheme using an external resistor 450

6.9.2 Self-tuned ﬁlter 451

6.9.3 Tuning scheme based on adaptive ﬁlter technique 453

6.10 Summary 456

Bibliography 479 7 Switched-Capacitor Circuits 487 7.1 Anti-aliasing ﬁlter 488

7.2 Capacitors 490

7.3 Switches 491

7.3.1 Switch description 491

7.3.2 Switch error sources 493

7.3.3 Switch compensation techniques 497

7.4 Programmable capacitor arrays 499

7.5 Operational ampliﬁers 500

7.6 Track-and-hold (T/H) and sample-and-hold (S/H) circuits 502 7.6.1 Open-loop T/H circuit 508

7.6.2 Closed-loop T/H circuits 510

7.7 Switched-capacitor (SC) circuit principle 511

7.8 SC ﬁlter design 517

7.8.1 First-order ﬁlter 518

7.8.2 Biquad ﬁlter 519

7.8.3 Ladder ﬁlter 527

7.9 SC ladder ﬁlter based on the LDI transform 528

7.10 SC ladder ﬁlter based on the bilinear transform 537

7.10.1 RLC ﬁlter prototype-based design 537

7.10.2 Transfer function-based design of allpass ﬁlters 543

7.11 Effects of the amplifier finite gain and bandwidth 546

7.11.1 Ampliﬁer dc gain 547

7.11.2 Ampliﬁer ﬁnite bandwidth 550

7.11.2.1 Inverting integrator 550

7.11.2.2 Noninverting integrator 552

7.12 Settling time in the integrator 553

7.13 Ampliﬁer dc oﬀset voltage limitations 556

7.14 Computer-aided analysis of SC circuits 556

7.15 T/H and S/H circuits based on the SC circuit principle 560

7.16 Circuit structures with low sensitivity to nonidealities 565

7.16.1 Integrators 566

7.16.2 Gain stages 572

7.17 Low supply voltage SC circuits 577

7.18 Summary 581

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Bibliography 593

A.1 MOS transistor 600

A.2 Ampliﬁer 604

A.3 Comparator and latch 615

A.4 Transistor sizing based on the gm/ID methodology 618

A.5 Bibliography 633

Appendix B Signal Flow Graph 635 B.1 SFG reduction rules 636

B.2 Mason’s gain formula 637

B.3 Bibliography 640

Appendix C Notes on Track-and-Hold Circuit Analysis 641 C.1 T/H transfer function 641

C.2 Bibliography 644

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Since the publication of the ﬁrst edition of the book, CMOS Analog IntegratedCircuits, the complementary metal-oxide semiconductor (CMOS) process usedfor the fabrication of integrated circuits has been constantly scaled down Cur-rent nanometer CMOS processes have the advantages of increasing the chipdensity and circuit speed, and reducing the power supply voltage However,signiﬁcant challenges (leakage currents, variability of technological parame-ters) for the analog circuit design can be related to the use of the nanometerCMOS process, especially below 65 nm They will only be tackled by usingappropriate analog synthesis techniques and computer-aided design tools atthe circuit and physical levels.

Hardware developments have been a major vehicle in popularizing the plications of signal processing theory in both science and engineering Thebook describes the important trends of designing high-speed and power-eﬃcient front-end analog circuits, which can be used alone or to interfacemodern digital signal processors and micro-controllers in various applicationssuch as multimedia, communication, instrumentation, and control systems.The book contains resources to allow the reader to design CMOS analogintegrated circuits with improved electrical performance It oﬀers a completeunderstanding of architectural- and transistor-level design issues of analogintegrated circuits It provides a comprehensive, self-contained, up-to-date,and in-depth treatment of design techniques, with an emphasis on practicalaspects relevant to integrated circuit implementations

ap-Starting from an understanding of the basic physical behavior and ing of MOS transistors, we review design techniques for more complex com-ponents such as amplifiers, comparators, and multipliers The book detailsall aspects from specifications to the final chip related to the developmentand implementation process of filters, analog-to-digital converters (ADCs)and digital-to-analog converters (DACs), phase-locked loops (PLLs) and de-lay locked loops (DLLs) It provides analyses of architectures and performancelimitation issues affecting the circuit operation The focus is on designing andverifying analog integrated circuits

model-The book is intended to serve as a text for the core courses in analogintegrated circuits and as a valuable guide and reference resource for analogcircuit designers and graduate students in electrical engineering programs Itprovides balanced coverage of both theoretical and practical issues in hierar-chically organized format With easy-to-follow mathematical derivations of allequations and formulas, the book also contains graphical plots, and a number

xi

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of open-ended design problems to help determine the most suitable circuit chitecture satisfying a given set of performance speciﬁcations To appreciatethe material in this book, it is expected that the reader has a rudimentaryunderstanding of semiconductor physics, electronics, and signal processing.

ar-New to this edition

Every chapter in the second edition has been revised to reﬂect the tion of modern CMOS process technology Furthermore, the text emphasizesparadigms that needed to be mastered and covers new material such as:

evolu-1 MOS transistor short channel eﬀects and capacitor modeling

2 Transistor sizing based on the gm/ID methodology

3 Temperature compensation of voltage and current references

4 Frequency compensation of three-stage operational ampliﬁers

5 Comparator design based on settling time speciﬁcation

6 Analysis of track-and-hold circuits

Chapter 2

Physical Design of MOS Integrated Circuits

Physical design and fabrication considerations for high-density circuits (ICs) in deep-submicrometer processes are reviewed In addition toconsidering RLC models for the interconnect and package parasitic compo-nents, it appears also necessary to take into account the coupling through the

integrated-www.TechnicalBooksPDF.com

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common substrate during the IC design Advances in packaging technologywill be required to support high-performance ICs.

Chapter 3

Bias and Current Reference Circuits

Circuit structures for the design of current mirrors (current sources and sinks)and voltage references are reviewed Generally, the eﬀects of the IC processand power supply variations on these basic blocks should be minimized toimprove the overall performance of a device Current mirrors are used in avariety of circuit building blocks to copy or scale a reference current, whilevoltage references are required to set an accurate and stable voltage for bias-ing circuits irrespective of ﬂuctuations of the supply voltage and changes inoperating temperature

Chapter 4

CMOS Amplifiers

Topologies of amplifiers, which are suitable for the design of analog circuits,are described The factors determining the nonideal behavior of an amplifiercircuit are considered To be tailored for a given application, an architecturehas to meet the trade-off requirement among the different specifications, such

as gain, bandwidth, phase margin, signal swing, noise, and slew rate Designmethods, which result in the optimization of speciﬁc performance character-istics, are summarized

Chapter 5

Nonlinear Analog Components

Circuit architectures for comparators and multipliers are reviewed Theoreticalanalysis is carried out for design and optimization purposes The performances

of comparators are essentially limited by the switching speed and mismatches

of transistor characteristics, resulting in voltage oﬀsets, while the main itations aﬀecting the operation of multipliers are nonlinear distortions Thedesign challenge is to meet the requirements of low-voltage and low-powercircuits

lim-Chapter 6

Continuous-Time Circuits

Continuous-time circuits are required to interface digital signal processors toreal-world signals They are based on components such as transistors, resistors,capacitors, and inductors The choice of an architecture and design techniquedepends on the performance parameters and application frequency range Theuse of inductors, which can only be integrated with moderate eﬃciency (lowquality factor, parasitic elements) in CMOS processes, is restricted to high-frequency building blocks with tuned characteristics Using active components(transistor and operational ampliﬁer) and capacitors, MOSFET-C and Gm-Cstructures have proven reliable for the design of integrated circuits in the video

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frequency (or MHz) range.

Chapter 7

Switched-Capacitor Circuits

Switched-capacitor circuits are used in the design of large-scale integratedsystems They are based on basic building blocks such as sample-and-hold,integrator, and gain stage, which can be optimized to meet the requirements

of low power consumption and chip area Design techniques, which result inthe minimization of the circuit sensitivity to component imperfections, aredescribed Accurate switched-capacitor ﬁlters are obtained by performing thesynthesis in the z-domain, and using stray insensitive circuits for the imple-mentation of the resulting signal-ﬂow graph

Appendices

Three appendices cover the following topics:

Appendix A: Transistor Sizing in Building Blocks

Appendix B: Signal Flow Graph

Appendix C: Notes on Track-and-Hold Circuit Analysis

Acknowledgments

Many of the changes in this edition were made in response to feedback receivedfrom some readers of the ﬁrst edition I would like to thank all those who tookthe time to send me messages

I am grateful for the support of colleagues and students whose remarkshelped reﬁne the content of this book

I would like to thank Prof Dr.-Ing h.c R Unbehauen Nuremberg University, Germany) His continuing support, the discussions Ihad with him, and the comments he made have been very useful

(Erlangen-I express my sincere gratitude for all the support and spontaneous help (Erlangen-Ireceived from Dr Fa-Long Luo (Element CXI, USA)

I wish to acknowledge the suggestions and comments provided by Prof.Avebe Zibi (UY-I, CM) and Prof Emmanuel Tonye (ENSP, CM) during theearly phase of this project

While doing this work, I received much spontaneous help from some ternational experts: Prof Ramesh Harjani (University of Minnesota, Min-neapolis, Minnesota), Prof Antonio Petraglia (Universidade Federal do Rio

in-de Janeiro, Brazil), Dr Schmid Hanspeter (Institute of Microelectronics,Windisch, Switzerland), Prof Sanjit K Mitra (University of California, SantaBabara, California), and Prof August Kaelin (Siemens Schweiz AG, Zurich,Switzerland) I would like to express my thanks to all of them

I am also indebted to the publisher, Nora Konopka, the project

coordi-www.TechnicalBooksPDF.com

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nator, Kyra Lindholm, the production editor, Michele Dimont, and the CRCPress editorial team of the previous edition, Jessica Vakili, Karen Simon, Brit-tany Gilbert, Stephany Wilken, Christian Munoz, and Shashi Kumar, for theirvaluable comments and reviews at various stages of the manuscript prepara-tion, and their quality production of the book.

Finally, I would like to truly thank all members of my family and friendsfor the continual love and support they have given during the writing of thisbook

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MOS Transistors

CONTENTS

1.1 Transistor structure 2

1.1.1 I-V characteristics of MOS transistors 3

1.1.2 Drain current in the strong inversion approximation 4

1.1.3 Drain current in the subthreshold region 7

1.1.4 MOS transistor capacitances 10

1.1.5 Scaling effects on MOS transistors 12

1.2 Transistor SPICE models 13

1.2.1 Electrical characteristics 13

1.2.2 Temperature effects 19

1.2.3 Noise models 20

1.3 Drain-source current valid in all regions of operation 23

1.4 Small-geometry effects 32

1.5 Design-oriented MOSFET models 34

1.5.1 Small-signal transconductances 37

1.5.2 Transistor parameters in various CMOS technologies 37

1.5.3 Capacitances 38

1.6 Summary 48

In almost all modern electronic circuits, transistors are the key active element

By reducing the dimensions of MOS transistors and the wires connecting them in integrated circuits (ICs), it has been possible to increase the density and complexity of integrated systems.Figure 1.1illustrates the reduction in feature size over time It is expected that a chip designed in a 35-nm IC process will include more than 1011 transistors in a few years [1] But up to now, the scaling progress was essentially attributed to the improvements in manufacturing technology However, as the physical limits are being met, some changes to the device structures and new materials will be necessary Next,

we will describe the transistor structure and the diﬀerent equivalent models that are generally used for simulations

1

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Structures of MOS transistors are shown inFigure 1.2 The drain and source

of the nMOS transistor (seeFigure 1.2(a)) are realized by two heavily dopedn-type semiconductor regions, which are implanted into a lightly doped p-typesubstrate or bulk A thin layer of silicon dioxide (SiO2) is thermally grown overthe region between the source and drain, and is covered by a polycrystallinesilicon (also called polysilicon or poly), which forms the gate of the transistor.The thickness tox of the oxide layer is on the order of a few angstroms Theuseful charge transfer takes place in the induced channel of the transistor,which is the substrate region under the gate oxide The length L and thewidth W of the gate are estimated along and perpendicularly to the drain-source path, respectively The substrate connection is provided by a doped

p+ region Generally, the substrate is connected to the most negative supplyvoltage of the circuit so that the source-drain junction diodes are reverse-biased

In the case of the pMOS transistor (seeFigure 1.2(b)), the drain and sourceare formed by p+ diﬀusions in the n-type substrate A doped n+ region isrequired for the realization of the substrate connection Otherwise, the cross-sections for the two transistor types are similar Here, the substrate is to beconnected to the most positive supply voltage

The gate and substrate of an nMOS transistor can be assumed to formthe plates of a capacitor using silicon dioxide as the dielectric As a positivevoltage is applied to the gate, there is a movement of charges resulting in anaugmentation of holes at the gate side and electrons at the substrate edge.Initially, the mobile holes are pushed away from the substrate surface, leaving

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+ + +

G Polysilicon

Model and structure of (a) nMOS transistor and (b) pMOS transistor

behind a depletion region below the gate as shown in Figure 1.3, and theelectron enhancement is ﬁrst attributed to a weak inversion By increasingthe gate voltage, the concentration of electrons (minority carriers) can becomelarger than the one of holes (majority carriers) at the surface of the p-typesubstrate This is known as strong inversion, which occurs for voltages greaterthan two times the Fermi potential When the gate voltage is negative, theconcentration of holes will increase at the surface and an accumulation region

is formed

doped region

G

Polysilicon Oxide

depletion region inversion region

doped

Substrate

region

FIGURE 1.3

Localization of the inversion and depletion regions in a MOS transistor

For a pMOS transistor, the current is carried by holes instead of electrons.The source should be the node biased at the most positive voltage Similarresults can then be obtained for the pMOS device connected to a gate voltagewith inverse polarity Generally, the electrical characteristics of pMOS tran-sistors can be obtained from the ones of nMOS transistors by reversing thesign of all currents and voltages

The static characteristics of a MOS device can be determined by solving merically a set of diﬀerential equations governing the movement of electrical

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charges, given the relevant boundary conditions The behavior of the internalelectrostatic potential φ is given by the Poisson law,

∇2φ = −qǫ(Nd− Na+ p − n) (1.1)where q is the charge of the electron, ǫ is the dielectric constant of the semi-conductor, and Na and Nd are the concentrations of the acceptors (n-typedopant) and donors (p-type dopant), respectively The electron and hole con-centrations, n and p, can be derived, respectively, from the following conser-vation equations,

of electrons and holes The electron and hole current densities, Jnand Jp, are,respectively, given by

Based on Boltzmann’s distribution [2, 3], the concentration of electrons andholes can be respectively computed as

pdp ≃ Na, we can write ndp≃ n2i/NA, where ni is the intrinsic charge density.With the assumption that the current ﬂow is essentially one-dimensionalfrom the source to drain and the mobility is constant throughout the channel,

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the current density becomes

IDS = µn

WL

To proceed further, we assume that

VGS− VF B = VGB= Vox+ φs (1.13)where VF B is the ﬂat-band voltage, Vox is the voltage drop across the oxide,and φs is the potential at the silicon-oxide interface referenced to the bulk.Furthermore,

φs= φs(0) + V (y) = −2ψF+ V (y) (1.14)with ψF being the bulk Fermi potential, which is negative for a p-type sub-strate

Figure 1.4shows the variation of the total charge per unit area, Qs, as afunction of the surface potential The following relation can be written:

Qs= −CoxVox= −Cox[VGB+ 2ψF− V (y)] (1.15)where Cox = ǫox/tox is the gate oxide capacitance per unit area, ǫox is theoxide permittivity, and tox denotes the oxide thickness As a small positivevoltage is applied to the gate, holes are lessened from the vicinity of the oxide-silicon interface, and a space-charge region consisting of stationary acceptorions is established The depletion charge is then given by

Qd= −qNAWd = −p2qǫNA[V (y) − 2ψF] (1.16)where Wd =p2ǫ[V (y) − 2ψF]/qNAis the width of the depletion region In the

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10 10

Plot of the charge density versus the surface potential

small-signal analysis, the depletion capacitance is obtained as Cd= ∂Qd/∂V.The expression of the drain current reads

(1.18)

where

γ =

√2ǫqNA

(VGS− VT − VDS/2)VDS (1.20)

where

VT = VF B− 2ψF+ γp−2ψF (1.21)The current IDS reaches its maximum at VDS(sat)= VGS− VT, which can beobtained by solving the equation ∂IDS/∂VDS = 0 Based on this result, the

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drain-source current in the saturation region is deduced from Equation (1.20)

as follows:

IDS =1

2µnCox

WL

(VGS− VT)2 (1.22)Without the above simplifying assumption, the equation of the drain currentcan be derived as

to VDS and the channel behaves as a voltage-controlled resistor in the triode

or linear region By increasing the drain voltage, there is a reduction of thecharges at the drain boundary and the channel is pinched off That is, for

VDS ≥ VDS(sat)= VGS− VT, where VGS denotes the gate-source voltage, thechannel ceases to further conduct electricity and its conductivity is signiﬁ-cantly reduced The current is now due to the charge drift and IDS remainspractically constant In this case, the transistor is considered to operate in thesaturation region

A plot of the square root of the normalized drain current versus the source voltage is shown in Figure 1.6 for several values of the bulk-sourcevoltage, VBS Note that the threshold voltage changes with VBS, providedthat this latter is diﬀerent from zero

For a gate voltage, VG, greater than 0 and less than VT, the drain-sourcecurrent still exhibits a magnitude diﬀerent from zero, which decreases expo-nentially This corresponds to the subthreshold region Here, the current IDS

is due to the diﬀusion [4] instead of the drift process, as is the case in thestrong inversion region Thus,

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where A = W · △d is the cross-section area of the current ﬂow; △d is thechannel depth, which is deﬁned as the distance from the silicon-oxide interface

at which the potential is lowered by kT /q, i.e., △d = kT/qEs; and Es is thesurface ﬁeld given by

kT(φs+ 2ψF− VDB)i (1.29)where ndp≃ Na, as the concentration of acceptors is the most signiﬁcant Thedrain-source current can be written as

IDS = µnq W

L

kTq

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silicon-oxide interface, and Coxis the oxide capacitance per unit area Due tothe nonlinear dependence of the charge on φs, an expression of φs is easilyobtained from the next ﬁrst-order Taylor series of VGS around φso+ VSB [6],

VGS = VGS∗ + η(φs− φso− VSB) (1.32)where

V∗

GS= VGS|φ s =φ so +V SB (1.33)and

η = dVGS

dφs

φ s =φ so +V SB

(1.34)Thus,

φs= VGS− V∗

GS

η + φso+ VSB (1.35)and the subthreshold current becomes

In the weak inversion region, −ψF + VSB < φs < −2ψF + VSB, and greataccuracy can be ensured by choosing the reference point φso = −3ψF/2.However, with φso = −2ψF, the voltage V∗

GS is reduced to VT The current

IDS depends on the gate-source and drain-source voltages But, its dependence

on the voltage, VDS, is considerably reduced as VDS becomes greater than afew kT /q

The I-V characteristics of an nMOS transistor are shown in Figure 1.7.For VDS > 0.1V, the current IDS is almost independent of VDS, and we have

IDS ≃ µn

W

L

kTq

2

Cdexp

qkT

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I-V characteristics of an nMOS transistor.

A model for MOS transistor capacitances is required to accurately predictthe ac behavior of circuits The silicon oxide, which provides the isolation ofthe gate from the channel, can be considered as the dielectric of a capacitorwith the value Cox Due to the lateral diﬀusion, the eﬀective channel length,

Lef f, is shorter than the drawn length, L, as shown inFigure 1.8, and overlapcapacitors are formed between the gate and drain/source The expression ofthe overlap capacitance can be given by

Cgso= Cgdo= CoxW △L (1.39)where △L = (L−Lef f)/2 Note that the accurate determination of the overlapcapacitance per unit width, Cov, can require more precise calculations The ca-pacitors related to the silicon oxide, Cg = CoxW L, and the depletion region,

Cd, exist between the gate and channel and between the channel and strate In addition, junction capacitors are present between the source/drainand substrate They consist of two geometry-dependent components related,respectively, to the bottom-plate and side-wall of the junction

FIGURE 1.8

MOS transistor layout

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A transistor can then be represented as shown inFigure 1.9with parasiticcapacitors between every two of the four output nodes [7] It is assumed thatthe capacitance between the source and drain is negligible.

GS C

GB

GD C

DB C

FIGURE 1.9

MOS transistor capacitance model

Let QG, QB, QS, and QD be the gate, bulk, source, and drain charges,respectively The charge conservation principle results in the following relation:

QG+ QB+ QS+ QD= 0 (1.40)The charges QGand QBcan be computed from the Poisson equation The sum

of QDand QS is equal to the channel charge, and the drain and source chargepartition changes uniformly from the QD/QS ratio of 50/50 in the trioderegion to 40/60 in the saturation region [8] However, the charge partitionwill become closer to the ratio 0/100 when the transistor is switched at aspeed greater than the channel charging time Based on the charge model, thecapacitances can be deﬁned as

Trang 29

0 0

1 Cut−

C

(V) /WLC

FIGURE 1.11Plot of normalized capacitances(CGB and CBG) versus the gate-source voltage (Adapted from [7],

the order of 1 fF/µm, 0.5 fF/µm, and 1.5 fF/µm, respectively, remain almostunchanged across technology nodes [9]

Typical values of the threshold voltages and transconductance characteristicsare provided inTable 1.1for the 0.25-µm, 0.18-µm, and 0.13-µm CMOS pro-cesses Note that the transconductance is deﬁned as half of the product of thecharge carrier mobility and oxide capacitance

TABLE 1.1

CMOS Process Characteristics

0.25µm 0.18µm 0.13µm

VDD= 2.5V VDD= 1.8V VDD = 1.5VnMOS pMOS nMOS pMOS nMOS pMOS

VT (V) 0.65 −0.51 0.49 −0.43 0.44 −0.42

K′ (µA/V2) 114.9 25.5 154.0 33.2 283.1 49.2

While resulting in the improvement of the circuit performance (area, speed,power dissipation), the reduction of the transistor size is aﬀected by limita-tions associated with the thickness and electrical characteristics of the gatedielectric With the constant-voltage scaling, the magnitude of the electric

Trang 30

ﬁeld in the channel can increase considerably, placing some limitations in thetransistor miniaturization.

• Small-geometry eﬀects

When the effective channel length is on the order of the source/drain tion depletion width, the potential distribution in the channel becomes de-pendent on the lateral electric field component in addition to the normalone and features a two-dimensional representation As a result, the thresh-old voltage is now dependent on the drain bias, channel length, and channelwidth The threshold voltage is decreased as the channel length is reducedand also as the drain bias is raised By reducing excessively the channellength, the depletion region of the drain junction can punch through theone of the source junction and the drain-source current ceases to be con-trolled by the gate-source voltage The variation of the threshold voltagewith the drain bias is caused by the drain-induced barrier lowering effect atthe source junction

junc-• Hot carrier eﬀects

The lateral electric field increases quickly as the transistor is scaled down.During the displacement from the source to the drain, carriers can be ac-celerated when they can acquire the energy related to the high electric fieldexisting in the channel They may collide with fixed atoms to generate ad-ditional electron/hole pairs This process is repetitive and results in an ab-normal increase in the drain current The high-energy electrons may also

be trapped at the silicon-oxide interface, and in turn cause the degradation

of the device characteristics, such as the voltage threshold and ductance For the long-term operation, the transistor can exhibit reliabilityproblems, due to the variation of the I-V characteristics

transcon-• Gate-induced drain leakage current

The gate-induced drain leakage current is observed in a transistor biased

in the oﬀ-state Due to the tunneling eﬀect through the gate insulator, it

is dependent on the drain-gate voltage and becomes important as the dielectric thickness is decreased

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The accuracy of the level 1 model is adequate for transistors with channellength and width greater than 4 µm The drain-source current, IDS, in thecutoﬀ, triode, and saturation regions is given by the next equation [11],

K(VGS− VT)2(1 + λVDS) for VGS > VT and VDS≥ VGS− VT

(1.44)where

VT = VT 0+ γ(pψB+ VSB−pψB) (1.45)

VT 0= VF B+ ψB+ γpψB (1.46)and

The transconductance parameter K is deﬁned as

β = 2K = µnCox W

where Lef f is the eﬀective channel length, and the saturation voltage is given

by VDS(sat) = VGS− VT The parameter γ represents the body-effect cient, ψB is the surface potential in the strong inversion for zero back-gatebias, ψF represents the bulk Fermi potential, and λ is the channel-lengthmodulation coefficient By introducing the parameter λ, the slight increase inthe drain current in the saturation region is taken into account However, thedrain current in the triode region can be multiplied by the term 1 + λVDS toprovide a continuous transition to the saturation current during the simula-tion To model the drain-source resistance near the transistor bias point, thechannel-length modulation coefficient can be expressed as,

where VAis the Early voltage The drain-bulk and source-bulk currents, IDB

and ISB, can be written as

IDB = ID0

exp qVDBkT

− 1

(1.50)and

ISB = IS0

exp qVSBkT

− 1

(1.51)where ID0 and IS0 are the saturation currents of the drain and source junc-tions, respectively

A small-signal equivalent model of a MOS transistor [12] is shown inure 1.12 The gate-source and source-bulk (or simply bulk) transconductances,

Fig-www.TechnicalBooksPDF.com

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rs rdS

sb

gds

FIGURE 1.12

Small-signal equivalent model of a MOS transistor

gmand gmb, and the drain-source conductance, gds, can be related to the I-Vcharacteristic as follows:

gm= ∂IDS

∂VGS

V GS ,V DS

(1.53)and

gds= ∂IDS

∂VDS

V GS ,V BS

(1.54)The ﬁve capacitances, CGD, CGS, CGB, CDB, and CSB, are determined bythe corresponding charges The ohmic resistances, rd and rs, are not aﬀected

by the bias condition and are lower than the other transistor resistances Due

to the fact that the drain-bulk and source-bulk junctions are reverse-biased,the eﬀect of the conductances gdb = ∂IDB/∂VDB and gsb = ∂ISB/∂VSB onthe device behavior is limited It should be noted that additional substrate-coupling resistors and the gate resistor are to be included in the compact model

ofFigure 1.12for an accurate description of the radio-frequency response

Find the transconductances, gmand gmb, and the conductance,

gds, for a transistor operating in the saturation region

From the drain-source current in the saturation region,

IDS = ID= K(VGS− VT)2(1 + λVDS) (1.55)

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the threshold voltage,

VT = VT 0+ γ(pψB+ VSB−pψB) (1.56)and with the assumption that VBS = −VSB and ψB= 2φF, wecan obtain the next relations

gm= ∂ID

∂VGS

V GS ,V BS

= λ ID

1 + λVDS (1.58)and

gmb= ∂ID

∂VBS

... Cg = CoxW L, and the depletion region,

Cd, exist between the gate and channel and between the channel and strate In addition, junction capacitors... QGand QBcan be computed from the Poisson equation The sum

of QDand QS is equal to the channel charge, and the drain and source chargepartition...

Typical values of the threshold voltages and transconductance characteristicsare provided inTable 1.1for the 0.25-µm, 0.18-µm, and 0.13-µm CMOS pro-cesses Note that the transconductance

Tiêu đề	CMOS Analog Integrated Circuits Amplifiers, Comparators, Multipliers, Filters, and Oscillators
Tác giả	Tertulien Ndjountche
Trường học	CRC Press Taylor & Francis Group
Thể loại	book
Năm xuất bản	2019
Thành phố	Boca Raton

Định dạng
Số trang	670
Dung lượng	20,47 MB