Tài liệu RF và mạch lạc lò vi sóng P10 docx

Expressions for input and output stability circles are presented next tofacilitate the design of ampli®er circuits.. Thesource re¯ection coef®cient is GS while the load re¯ection coef®ci

TRANSISTOR AMPLIFIER DESIGN

Ampli®ers are among the basic building blocks of an electronic system Whilevacuum tube devices are still used in high-power microwave circuits, transistorsÐsilicon bipolar junction devices, GaAs MESFET, heterojunction bipolar transistors(HBT), and high-electron mobility transistors (HEMT)Ðare common in many RFand microwave designs This chapter begins with the stability considerations for atwo-port network and the formulation of relevant conditions in terms of its scatteringparameters Expressions for input and output stability circles are presented next tofacilitate the design of ampli®er circuits Design procedures for various small-signalsingle-stage ampli®ers are discussed for unilateral as well as bilateral transistors.Noise ®gure considerations in ampli®er design are discussed in the followingsection An overview of broadband ampli®ers is included Small-signal equivalentcircuits and biasing mechanisms for various transistors are also summarized insubsequent sections

10.1 STABILITY CONSIDERATIONS

Consider a two-port network that is terminated by load ZLas shown in Figure 10.1

A voltage source VS with internal impedance ZS is connected at its input port.Re¯ection coef®cients at its input and output ports are Ginand Gout, respectively Thesource re¯ection coef®cient is GS while the load re¯ection coef®cient is GL.Expressions for input and output re¯ection coef®cients were formulated in thepreceding chapter (Examples 9.6 and 9.7)

385

Radio-Frequency and Microwave Communication Circuits: Analysis and Design

Devendra K Misra Copyright # 2001 John Wiley & Sons, Inc ISBNs: 0-471-41253-8 (Hardback); 0-471-22435-9 (Electronic)

For this two-port to be unconditionally stable at a given frequency, the followinginequalities must hold:

This traces a circle on the complex plane as y varies from zero to 2p It is illustrated

in Figure 10.2 Further, 1=1 jS22j exp… jy† represents a circle of radius r with itscenter located at d, where

r ˆ12

1 jS22j2< 1or,

Since the left-hand side of (10.1.12) is always a positive number, this inequality will

be satis®ed if the following is true

1 jS22j2 jS12S21j > 0 …10:1:13†

Similarly, stability condition (10.1.4) will be satis®ed if

1 jS11j2 jS12S21j > 0 …10:1:14†Adding (10.1.13) and (10.1.14), we get

2 jS11j2 jS22j2 2jS12S21j > 0or,

2…jS11j2‡ jS22j2† > jS12S21j …10:1:15†From (10.1.6) and (10.1.15), we have

jDj < jS11S22j ‡ jS12S21j < jS11S22j ‡ 1 1

2…jS11j2‡ jS22j2†or,

jDj < 1 1

2…jS11j jS22j†2) jDj < 1 …10:1:16†Multiplying (10.1.13) and (10.1.14), we get

…1 jS22j2 jS12S21j†…1 jS11j2 jS12S21j† > 0or,

1 jS11j2 jS22j2 2jS12S21j ‡ z > 0 …10:1:17†

Figure 10.2 A graphical representation of (10.1.7)

1 jS11j2 jS22j2 2jS12S21j ‡ jDj2> 0or,

1 jS11j2 jS22j2‡ jDj2 > 2jS12S21jor,

1 jS11j2 jS22j2‡ jDj22jS12S21j > 1Therefore,

k ˆ1 jS11j2 jS22j2‡ jDj2

If S-parameters of a transistor satisfy conditions (10.1.16) and (10.1.18) then it isstable for any passive load and generator impedance In other words, this transistor isunconditionally stable On the other hand, it may be conditionally stable (stable forlimited values of load or source impedance) if one or both of these conditions areviolated It means that the transistor can provide stable operation for a restrictedrange of GS and GL A simple procedure to ®nd these stable regions is to testinequalities (10.1.3) and (10.1.4) for particular load and source impedances Analternative graphical approach is to ®nd the circles of instability for load andgenerator re¯ection coef®cients on a Smith chart This latter approach is presentedbelow

From the expression of input re¯ection coef®cient (9.4.7), we ®nd that

Ginˆ S11‡1 SS21S12GL

22GL) Gin…1 S22GL† ˆ S11…1 S22GL† ‡ S21S12GLor,

Ginˆ S11 GL…S11S22 S12S21 GinS22† ) GLˆ S11 Gin

D GinS22or,

As before, 1 GinS22D 1 represents a circle on the complex plane It is centered

at 1 with radius jGinS22D 1j; the reciprocal of this expression is another circle withcenter at

CLˆS1

22

D*…D ‡ S12S21† jS22j2jDj2 jS22j2

ˆS122

D*S11S22 jS22j2jDj2 jS22j2

Therefore,

CLˆD*S11 S*22jDj2 jS22j2ˆ…S22 DS**11†*

ˆ jDjS212SjS2122j2

As explained following (10.1.19), this circle represents the locus of points overwhich the input re¯ection coef®cient Ginis equal to unity On one side of this circle,the input re¯ection coef®cient is less than unity (stable region) while on its other side

it exceeds 1 (unstable region) When load re¯ection coef®cient GL is zero (i.e., amatched termination is used), Gin is equal to S11 Hence, the center of the Smithchart (re¯ection coef®cient equal to zero) represents a stable point if jS11j is less thanunity On the other hand, it represents unstable impedance for jS11j greater thanunity If GLˆ 0 is located outside the stability circle and is found stable then alloutside points are stable Similarly, if GLˆ 0 is inside the stability circle and isfound stable then all enclosed points are stable If GLˆ 0 is unstable then all points

on that side of the stability circle are unstable

Similarly, the locus of GScan be derived from (10.1.4), with its center CSand itsradius rSgiven as follows:

CSˆD*S22 S**11jDj2 jS11j2 ˆ…S11 DS**22†*

and,

rSˆ 1jDS11j

S12S21jD 1S11j

1 jD 1S11j2

2

X ˆ…1 SS12S21GSGL

22GL†…1 S11GS†Therefore, the bounds of this gain ratio are given by

Example 10.4: The scattering parameters of two transistors are given below.Compare the unilateral ®gures of merit of the two

U ˆ0:01  2:05  0:45  0:4…1 0:452†…1 0:42† ˆ 0:00551 ˆ UAfor transistor A

Similarly, for transistor B,

U ˆ0:057  2:058  0:641  0:572…1 0:6412†…1 0:5722† ˆ 0:1085 ˆ UB

Hence, the error bounds for these two transistors can be determined from (10.2.9)

as follows For transistor A,

0:9891 <GGT

TU< 1:0055and for transistor B,

0:8138 < GT

GTU< 1:2582Alternatively, these two results can be expressed in dB as follows:

0:0476 dB <GGT

TU< 0:0238 dBand,

0:8948 dB < GT

GTU< 0:9976 dBCONCLUSION: If S12ˆ 0 can be assumed for a transistor without introducingsigni®cant error, the design procedure will be much simpler in comparison with that

of a bilateral case

10.3 CONSTANT GAIN CIRCLES

In the preceding section, we considered the design of ampli®ers for maximumpossible gains Now, let us consider the design procedure for other ampli®er circuits

We split it again into two cases, namely, the unilateral and the bilateral transistors

Unilateral Case

We consider two different cases of the unilateral transistors In one case, it isassumed that the transistor is unconditionally stable because jS11j and jS22j are lessthan unity In the other case, one or both of these parameters may be greater thanunity Thus, it makes jDj greater than 1

From (9.4.10)

GTUˆ 1 jGSj2

j1 S11GSj2 ? jS21j2? 1 jGLj2

j1 S22GLj2ˆ GS? Go? GLExpressions of GSand GL in this equation are similar in appearance Therefore,

we can express them by the following general form:

Giˆ 1 jGij2j1 SiiGij2; i ˆ L; ii ˆ 22i ˆ S; ii ˆ 11



…10:3:1†

Now, let us consider two different cases of unilateral transistors In one case thetransistor is unconditionally stable and in the other case it is potentially unstable.(i) If the unilateral transistor is unconditionally stable then jSiij < 1 Therefore,maximum Giin (10.3.1) will be given as

We de®ne the normalized gain factor gi as follows:

giˆGGi

Hence,

0  gi 1From (10.3.1) and (10.3.2), we can write

giˆ 1 jGij2

j1 SiiGij2…1 jSiij2† ) gij1 SiiGij2ˆ …1 jGij2†…1 jSiij2†or,

gi…1 SiiGi†…1 S*iiG*† ˆ 1 jSi iij2 jGij2‡ jGij2jSiij2

Since S12 is zero, this transistor is unilateral Hence,

k ˆ 1; and jDj < 1; …because jS11j < 1 and jS22j < 1†

Therefore, it is unconditionally stable From (9.4.14)±(9.4.16) we have

Goˆ jS21j2ˆ 2:52ˆ 6:25 ˆ 7:96 dB

;GTUmaxˆ 3:59 ‡ 1:92 ‡ 7:96 ˆ 13:47 dBThus, maximum possible gain is 2.47 dB higher than the desired value of 11 dB.Obviously, this transistor can be used for the present design

The constant gain circles can be determined from (10.3.5) and (10.3.6) Theseresults are tabulated here

GSˆ 3 dB  2 gSˆ 0:875 dSˆ 0:706€ 120 RSˆ 0:166

GSˆ 2 dB ˆ 1:58 gSˆ 0:691 dSˆ 0:627€ 120 RSˆ 0:294

GLˆ 1 dB ˆ 1:26 gLˆ 0:8064 dLˆ 0:52€ 70 RLˆ 0:303

GLˆ 0 dB ˆ 1 gLˆ 0:64 dLˆ 0:44€ 70 RLˆ 0:44

As illustrated in Figure 10.10, the gain circles are drawn from this data Since Go

is found as 8 dB (approximately), the remaining 3 dB need to be obtained through

GSand GL If we select GSas 3 dB then GLmust be 0 dB Alternatively, we can use

GS and GL as 2 dB and 1 dB, respectively, to obtain a transducer power gain of7:96 ‡ 2 ‡ 1  11 dB

Let us select point A on a 2-dB GScircle and design the input side network Thecorresponding admittance is found at point B, and therefore, a normalized capacitivesusceptance of j0:62 is needed in parallel with the source admittance to reach theinput VSWR circle An open-ended, 0.09-l-long shunt-stub can be used for this Thenormalized admittance is now 1 ‡ j0:62 This admittance can be transformed to that

of point B by a 0.183-l-long section of transmission line Similarly, point C can beused to obtain GLˆ 1 dB A normalized reactance of j0:48 in series with a 50-Oload can be used to synthesize this impedance Alternatively, the correspondingadmittance point D is identi®ed Hence, a shunt susceptance of j0:35 (an open-circuit stub of 0:431 l) and then a transmission line length of 0:044 l can provide thedesired admittance This circuit is illustrated in Figure 10.11

The return-loss is found by expressing jGinj in dB Since

Ginˆ S11‡ S12S21GL

1 S22GLand S12 ˆ 0, Ginˆ S11, therefore, jGin…3 GHz†j ˆ 0:8, jGin…4 GHz†j ˆ 0:75, and

jGin…5 GHz†j ˆ 0:71

Return loss at 3 GHz ˆ 20 log10…0:8† ˆ 1:94 dB

Return loss at 4 GHz ˆ 20 log10…0:75† ˆ 2:5 dB

Figure 10.11 RF circuit designed for Example 10.4

Figure 10.10 Constant gain circles and the network design for Example 10.4

Return loss at 5 GHz ˆ 20 log10…0:71† ˆ 2:97 dB.

Transducer power gain at 4 GHz is 11 dB (because we designed the circuit for thisgain) However, it will be different at other frequencies We can evaluate it from(9.4.16) as follows

GTUˆ 1 jGSj2j1 S11GSj2 ? jS21j2? 1 jGLj2

j1 S22GLj2Note that GS, GL, and S-parameters of the transistor are frequency dependent.Therefore, we need to determine re¯ection coef®cients at other frequencies beforeusing the above formula For a circuit designed with reactive discrete components,the new reactances can be easily evaluated The corresponding re¯ection coef®cientscan, in turn, be determined using the appropriate formula However, we usedtransmission lines in our design Electrical lengths of these lines will be different

at other frequencies We can calculate new electrical lengths by replacing l asfollows:

l !ffnewdesignlnew

At 3 GHz, original lengths must be multiplied by 3=4 ˆ 0:75 to adjust for thechange in frequency Similarly, it must be multiplied by 5=4 ˆ 1:25 for 5 GHz Thenew re¯ection coef®cients can be determined using the Smith chart The results aresummarized below

GTU…3 GHz† ˆ 5:4117 ˆ 10 log…5:4117† ˆ 7:33 dBSimilarly,

j1 …0:71€ 140†…0:41€ 81†j2 ? 2:32

j1 …0:58€ 85†…0:15€ 141†j2or,

GTU…5 GHz† ˆ0:7849 ? 1:12844:4008 ˆ 4:9688 ˆ 6:96 dBThese return-loss and gain characteristics are displayed in Figure 10.12

Figure 10.12 Gain and return loss versus frequency

(ii) If a unilateral transistor is potentially unstable then jSiij > 1.

For jSiij > 1, the real part of the corresponding impedance will be negative.Further, Gi in (10.3.1) will be in®nite for Giˆ 1=Sii In other words, total loop-resistance on the input side (for i ˆ S) or on the output side (for i ˆ L) is zero This

is the characteristic of an oscillator Hence, this circuit can oscillate We can still usethe same Smith chart to determine the corresponding impedance provided that themagnitude of re¯ection coef®cient is assumed as 1=jSiij, instead of jSiij while itsphase angle is the same as that of Sii, and the resistance scale is interpreted asnegative The reactance scale of the Smith chart is not affected

It can be shown that the location and radii of constant gain circles are still given

by (10.3.5) and (10.3.6) The centers of these circles are located along a radial linepassing through 1=Siion the Smith chart In order to prevent oscillations, Gimust beselected such that the loop resistance is a positive number

Example 10.5: A GaAs FET is biased at Vdsˆ 5 V and Idsˆ 10 mA A 50-O ANA

is used to determine its S-parameters at 1 GHz These are found as follows:

S11ˆ 2:27€ 120; S21ˆ 4€ 50; S12 ˆ 0; and S22ˆ 0:6€ 80(a) Use a Smith chart to determine its input impedance and indicate on it thesource impedance region(s) where the circuit is unstable

(b) Plot the constant gain circles for GSˆ 3 dB and GSˆ 5 dB on the sameSmith chart

(c) Find a source impedance that provides GSˆ 3 dB with maximum possibledegree of stability Also, determine the load impedance that gives maximum

GL Design the input and output networks

(d) Find the gain (in dB) of your ampli®er circuit

(a) First we locate 1=2:27 ˆ 0:4405 at € 120on the Smith chart It is depicted

as point P in Figure 10.13 This point gives the corresponding impedance if theresistance scale is interpreted as negative Thus, the normalized input impedance isabout 0:49 j0:46 Hence,

Zinˆ 50… 0:49 j0:46† ˆ 24:5 j23Therefore, if we use a source that has impedance with its real part less than 24.5 O,the loop resistance on the input side will stay negative That means one has to select

a source impedance that lies inside the resistive circle of 0.49 Outside this circle isunstable

1 …1 gS†jS11j2

where gSˆ GS…1 jS11j2†; the locations and radii of constant GScircles are found

1 …1 ‡ 13:1327†2:272 ˆ 0:2174 RSˆ…1 2:272†



1 ‡ 8:3058p

1 …1 ‡ 8:3058†2:272 ˆ 0:2698

dSˆ 1 …1 ‡ 13:1327†2:2713:1327 ? …2:27€ 1202†ˆ 0:45€ 120 dSˆ 1 …1 ‡ 8:3058†2:278:3058 ? …2:27€ 1202†ˆ 0:4015€ 120

These constant GS circles are shown on the Smith chart in Figure 10.13

(c) In order to obtain GSˆ 3 dB with maximum degree of stability, we selectpoint A for the source impedance because it has a maximum possible real part

; ZS 1 ‡ j0:5 or GSˆ 0:24€ 76With ZSˆ 50 ‡ j25 O, loop resistance in the input side is 50 24:5 ˆ 25:5 O It is apositive value, and therefore, the input circuit will be stable

For maximum GL, we select GLˆ S*22ˆ 0:6€ 80 It is depicted as point C inFigure 10.13 The corresponding impedance ZL is found to be

ZL ˆ 50…0:55 ‡ j1:03† ˆ 27:5 ‡ j51:5

Figure 10.13 Ampli®er design for Example 10.5

Now, the input and output circuits can be designed for these values One such circuit

is shown in Figure 10.14

(d) As designed, GSˆ 3 dB From (9.4.16),

1 jS22j2ˆ1 0:61 2ˆ 1:5625 ˆ 1:9382 dBand,

Go ˆ jS21j2 ˆ 42ˆ 16 ˆ 12:0412 dBTherefore,

GTUˆ 3 ‡ 1:9382 ‡ 12:0412 ˆ 16:9794 dB

Bilateral Case

If a microwave transistor cannot be assumed to be unilateral, the design procedurebecomes tedious for a less than maximum possible transducer power gain In thiscase, the operating or available power gain approach is preferred because of itssimplicity The design equations for these circuits are developed in this section

Unconditionally Stable Case: The operating power gain of an ampli®er is given by(9.4.19) For convenience, it is reproduced here:

GPˆ …1 jGLj2†jS21j2…j1 S22GLj2†…1 jGinj2† …9:4:19†

Figure 10.14 RF circuit for the ampli®er of Example 10.5

and the input re¯ection coef®cient is

Ginˆ S11‡1 SS12S21GL

22GL ˆ

S11 GLD

1 S22GLTherefore,

GPˆ …1 jGLj2†jS21j2…j1 S22GLj2† …jS11 GLDj2†ˆ jS21j2gp …10:3:7†where,

…j1 S22GLj2† …jS11 GLDj2† …10:3:8†The equation for gp can be simpli®ed and rearranged as follows:

2

ˆ…1 2kjS12S21jgp‡ jS12S21j2g2†

…1 ‡ gp…jS22j2 jDj2††2This represents a circle with its center cp and radius Rp given as follows:

For Rpˆ 0, (10.3.12) can be solved for gp, which represents its maximum value.

9 dB

Since k ˆ 1:5037 and jDj ˆ 0:3014, this transistor is unconditionally stable.Further, Gpmaxis found to be 11.38 dB Hence, it can be used to get a gain of 9 dB.The corresponding circle data is found from (10.3.11) and (10.3.12) as follows:

cpˆ 0:5083€ 103:94 and Rpˆ 0:4309This circle is drawn on the Smith chart (Figure 10.15) and the load re¯ectioncoef®cient is selected as 0:36€ 50 The corresponding input re¯ection coef®cient iscalculated as 0:63€ 175:6 Hence, GS must be equal to 0:63€ 175:6 (i.e.,conjugate of input re¯ection coef®cient) These load- and source-impedancepoints are depicted in Figure 10.15 as C and A, respectively The correspondingadmittance points are identi®ed as D and B on this chart The load side network isdesigned by moving from point O to point F and then to point D It is achieved byadding an open-circuited shunt stub of length 0:394 l and then a transmission line of0:083 l For the source side, we can follow the path O±E±B, and therefore, an open-circuited shunt stub of 0:161 l followed by a 0.076 l-long transmission line canprovide the desired admittance The designed circuit is shown in Figure 10.16.Potentially Unstable Case: Operating power gain circles for a bilateral potentiallyunstable transistor still can be found from (10.3.9) and (10.3.10) However, the loadimpedance point is selected such that it is in the stable region Further, the conjugate

of its input re¯ection coef®cient must be a stable point because it represents thesource re¯ection coef®cient Similarly, the available power gain circles can be drawn

Figure 10.15 Matching network design for Example 10.6

(i) Stability check:

k ˆ1 jS11j2... susceptance at point C is estimated as j1:7 Hence, the shuntcapacitor on the source side must provide a susceptance of 1:7=50 ˆ 0:034 S

Figure 10.4 Smith chart illustrating the design of...

Ginˆ GS*and

Gout ˆ GL*

Figure 10.5 RF circuit designed for Example 10.2

Figure 10.6 A bilateral transistor with input and output