COMPAL LA a551p (ZRMAE,ZEMAE) 2013 06 07 rev 0 2 schematic

NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.THIS SHEET OF ENGINEERING DRAWIN

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THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC

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Jaguar Core Integrated Yangtze FCH

BGA 769-balls

BANK 0, 1, 2, 3

200pin DDRIII-SO-DIMM X2

1.5V DDRIII 1333/1600 MT/s APU SMBUS

Memory BUS(DDRIII)

page 10,11

Single Channel

PCIeMini Card For BT USB port 1

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DESIGN CURRENT 0A DESIGN CURRENT 0.15A

+5VL +3VL

DESIGN CURRENT 4A

Ipeak=8A, Imax=5.6A, Iocp min=10A Ipeak=12A, Imax=8.4A, Iocp min=14A

+1.5VGSVGA_PWRGD

N-CHANNEL Ipeak=12A, Imax=8.4A, Iocp min=13.8A

DESIGN CURRENT 2A

RT8207MSYSON

SUSP#

DESIGN CURRENT 1.5A +0.75VS

RT8243A B+

DGPU_PWR_EN

DESIGN CURRENT 60mA +3VS_DGPU

VGA_COREGPU_DPRSLPVR

ISL62881

APU_CORE_NB

Ipeak=13A, Imax=9.1A, Iocp min=30A

+1.8VALW1.8_0.95VALW_PWREN

FDS6676

+5VS_ODDODD_PWR

TPS22966

+1.8VSSUSP#

N-CHANNEL TPS22966

+1.8VGSVGA_PWRGD

N-CHANNEL TPS22966

Title

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O O

X

O

X

O O

X

Voltage Rails ( O MEANS ON X MEANS OFF )

O O

X

power plane

O O O O O

+0.75VS +RTCVCC

O O O

O O

Power

+0.95VS +0.95VALW

G-A G-B

G-C G-D

G-E

APU POWER SEQUENCE

+3VALW_APU

+1.8VALW +0.95VALW +RTC

+3VS +1.8VS +1.5V

+0.95VS

+APU_CORE +APU_CORE_NB

HIGH HIGH

HIGH

9012 9012 EC

BTO Option Table

CAM@EMI@ @CAM@EMI@

2544@

Codec ALC259 ALC259 259@

Sun-Pro M2 VGA GPU

VGA@

BTO explain

Function description

EMI/ESD/RF part

EMI@ @EMI@ ESD@ @ESD@ @RF@

EMI/ESD/RF part EMI/ESD/RF part

885 w/

885@

w/ EMI 885_EMI@

Touch Screen Touch Screen W/ Touch LAN

KB Light

KB Light KBL@

Function

BTO explain description

8106E

8106E@

Function

BTO explain description

APU CPU A4-5000

Function

BTO explain

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M_ZVDDIO

DDR_AB_D0

DDR_AB_D2DDR_AB_D4

DDR_AB_D6

DDR_AB_D8

DDR_AB_D10DDR_AB_D12

DDR_AB_D15

DDR_AB_D16

DDR_AB_D22

DDR_AB_D24

DDR_AB_D26

DDR_AB_D32

DDR_AB_D34

DDR_AB_D40

DDR_AB_D42

DDR_AB_MA14

DDR_AB_MA1

DDR_AB_MA11DDR_AB_MA6DDR_AB_MA3

DDR_AB_MA5

DDR_AB_MA8DDR_AB_MA0

DDR_AB_DM6DDR_AB_DM3

DDR_AB_DQS0

DDR_AB_DQS3DDR_AB_DQS#3

DDR_AB_DQS4DDR_AB_DQS#4DDR_AB_DQS5DDR_AB_DQS#5DDR_AB_DQS6DDR_AB_DQS#6

DDR_AB_DQS#7DDR_AB_DQS7

MEM_MAB_RST#

DDR_A_CLK1#

DDR_A_CLK1DDR_AB_BS1

PCIE_WLANTX_ARX_P2PCIE_WLANTX_ARX_N2

PCIE_ATX_C_WLANRX_P2

FAN_SPEED1DFAN1

Title

CC11 VGA@ 0.1U_0402_16V7KCC111 2VGA@ 0.1U_0402_16V7K

CC171U_0402_6.3V6KCC171U_0402_6.3V6K

1

2

CC2 0.1U_0402_16V7KCC21 2 0.1U_0402_16V7K

CC6 VGA@ 0.1U_0402_16V7KCC6 1 2VGA@ 0.1U_0402_16V7K

C2710U_0805_6.3V6MC2710U_0805_6.3V6M

CC3 0.1U_0402_16V7KCC31 2 0.1U_0402_16V7K

C310U_0805_6.3V6MC310U_0805_6.3V6M

FT3 REV 0.51

MEMORYUC1A

FT3_BGA769 @

FT3 REV 0.51

MEMORYUC1A

FT3_BGA769 @AC38 M_VREFDQ

@1

2

CC18

0.1U_0402_16V7KCC18

0.1U_0402_16V7K

12

RC439.2_0402_1% RC439.2_0402_1%

FT3 REV 0.51

PCIEUC1B

FT3_BGA769 @

FT3 REV 0.51

PCIEUC1B

U4

P2793BB0_SO8U4

P2793BB0_SO8

EN1VIN2VOUT3VSET4

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EDP/LVDS EDP Cap co-lay

route TEST25_H/L AND TEST28_H/L differentially

EDP Cap co-lay

DP_STEREOSYNC Used to align shutter glasses with the interleaved video frame

EDP use 2 Lane for FHD

EDP_LCD_TXOUT2+

EDP_LCD_TXOUT1+

EDP_LCD_TXOUT2-

EDP_LCD_TXOUT1-LCD_TXCLK+

LCD_TXCLK-DP_2K_ZVSSDP_150_ZVSS

LCD_ENBKLLCD_ENVDDLCD_INT_PWM

EDP_LVDS_DATA_REDP_LVDS_CLK_R

DAC_ZVSS

EDP_LVDS_CLK_REDP_LVDS_DATA_R

TEST4

TEST31TEST28_LTEST28_H

TEST42TEST39

TEST41

TEST18TEST25_HTEST25_L

DP_STEREOSYNCVDDMEM_SENSE

VDD095_FB_HVDD095_FB_L

APU_DBRDYAPU_DBREQ#

APU_RST#

APU_PWRGD

DP_STEREOSYNCAPU_PROCHOT#

APU_HDMI_TX2-APU_HDMI_TX0+

APU_HDMI_TX1-APU_HDMI_CLK+

APU_HDMI_TX0-

APU_HDMI_CLK-APU_HDMI_CLKAPU_HDMI_DATA

EDP_LCD_TXOUT2+_REDP_LCD_TXOUT2-_R

EDP_LCD_TXOUT1-_REDP_LCD_TXOUT1+_R

EDP_LCD_TXOUT0+_REDP_LCD_TXOUT0-_R

LCD_TXCLK+

LCD_TXCLK-LCD_ENBKLLCD_ENVDDLCD_INT_PWM

APU_SVTAPU_SVC

EC_SMB_CK2EC_SMB_DA2

APU_VDDNB_SEN_HAPU_VDD_SEN_HAPU_VDD_SEN_L

APU_PROCHOT#

APU_PWRGD

EDP_LVDS_CLKEDP_LVDS_DATAEDP_LVDS_HPDHDMI_HPD

+3VS

+1.8VS+1.8VS

+1.8VS

+1.8VS+3VS

Title

CC103 LVDS@ 0_0402_5%

CC1031LVDS@20_0402_5%

RC41 @ 1K_0402_5%RC411 @ 2 1K_0402_5%

CC108 LVDS@ 0_0402_5%

CC108 1LVDS@20_0402_5%

CC1100.1U_0402_16V7K

EDP@

CC1100.1U_0402_16V7K

T6TP@

RC20 100K_0402_5%RC202 1100K_0402_5%

EDP@

CC1090.1U_0402_16V7K

EDP@

RC46 @ 1K_0402_5%RC461 @ 2 1K_0402_5%RC36 @ 1K_0402_5%RC361 @ 2 1K_0402_5%

FT3_BGA769 @

FT3 REV 0.51

DISPLAY/SVI2/JTAG/TESTUC1C

RC28 1K_0402_5%

12

RC45 @ 100K_0402_5%RC452 @ 1100K_0402_5%

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USB3.0-Right1 USB3.0-Right2

WLAN (BT)

Touch Screen

Cardreader Int Camera

LAN WLAN

USB_ZVSS

USBSS_ZVDDUSBSS_ZVSS

SATA_ZVSSSATA_ZVSS_095

48M_X1

48M_X2

LPC_CLK0

APU_SPI_CLKAPU_SPI_CS1#

APU_SPI_MOSI

APU_SPI_CLK_RAPU_SPI_CS1#

APU_SPI_MISOAPU_SPI_MOSI

APU_SPI_CS2#

48M_X148M_X2

SATA_ATX_DRX_P0

LPC_AD0LPC_AD2

SERIRQ

CLK_PCI_ECCLK_PCI_DDR

LPC_FRAME#

SATA_DTX_C_ARX_N0

USB30_TX0P

USB30_TX1PUSB30_RX0P

CLK_WLANCLK_WLAN#

EC_SPIDIEC_SPIDOEC_SPICLK

+0.95VALW+0.95VS

+3VALW_APU

Title

FT3 REV 0.51

CLK/SATA/USB/SPI/LPCUC1E

MX25L3205DM2I-12G SO8

CS1

VCC8

HOLD7

SI5SCLK6

W P3

12

@EMI@

CC1310P_0402_50V8J

@EMI@

12

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BOOT FAIL TIMER

DISABLED

CLKGEN ENABLE

CLKGEN DISABLED

SPI ROM 1.8V SPI ROM

3.3V SPI ROM

NORMAL POWR UP/RESET TIMING

FAST POWER UP/RESET TIMING FOR SIMULATION LPC ROM

DEFAULT DEFAULT

DEFAULT

Follow check list & ORB_0C

design 10 ms RC delay circuit

on +1.8-V S5 power rail.

PCIE_RST# is for PCIE devices on APU

A_RST# is for LPC devices

APU SMBus0 for S0 , SMBus1 for S5

SLP_S3#, SLP_S5# PU reserve

Board_ID0 Board_ID1 Board Conf.

PX5 Reserved DIS

0 1

0 0

PANEL_SEL

eDP panel

LVDS panel

HDA_RST#

AZ_SDIN0_HDHDA_BITCLK

RSMRST#

TEST0TEST1/TMSTEST2

APU_PCIE_RST#_R

LPC_RST#_R

EC_LID_OUT#

APU_SCLK1APU_SDATA1

32K_X1

32K_X2

APU_GPIO174RSMRST#

APU_SDATA1

TOUCH_SEL

PXS_PWRENPANEL_SEL

PANEL_SEL

SYS_PWRGD

USB_OC#0USB_CHG_OC#

PXS_PWREN

Board_ID1PXS_EN#

TEST0

TEST1/TMS

TEST2

APU_SCLK0APU_SDATA0

AZ_SYNC_HD

AZ_SDIN0_HDAZ_SDOUT_HD

KB_RST#

USB_OC#0USB_CHG_OC#

+3VS+3VS

+1.8VALW

+3VS+3VALW_APU

@

RC161K_0402_5%

RC1142K_0402_5%

RC10420M_0402_5%

RC171K_0402_5%

@

RC171K_0402_5%

32.768KHZ_7PF_Q13MC1461000100

14

23

RC11010K_0402_5%

RC315K_0402_5%

RC991K_0402_5%

NTOUCH@

RC991K_0402_5%

NTOUCH@

RC1152K_0402_5%

@

RC1152K_0402_5%

@

RC74100K_0402_5%

@

RC74100K_0402_5%

FT3 REV 0.51

ACPI/SD/AZ/GPIO/RTC/MISCUC1D

150P_0402_50V8J

1

2

RC515K_0402_5%

@

RC515K_0402_5%

@

RC127 10K_0402_5%

RC1271 210K_0402_5%

RC9510K_0402_5%

TOUCH@

RC9510K_0402_5%

QC22N7002KW_SOT323-3

@

RC10710K_0402_5%

VGA@

QC3A2N7002KDWH_SOT363-6

VGA@

CC31 10P_0402_50V8JCC311 210P_0402_50V8J

RC10810K_0402_5%

RC1115K_0402_5%

@

RC1115K_0402_5%

@

DC2

CH751H-40PT_SOD323-2DC2

CH751H-40PT_SOD323-2

21

QC3B2N7002KDWH_SOT363-6

VGA@

QC3B2N7002KDWH_SOT363-6

VGA@

34

EDP@

RC12510K_0402_5%

RC1122K_0402_5%

LVDS@

RC12610K_0402_5%

LVDS@

RC1132K_0402_5%

@

RC1132K_0402_5%

@

RC10610K_0402_5%

CC30 10P_0402_50V8JCC301 210P_0402_50V8J

RC68 33_0402_5%

RC681 233_0402_5%

RC121K_0402_5%

@

RC121K_0402_5%

@

RC1112K_0402_5%

@

RC1112K_0402_5%

@

RC10910K_0402_5%

@

CC28150P_0402_50V8JCC28150P_0402_50V8J

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1.8VALW & 1.8VS OF APU

0.95VALW & 0.95VS OF APU 3.3VALW & 3.3VS OF APU

RTC OF APU

15A/21A

13A/17A 3A

0.1A 0.5A

0.2A 1A

0.5A

4.5uA

1.5A

0.2A 5A

4.7uF 1uF 180pF AMD CKL v1.01

1 3 1 2

2 1

VDD_18 VDD_18_ALW

10uF 1uF 180pF

1 7 1

1 6 1 AMD CKL v1.01 4.7uF

VDDIO_MEM_S

10uF 0.1uF 180pF

2 8 4 AMD CKL v1.01

VDD_095_USB3_DUAL

10uF 1uF 180pF

2 3 1 VDD_095

VDD_095_ALW 2 5 1 4

1 1 AMD CKL v1.01

for VDDIO_AZ_ALW 0.1A

Place on TOP

4.5uA

route to 20mil

+APU_CORE_NB+APU_CORE

+1.8VS

+3VS_APU

+0.95VS_APU

+0.95VS_APU_GFX+RTC_APU

+0.95VALW_APU+0.95VALW_APU_USB3+3VALW_APU+1.8VALW_APU+1.5VS

+1.5V

+1.8VALW

+3VS

+1.8VS+1.5V

+0.95VALW_APU_USB3

+0.95VALW_APU

+RTC_APU+1.5VS

Title

RC123120_0402_5%

@

PJ2JUMP_43X79

FT3_BGA769 @

FT3 REV 0.51

GNDUC1G

FT3_BGA769 @H31 VSS_62

RC12210K_0402_5%

FT3_BGA769 @

FT3 REV 0.51

POWERUC1F

FT3_BGA769 @AN4 VDDBT_RTC_G

FT3_BGA769 @

FT3 REV 0.51

GNDUC1H

FT3_BGA769 @AL29 VSS_186

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DDR_A_SCS0#

DDR_AB_DQS#1

DDR_AB_D10

DDR_AB_D44

DDR_AB_DQS#3DDR_AB_D12

DDR_AB_DM7

DDR_A_ODT1DDR_A_CLK0

DDR_AB_D58

DDR_AB_DQS#2

DDR_AB_MA6

DDR_AB_D48DDR_AB_DM5

DDR_AB_D6

DDR_AB_D42

DDR_AB_D54

DDR_AB_D2DDR_AB_DM0

DDR_AB_D24

DDR_AB_D0

+VREF_CAA+VREF_DQA

MEM_MAB_EVENT#

+VREF_CAA

DDR_A_CKE1DDR_A_CKE0

DDR_AB_RAS#

DDR_A_ODT1DDR_AB_BS0

+0.75VS

+1.5V

+0.75VS+1.5V

Title

RD31K_0402_1%

RD21K_0402_1%RD21K_0402_1%

CD9 1U_0402_6.3V6KCD9 2 11U_0402_6.3V6K

RD11K_0402_1%

CD11 10U_0603_6.3V6MCD111 210U_0603_6.3V6M

CD18 10U_0603_6.3V6MCD181 210U_0603_6.3V6M

CD44 22U_0603_6.3V6MCD441 222U_0603_6.3V6M

CD6 0.1U_0402_16V4ZCD6 1 20.1U_0402_16V4ZCD13 10U_0603_6.3V6M

CD131 210U_0603_6.3V6M

CD12 1U_0402_6.3V6KCD122 11U_0402_6.3V6K

2

CD10 10U_0603_6.3V6MCD101 210U_0603_6.3V6M

CD5 0.1U_0402_16V4ZCD5 1 20.1U_0402_16V4Z

2

CD16 10U_0603_6.3V6MCD161 210U_0603_6.3V6MCD14 10U_0603_6.3V6MCD141 210U_0603_6.3V6M

CD8 0.1U_0402_16V4ZCD8 1 20.1U_0402_16V4Z

CD43 22U_0603_6.3V6MCD431 222U_0603_6.3V6M

CD7 0.1U_0402_16V4ZCD7 1 20.1U_0402_16V4Z

RD41K_0402_1%RD41K_0402_1%

27DQS129VSS31DQ1033DQ1135VSS37DQ1639

45DQS247VSS49DQ1851DQ1953VSS55DQ2457DQ2559VSS61DM363VSS65DQ2667DQ2769VSS71

CKE073VDD75NC77BA279VDD81A12/BC#

83A985VDD87A889A591VDD93A395A197VDD99CK0101CK0#

103VDD105A10/AP107BA0109VDD111

W E#

113CAS#

115VDD117A13119S1#

121VDD123TEST125VSS127DQ32129DQ33131VSS133DQS4#

135DQS4137VSS139DQ34141DQ35143VSS145DQ40147DQ41149VSS151DM5153VSS155DQ42157DQ43159VSS161DQ48163DQ49165VSS167DQS6#

169DQS6171VSS173DQ50175DQ51177VSS179DQ56181DQ57183VSS185DM7187VSS189DQ58191DQ59193VSS195SA0197VDDSPD199

BOSS1207

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DDR_B_SCS0#

DDR_AB_DQS#1

DDR_AB_D10

DDR_AB_D44

DDR_AB_DM7

DDR_B_ODT1DDR_B_CLK0

DDR_AB_D26

DDR_B_CLK1

DDR_AB_DM4DDR_AB_D38

DDR_AB_DM3

DDR_AB_D20

DDR_AB_D58

DDR_AB_DQS#2

DDR_AB_MA6

DDR_AB_D48DDR_AB_DM5

DDR_AB_D6

DDR_AB_D42

DDR_AB_D54

DDR_AB_D2DDR_AB_DM0

DDR_AB_D24DDR_AB_D0

MEM_MAB_EVENT#

+VREF_CAB+VREF_DQB

+VREF_CAB

DDR_B_CKE1DDR_B_CKE0

DDR_AB_RAS#

DDR_B_ODT1DDR_AB_BS0

+0.75VS

+1.5V

+1.5V+1.5V

Title

CD33 10U_0603_6.3V6MCD331 2 10U_0603_6.3V6M CD32CD322 11U_0402_6.3V6K1U_0402_6.3V6K

CD27 0.1U_0402_16V4ZCD272 1 0.1U_0402_16V4Z

RD71K_0402_1%RD71K_0402_1%

2

CD38 10U_0603_6.3V6MCD381 2 10U_0603_6.3V6M

CD28 0.1U_0402_16V4ZCD282 1 0.1U_0402_16V4Z

CD31 10U_0603_6.3V6MCD311 2 10U_0603_6.3V6M

RD51K_0402_1%

RD81K_0402_1%RD81K_0402_1%

CD25 0.1U_0402_16V4ZCD252 1 0.1U_0402_16V4Z

RD61K_0402_1%

2

CD30 10U_0603_6.3V6MCD301 2 10U_0603_6.3V6M

CD36 10U_0603_6.3V6MCD361 2 10U_0603_6.3V6MJDDR3H

27DQS129VSS31DQ1033DQ1135VSS37DQ1639

45DQS247VSS49DQ1851DQ1953VSS55DQ2457DQ2559VSS61DM363VSS65DQ2667DQ2769VSS71

CKE073VDD75NC77BA279VDD81A12/BC#

83A985VDD87A889A591VDD93A395A197VDD99CK0101CK0#

103VDD105A10/AP107BA0109VDD111

W E#

113CAS#

115VDD117A13119S1#

121VDD123TEST125VSS127DQ32129DQ33131VSS133DQS4#

135DQS4137VSS139DQ34141DQ35143VSS145DQ40147DQ41149VSS151DM5153VSS155DQ42157DQ43159VSS161DQ48163DQ49165VSS167DQS6#

169DQS6171VSS173DQ50175DQ51177VSS179DQ56181DQ57183VSS185DM7187VSS189DQ58191DQ59193VSS195SA0197VDDSPD199

BOSS1207

CD341 2 10U_0603_6.3V6M

CD29 1U_0402_6.3V6KCD292 11U_0402_6.3V6K

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PCIeR Gen3: Recommended value is 220 nF 10%.

3.3-V tolerant

For MEMCLK 1GHz Brand

skHynix

Samsung gDDR3-2Gbit

000

001 NC

4750 4750

NC

Samsung K4W2G1646E-BC11 1.5V/900MHz 111

CLK_PCIE_VGACLK_PCIE_VGA#

PCIE_ATX_C_GRX_P3PCIE_ATX_C_GRX_P2PCIE_ATX_C_GRX_P1PCIE_ATX_C_GRX_P0

+3VS

Title

0.2PCIE/LVDS

.1U_0402_16V7K VGA@

CV6.1U_0402_16V7K

VGA@

CV6.1U_0402_16V7K

CV2.1U_0402_16V7K

VGA@

CV2.1U_0402_16V7K

VGA@

RV212100K_0402_5%

.1U_0402_16V7K 1 2 VGA@

CV7.1U_0402_16V7KCV7 VGA@

.1U_0402_16V7K 1 2 VGA@

CV1.1U_0402_16V7K

VGA@

CV1.1U_0402_16V7K

VGA@

PART 1 0F 9

CALIBRATIONCLOCK

UV1A

SUN-PRO M2_FCBGA962

VGA@

AA30PERSTB

AH16TEST_PG

AA36PCIE_REFCLKNAB35

PCIE_REFCLKP

E37NCF35NC

F37NCG38NC

G36NCH35NC

H37NCJ38NC

J36NCK35NC

K37NCL38NC

L36NCM35NC

M37NCN38NC

N36PCIE_RX7NP35PCIE_RX7P

P37PCIE_RX6NR38 PCIE_RX6P

R36PCIE_RX5NT35PCIE_RX5P

T37PCIE_RX4NU38PCIE_RX4P

U36PCIE_RX3NV35PCIE_RX3P

V37PCIE_RX2NW38PCIE_RX2P

W36PCIE_RX1NY35PCIE_RX1P

Y37PCIE_RX0NAA38PCIE_RX0P

Y29PCIE_CALR_RX

Y30PCIE_CALR_TX

H32NCH33NC

K29NCK30NC

J32NCJ33NC

K32NCK33NC

L29NCL30NC

L32NCL33NC

N29NCN30NC

N32NCN33NC

P29PCIE_TX7NP30PCIE_TX7P

P32PCIE_TX6NP33PCIE_TX6P

T29PCIE_TX5NT30PCIE_TX5P

T32PCIE_TX4NT33PCIE_TX4P

U29PCIE_TX3NU30PCIE_TX3P

U32PCIE_TX2NU33PCIE_TX2P

W32PCIE_TX1NW33PCIE_TX1P

Y32PCIE_TX0NY33PCIE_TX0P

RV1 VGA@ 1.69K_0402_1%

RV1 1VGA@ 2 1.69K_0402_1%

CV5.1U_0402_16V7KCV5 VGA@

AR35TX2M_DPA0N

AP35TX2P_DPA0P

AU39TX1M_DPA1N

AR37TX1P_DPA1P

AU35TX0M_DPA2N

AW37TX0P_DPA2P

AR34TXCAM_DPA3N

AP34TXCAP_DPA3P

AG36NC#AG36AF35NC#AF35

AH37TX5M_DPB0N

AG38TX5P_DPB0P

AJ36TX4M_DPB1N

AH35TX4P_DPB1P

AK37TX3M_DPB2N

AJ38TX3P_DPB2P

AL36TXCBM_DPB3N

AK35TXCBP_DPB3P

AJ27RSVD/DIGON

AK27RSVD/VARY_BL

CV8.1U_0402_16V7K

VGA@

CV8.1U_0402_16V7K

VGA@

Trang 13

680 nF

R_pu R_pd

8.45KNCX

8.45K 2K2K4.75KX

111 = No usable endpoints

101 = Two usable endpoints

100 = Three usable endpoints

011 = Four usable endpoints

001 = Six usable endpoints

000 = All endpoints are usable

0

Base onVRAM ID

MLPS

PS_0[1]

PS_0[3]

PS_0[4] N/A

Reserved for internal use only Must be 1 at reset

PS_1[1]

STRAP_BIF_

GEN3_EN_A

Re-defined strap to indicate PCIe GEN3 capability

1 = PCIe GEN3 supported

0 = PCIe GEN3 not supported

PS_1[2] STRAP_BIF_

CLK_PM_EN

Determines whether or not the PCIe reference clock powermanagement capability is reported in the PCI configuration space (otherwise known as CLKREQB)

0 = The CLKREQB power management capability is disabled

1 = The CLKREQB power management capability is enabled

PS_1[3] N/A Reserved for internal use only Must be 0 at reset

To enable the external BIOS ROM device

0 = Disable the external BIOS ROM device

1 = Enable the external BIOS ROM device

PS_2[4] BIF_VGA_DIS

VGA disable determines whether or not the card will be recognized as the system's VGA controller

0 = VGA controller capacity enabled

1 = The device will not be recognized as the system’s VGA controller

Bits[5:1]

xx000 xx010 xx011 xx101 xx110 xx111 01xxx 10xxx

PD(1%) Cap PU(1%)

680nF 82nF 10nF NC

001

010

011

PX_EN :

High (3.3 V) switches the regulators

off (enter BACO mode)

Low (0 V) switches the regulators

on (Default)

CHECK VR

IF VR Suport PSI# and DPRSLPVR PU 10K

to +3VGS:

PSI# :Low load current flag

DPRSLPVR : Deeper sleep enable flag

Enable JTAG access

Reserved signal, for normal ASIC operation

GENERIC_X

Stereo-sync signal

Indicates left/right frame, or top/bottom field

Can be left unconnected if not used

Mapping to VRAM type please refer to page 6

PX_EN CLKREQB

I/O 3.3 V (VDDR3) PD-reset Power-state indicator.

Permits the voltage regulator to activate power-saving features.

IF VR Suport PSI# and DPRSLPVR PU 10K to +3VGS.

PSI# :Low load current flag DPRSLPVR : Deeper sleep enable flag

I/O 3.3 V (VDDR3) PD-reset

(Optional) An input which allows the system to request a fastpower reduction by setting GPIO_5_AC_BATT to low (0 V) The resulting state transition may disturb the display momentarily.

Power reductions that are less time critical should use the standard software methods in order

to prevent display disturbances.

Voltage control signals for the core (VDDC and VDDCI).

At reset, these signals will be inputs with weak internal pulldown resistors.

The VBIOS can define all voltage-control signals to be either 3.3-V or open-drain outputs (all signals must

be the same type).

The output states (high/low) of these pins are programmable for each AMD PowerPlay state when they are used as voltage control signals.

Note: GPIO_29 and GPIO_30 are only available on 28-nm ASICs, and are NC on earlier generation ASICs.

I 3.3 V (VDDR3) PD-reset

O 3.3 V (VDDR3) PD-reset

Serial-ROM output from ROM.

General purpose I/O or open-drain output.

Serial-ROM input to ROM.

Serial-ROM clock to ROM.

BIOS-ROM chip select.

Used to enable the ROM for ROM read and program operations.

Design: No use external VGA ROM, so use the test points.

Design: No use external VGA ROM, so use the test point.

Thermal monitor interrupt.

An input from an external temperature sensor (ALERTb).

O 3.3 V (VDDR3) PD-reset

Critical temperature fault (CTF) (active high) will output 3.3 V if the on-die temperature sensor exceeds

a critical temperature so that the motherboard can protect the ASIC from damage by removing power.

The CTF setpoint is 109℃ by default, and is programmed during ASIC initialization See the advisory for AMD PowerPlay states for more details.

(Optional) Voltage control signal for the memory-voltage regulator.

Note: This signal must be low (0 V) at reset (failure to do so will prevent booting).

I/O 3.3 V (VDDR3) PD-reset Disable MLPS: PU 10K ohm to 3.3V.

(Do not install for Mars) Enable MLPS: PD 10K ohm to GND.

(Install for Mars)

O Supports the CLKREQB feature for saving power to turn on/off the REFCLK clock on the ASIC.

+TSVDD

GPU_VID5

PS_0PS_1PS_2PS_3GPU_GPIO21

JTAG_TDIJTAG_TRSTBJTAG_TCKJTAG_TDO

GPU_GPIO10GPU_GPIO8

GPU_GPIO22GPU_VID3

GPU_VID1GPU_VID2

PS_2

VGA_SMB_DA2VGA_SMB_CK2

VGA_SMB_CK2

GPIO_16GPU_DPRSLPVR

GPIO_16GPIO_28_FDOVGA_SMB_CK2

GPU_DPRSLPVR

GPU_DOWN#

+1.8VGS

+TSVDD+1.8VGS

+3VGS

+3VGS+3VGS

TitleSize Document Number Rev

Security Classification Compal Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

0.2Main_MSIC

Custom

13 40Friday, June 14, 2013

Compal Electronics, Inc.

LA-A551P

0.2Main_MSIC

Custom

13 40Friday, June 14, 2013

LA-A551P

0.2Main_MSIC

Custom

13 40Friday, June 14, 2013

VGA@

RV684.75K_0402_1%

RV284.75K_0402_1%

VGA@

RV284.75K_0402_1%

RV238.45K_0402_1%

VGA@

RV238.45K_0402_1%

VGA@

RV228.45K_0402_1%

@

RV228.45K_0402_1%

QV1BDMN66D0LDW-7 2N_SOT363-6

VGA@

QV1BDMN66D0LDW-7 2N_SOT363-6

MLPS

BACO

DEBUG

THERMALDDC/AUX

DAC1GENERAL PURPOSE I/OI2C

MUTI GFX

DPDDPCDPBDPA

UV1B

SUN-PRO M2_FCBGA962

VGA@

SMBusPART 2 0F 9

MLPS

BACO

DEBUG

THERMALDDC/AUX

DAC1GENERAL PURPOSE I/OI2C

MUTI GFX

DPDDPCDPBDPA

UV1B

SUN-PRO M2_FCBGA962

VGA@

AJ33 TSVSSAJ32 TSVDDAL31 TS_AAK32 GPIO_28_FDOAG29AF29 DMINUSDPLUS

AM24 JTAG_TDOAL24 JTAG_TMSAK23 JTAG_TCKAN23 JTAG_TDIAM23 JTAG_TRSTBAD28 TESTENAL21 PX_ENAH13 DBG_VREFGAK24 HPD1AC30 CEC_1AH24 GENERICG_HPD6AH26 GENERICF_HPD5AJ24 GENERICE_HPD4AK20 GENERICDAJ20 GENERICCAK19 GENERICBAJ19 GENERICAAG33 GPIO_30AG32 GPIO_29AN13 CLKREQBAK13 GPIO_22_ROMCSBAJ14 GPIO_21AL13 GPIO_20_PWRCNTL_1AM17 GPIO_19_CTFAN14 GPIO_18_HPD3AG30 GPIO_17_THERMAL_INTAK14 GPIO_16AM13 GPIO_15_PWRCNTL_0AM14 GPIO_14_HPD2AM16AL16 GPIO_13GPIO_12AK16 GPIO_11AJ16 GPIO_10_ROMSCKAH15 GPIO_9_ROMSIAJ13 GPIO_8_ROMSOAK17 GPIO_7_BLONAJ17 GPIO_6_TACHAH17 GPIO_5_AC_BATTAN16 GPIO_2AH18 GPIO_1AH20 GPIO_0AJ26 SDAAK26 SCLAH23 SMBDATAAJ23 SMBCLKAP12 DBG_DATA23AU12 DBG_DATA22AW12 DBG_DATA21AR12 DBG_DATA20AT11 DBG_DATA19AV11 DBG_DATA18AP10 DBG_DATA17AU10 DBG_DATA16AW10AR10 DBG_DATA15DBG_DATA14AT9 DBG_DATA13AV9 DBG_DATA12AN7 DBG_DATA11AV7 DBG_DATA10AT7 DBG_DATA9AU6 DBG_DATA8AW6 DBG_DATA7AR6 DBG_DATA6AU5 DBG_DATA5AW5 DBG_DATA4AP6 DBG_DATA3AW3 DBG_DATA2AU3 DBG_DATA1AU1 DBG_DATA0AR1 NCAR3 NCAW8 NCAP8 DBG_CNTL0AU8 NCAR8 NCAK21 SWAPLOCKBAJ21 SWAPLOCKAAC29 GENLK_VSYNCAD29 GENLK_CLK

AJ31DDCVGADATAAJ30DDCVGACLKAK29NCAK30NCAM21NCAN21NCAM29NCAL29NCAM30NCAL30NCAM20AUX2NAN20AUX2PAL19DDC2DATAAM19DDC2CLKAL27AUX1NAM27AUX1PAN26DDC1DATAAM26DDC1CLK

AD33PS_3

AG31PS_2

AD31PS_1

AM34PS_0

AD32NC_SVI2AD30NC_SVI2AC31NC_SVI2AC32NCAG21NCAA29NCAF32NCAF33NCU13NCV13NCAC34VSS1DIAC33VDD1DIAE34AVSSQAD34AVDDAB34RSET

AC38VSYNCAC36HSYNCAE38AVSSNAF37BAD35AVSSNAE36GAD37AVSSNAD39R

AR22NCAT23NCAV21NCAU22NCAR20NCAT21NCAT19NCAU20NCAR16NCAT17NCAV15NCAU16NCAR14NCAT15NCAV13NCAU14NCAU32NCAT33NCAT31NCAR32NCAU30NCAV31NCAT29NCAR30NCAR26NCAT27NCAV25NCAU26NCAR24NCAT25NCAV23NCAU24NC

QV1ADMN66D0LDW-7 2N_SOT363-6

VGA@

QV1ADMN66D0LDW-7 2N_SOT363-6

VGA@

61

@

RV218.45K_0402_1%

VGA@

RV302K_0402_1%

VGA@

RV208.45K_0402_1%

@

RV208.45K_0402_1%

@

RV272K_0402_1%

@

RV272K_0402_1%

@

Trang 14

(MPLL_PVDD:1.8V@130mA )

(SPLL_PVDD:1.8V@75mA )

(SPLL_VDDC:0.95V@100mA )

SPLL_PVDD MarsCRB Design 120ohm 1 1 0.1u 1 1 1u 1 1 2.2u 1 1

SPLL_VDDC MarsCRB Design 120ohm 1 1 0.1u 1 1 1u 1 1 2.2u 1 1

Debug Only, for clock observation

As short as possible

Vgs=-4.5V,Id=3A,Rds<97mohm

+3VS to +3VGS +0.95VS to +0.95VGS

PXS_PWREN#

PXS_PWRENPXS_PWREN#

+3VGS

+3VS+3VGS

BACO POWERCustom

VGA@

RV44100K_0402_5%

VGA@

QV9B2N7002DW-T/R7_SOT363-6

VGA@

RV4647K_0402_5%

VGA@

RV48220K_0402_5%

@

CV1030.1U_0402_16V7K

@

12

CV2515P_0402_50V8J

VGA@

CV2515P_0402_50V8J

VGA@

12

VGA@

QV8A2N7002DW-T/R7_SOT363-6

VGA@

RV43470_0805_5%

VGA@

CV2415P_0402_50V8J

VGA@

CV2415P_0402_50V8J

H8MPLL_PVDDH7 MPLL_PVDD

AL10CLKTESTBAK10CLKTESTA

AW35XO_IN2

AW34XO_IN

AU34XTALOUTAV33XTALIN

Trang 15

Only for Kabini

BACO POWERCustom

VIN27

Trang 16

C yb

.ru

(VDD_CT:1.8V@13mA )

PCIE_PVDD MarsCRB Design

1u 2 2

10u 1 1

PCIE_VDDC MarsCRB Design 1u 7 7

10u 2 2

Route as differential pair (BIF_VDDC: 0.95V@1.4A) (VDDR3:3.3V@25mA) (VDDR1:1.5V@1.5A) BIF_VDDC Mars check list Design 1u 1 1

10u 1 1

PCIE_VDDC: 0.95 V @ 1.88 A (PCIe Gen 2.0) Maximum Current on +0.95VGS: "Sun": ~4.0 A for PCIe GEN 3.0 designs (estimated) Maximum Current on +1.8VGS: "Sun": ~0.5 A Need check all power current and decoupling capacitors after got SUN databook and reference schematic. (PCIE_PVDD: 1.80V@100mA) VDDR3 Mars check list Design 120ohm 1 1

1u 3 2

10u 1 0

0.1u 0 1

VDD_CT MarsCRB Design 120ohm 1 1

0.1u 1 1

1u 1 1

10u 1 1

VDDR1 MarsCRB Design 0.01u 5 0

0.1u 5 0

2.2u 5 5

10u 3 3

+0.95VGS +1.8VGS

+VDDR3 +VDDC_CT

+1.5VGS

+0.95VGS

+VGA_CORE

VCC_GPU_SENSE

VSS_GPU_SENSE

+1.8VGS

+0.95VGS +1.5VGS

+3VGS

+0.95VGS

+VDDR3

+VGA_CORE

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC

0.2 Power

C

LA-A551P

Title

0.2 Power

C

LA-A551P

Title

0.2 Power

C

LA-A551P

1

2

LV4

BLM15BD121SN1D_0402

VGA@

LV4

BLM15BD121SN1D_0402

VGA@

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

LV5

BLM15BD121SN1D_0402

VGA@

LV5

BLM15BD121SN1D_0402

VGA@

DVP

PART 5 0F 9

BACO

SENESE VOLTAGE

TRANSLATION LEVEL

I/O

MEM I/O

CORE

UV1E

SUN-PRO M2_FCBGA962

VGA@

DVP

PART 5 0F 9

BACO

SENESE VOLTAGE

TRANSLATION LEVEL

I/O

MEM I/O

CORE

UV1E

SUN-PRO M2_FCBGA962

VGA@

AH29FB_GND AG28FB_VDDCI AF28FB_VDDC

AG15VDDR4 AG13VDDR4 AG11VDDR4 AF15VDDR4 AF13VDDR4 AF12VDDR4 AF11VDDR4 AD12VDDR4 AG24VDDR3 AG23VDDR3 AF24VDDR3 AF23VDDR3 AG27VDD_CT AG26VDD_CT AF27VDD_CT AF26VDD_CT

Y7VDDR1 Y11U7VDDR1VDDR1 U11VDDR1 R11VDDR1 P7VDDR1 N11VDDR1 M11L7VDDR1VDDR1 L26VDDR1 L23VDDR1 L21VDDR1 L16VDDR1 L12K8VDDR1VDDR1 K13VDDR1 K11VDDR1 J9VDDR1 J7VDDR1 H10VDDR1 G29VDDR1 G26VDDR1 G23VDDR1 G20VDDR1 G17VDDR1 G14VDDR1 G11VDDR1 AL9VDDR1 AK8VDDR1 AJ7VDDR1 AG10VDDR1 AF7VDDR1 AD11VDDR1 AC7VDDR1

Y13 VDDCI V15 VDDCI T15 VDDCI T12 VDDCI R16 VDDCI R13 VDDCI R12 VDDCI N22 VDDCI N20 VDDCI N17 VDDCI N15 VDDCI N13 VDDCI M23 VDDCI M18 VDDCI M16 VDDCI M15 VDDCI AD16 VDDCI AD13 VDDCI AC15 VDDCI AC12 VDDCI AB13 VDDCI AA13 VDDCI Y28 VDDC Y26 VDDC Y23 VDDC Y21 VDDC Y18 VDDC Y16 VDDC V27 VDDC V24 VDDC V22 VDDC V20 VDDC V17 VDDC U26 VDDC U23 VDDC U21 VDDC U18 VDDC U16 VDDC T24 VDDC T22 VDDC T20 VDDC T17 VDDC R26 VDDC R23 VDDC R21 VDDC R18 VDDC N24 VDDC M26 VDDC AH28 VDDC AH27 VDDC AH22 VDDC AG18 VDDC AG16 VDDC AF22 VDDC AF20 VDDC AF17 VDDC AD26 VDDC AD23 VDDC AD21 VDDC AD18 VDDC AC27 VDDC AC24 VDDC AC22 VDDC AC20 VDDC AC17 VDDC AB28 VDDC AB26 VDDC AB23 VDDC AB21 VDDC AB18 VDDC AB16 VDDC AA27 VDDC AA24 VDDC AA22 VDDC AA20 VDDC AA17 VDDC AA15 VDDC

T27 BIF_VDDC N27 BIF_VDDC

U28 PCIE_VDDC T28 PCIE_VDDC R28 PCIE_VDDC N28 PCIE_VDDC M28 PCIE_VDDC L28 PCIE_VDDC J30 PCIE_VDDC J29 PCIE_VDDC H30 PCIE_VDDC H29 PCIE_VDDC G31 PCIE_VDDC G30 PCIE_VDDC AB37 PCIE_PVDD W29 NC_BIF_VDDC V28 NC_BIF_VDDC Y31 NC W30 NC AA34 NC AA33 NC AA32 NC AA31 NC

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

TV44

1

2

1

2

1

2

1

2

Trang 17

Close to pin Y12 and AA12

Place all these components close to GPU (Within 25mm)and keep all component close to each other

2GB/4pcs 2GB/4pcs

4Gbit 4Gbit

128M*16 128M*16

SA000068U20 Samsung

K4W4G1646B-HC11 SA000068R20

MT41K256M16HA-107G:E SA000065D30

Samsung

Micron 64bit

Size per part Configuration Total Memory Size/Qty

R_pu & R_pd resistor:

0402 1% resistors are required.

MAB0MAB2MAB4MAB6MAB8MAB10

DQMB#0DQMB#2DQMB#4DQMB#6

QSB0QSB2QSB4QSB6

QSB#0QSB#2QSB#4QSB#6MAB12

ODTB0

CLKB0CLKB0#

CLKB1CLKB1#

DRAM_RST#+1.5VGS

Title

0.2MEM Interface

ZZZ2

S1G

X76xxxxxLx1S1G@

PART 3 0F 9GDDR5/DDR3

M20MAA1_9/RSVD

M21MAA0_9/MAA_15

J19MAA1_8/MAA_14

H23MAA0_8/MAA_13

L15WEA1BK26WEA0BJ20CKEA1K21CKEA0K16CSA1B_1M13CSA1B_0K27CSA0B_1K24CSA0B_0K17CASA1BK20CASA0BK19RASA1BK23RASA0BH14CLKA1BJ14CLKA1G27CLKA0BH27CLKA0G19ADBIA1/ODTA1

J21ADBIA0/ODTA0

F8DDBIA1_3/QSA_7B

J11DDBIA1_2/QSA_6B

C12DDBIA1_1/QSA_5B

C16DDBIA1_0/QSA_4B

C20DDBIA0_3/QSA_3B

E26DDBIA0_2/QSA_2B

E30DDBIA0_1/QSA_1B

A34DDBIA0_0/QSA_0B

D7EDCA1_3/QSA_7

J10EDCA1_2/QSA_6

E12EDCA1_1/QSA_5

E16EDCA1_0/QSA_4

E20EDCA0_3/QSA_3

D25EDCA0_2/QSA_2

D29EDCA0_1/QSA_1

C34EDCA0_0/QSA_0

D9WCKA1B_1/DQMA_7

E10WCKA1_1/DQMA_6

A14WCKA1B_0/DQMA_5

C14WCKA1_0/DQMA_4

E22WCKA0B_1/DQMA_3

D23WCKA0_1/DQMA_2

C32WCKA0B_0/DQMA_1

A32WCKA0_0/DQMA_0

H17MAA1_7/MAA_BA1

J17MAA1_6/MAA_BA0

H16MAA1_5/MAA_BA2

J16MAA1_4/MAA_12

G16MAA1_3/MAA_11

L13MAA1_2/MAA_10

H20MAA1_1/MAA_9

H19MAA1_0/MAA_8

G21MAA0_7/MAA_7

H21MAA0_6/MAA_6

J26MAA0_5/MAA_5

H26MAA0_4/MAA_4

J24MAA0_3/MAA_3

H24MAA0_2/MAA_2

J23MAA0_1/MAA_1

G24MAA0_0/MAA_0

RV73100_0402_1%

VGA@

RV73100_0402_1%

VGA@

PART 4 0F 9GDDR5/DDR3

AH11DRAM_RSTV12MAB1_9/RSVDU12MAB0_9/MAB_15

W8MAB1_8/MAB_14

T8MAB0_8/MAB_13

AB11WEB1BN10WEB0BAA11CKEB1U10CKEB0AC10CSB1B_1AD10CSB1B_0L10CSB0B_1P10CSB0B_0AA10CASB1BW10CASB0BY10RASB1BT10RASB0BAD7CLKB1BAD8CLKB1L8CLKB0BL9CLKB0W7ADBIB1/ODTB1T7ADBIB0/ODTB0AM3DDBIB1_3/QSB_7B

AJ8DDBIB1_2/QSB_6B

AH3DDBIB1_1/QSB_5B

AC4DDBIB1_0/QSB_4B

W4DDBIB0_3/QSB_3B

P1DDBIB0_2/QSB_2B

K1DDBIB0_1/QSB_1B

G7DDBIB0_0/QSB_0B

AM5EDCB1_3/QSB_7

AJ9EDCB1_2/QSB_6

AH1EDCB1_1/QSB_5

AB5EDCB1_0/QSB_4

V5EDCB0_3/QSB_3

P3EDCB0_2/QSB_2

K3EDCB0_1/QSB_1

F6EDCB0_0/QSB_0

AK5WCKB1B_1/DQMB_7

AK6WCKB1_1/DQMB_6

AF5WCKB1B_0/DQMB_5

AE4WCKB1_0/DQMB_4

T5WCKB0B_1/DQMB_3

T3WCKB0_1/DQMB_2

H1WCKB0B_0/DQMB_1

H3WCKB0_0/DQMB_0

AA9MAB1_7/BA1Y8MAB1_6/BA0AA8MAB1_5/BA2AA7MAB1_4/MAB_12

AC9MAB1_3/MAB_11

AC8MAB1_2/MAB_10

W9MAB1_1/MAB_9

Y9MAB1_0/MAB_8

U8MAB0_7/MAB_7

U9MAB0_6/MAB_6

N9MAB0_5/MAB_5

N8MAB0_4/MAB_4

N7MAB0_3/MAB_3

P9MAB0_2/MAB_2

T9MAB0_1/MAB_1

P8MAB0_0/MAB_0

ZZZ3

H1G

X76xxxxxLx2H1G@

VGA@

RV7240.2_0402_1%

ZZZ5

H2G

X76xxxxxLx4H2G@

CV1591U_0402_6.3V6K

VGA@

CV1591U_0402_6.3V6K

ZZZ4

S2G

X76xxxxxLx3S2G@

RV714.99K_0402_1%

VGA@

RV714.99K_0402_1%

VGA@

Trang 18

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

0.2PWR_GND

AW18NC

AW28NC

AM32DP_VDDRAL38DP_VDDRAM37DP_VDDRAG34DP_VDDRAF34DP_VDDRAJ34DP_VDDRAH34DP_VDDR

AV19NCAU18NCAP23NCAP22NCAP21NCAP20NC

AV29NCAU28NCAP26NCAP25NCAP24NCAN24NC

AN32DP_VSSRAM35DP_VSSRAN38DP_VSSRAR18DP_VSSRAV17DP_VSSRAR28DP_VSSRAV27DP_VSSRAL34DP_VSSRAK39DP_VSSRAH39DP_VSSRAF39DP_VSSRAU37DP_VSSRAR39DP_VSSRAP39DP_VSSRAN34DP_VSSRAW22DP_VSSRAW20DP_VSSRAP19DP_VSSRAP18DP_VSSRAN19DP_VSSRAW16DP_VSSRAW14DP_VSSRAP17DP_VSSRAP16DP_VSSRAN17DP_VSSRAW32DP_VSSRAW30DP_VSSRAP30DP_VSSRAP29DP_VSSRAN29DP_VSSRAW26DP_VSSRAW24DP_VSSRAP28DP_VSSRAP27DP_VSSRAN27DP_VSSR

AP15NCAP14NCAT13NCAP13NC

AN31DP_VDDCAK34DP_VDDCAK33DP_VDDCAM33DP_VDDCAL33DP_VDDCAP33DP_VDDCAN33DP_VDDCAP32DP_VDDCAP31DP_VDDCPART 6 0F 9

Y39GNDY34GNDW34GNDW31GNDV39 GNDV34GNDU34GNDU31GNDT39GNDT34GNDT31GNDR34GNDP39GNDP34GNDP31GNDN34GNDN31GNDM39GNDM34GNDL34GNDL31GNDK39GNDK34GNDK31GNDJ34GNDJ31GNDH39GNDH34GNDH31GNDG34GNDG33GNDF39GNDF34GNDE39GNDAB39GND

AW39VSS_MECHAW1VSS_MECHA39VSS_MECH

AG22NC

F13GNDF11GNDE5GNDE35GNDC39GNDC1GNDB9GNDB7GNDB33GNDB31GNDB29GNDB27GNDB25GNDB23GNDB21GNDB19GNDB17GNDB15GNDB13GNDB11GNDAR5GNDAP9GNDAP7GNDAP11GNDAN8GNDAN6GNDAN30GNDAN2GNDAN11GNDAM9GNDAM31GNDAM11GNDAL8GNDAL6GNDAL32GNDAL26GNDAL23GND

AL20GNDAL2GNDAL17GNDAL14GNDAL11GNDAK7GNDAK31GNDAK11GNDAJ6GNDAJ28GNDAJ2GNDAJ11GNDAJ10GNDAH21GNDAG9GNDAG6GND

AG20GNDAG2GNDAG17GNDAF21GNDAF18GNDAF16GNDAF10GNDAE6GNDAE2GNDAD9GNDAD27GNDAD24GNDAD22GNDAD20GNDAD17GNDAD15GNDAC6GNDAC28GNDAC26GNDAC23GNDAC21GNDAC2GNDAC18GNDAC16GNDAC13GNDAC11GNDAB27GNDAB24GNDAB22GNDAB20GNDAB17GNDAB15GNDAB12GNDAA6GNDAA28GNDAA26GNDAA23GNDAA21GNDAA2GNDAA18GNDAA16GNDA37GNDA3GND

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Supported Memory Configurations: Up to 4 Gbit/part for DDR3.

close to UV7 UV8

close to UV9 UV10

close to UV7 UV8

close to UV9 UV10

MDB7

MDB31MDB27MDB29

MDB30MDB25

MDB18MDB22MDB19

MDB23

MDB32MDB33

MDB34MDB35

MDB36MDB37

MDB38MDB39

MDB63

MDB56MDB11

MDB53MDB55

MDB41

MDB43

MDB40MDB42MDB24

MDB47

MDB44MDB57

MDB58

MDB61

MDB60MDB62MDB4

MDB6

MDB2MDB3

MDB20MDB16MDB17

MDB48MDB49

MDB50MDB51

MAB15MAB15

VRAM Channel B Compal Electronics, Inc.

LA-A551P

VGA@

RV80243_0402_1%

VGA@

RV864.99K_0402_1%

VGA@ 1

96-BALLSDRAM DDR3

UV5

K4W1G1646G-BC11_FBGA96

@

96-BALLSDRAM DDR3

VSSQ D1

VSS A9VSS E1VSS B3

NC/ODT1

J1

VDD B2VDD D9

VDDQ A1VDDQ A8VDDQ C1VDDQ C9

VDDQ H2VDDQ H9

VSS J8VSS M1VSS M9VSS P1VSS P9VSS T1VSS T9VDDQ D2

RV914.99K_0402_1%

VGA@

RV914.99K_0402_1%

UV7

@

96-BALLSDRAM DDR3

VSSQ D1

VSS A9VSS E1VSS B3

NC/ODT1

J1

VDD B2VDD D9

VDDQ H2VDDQ H9

RV874.99K_0402_1%

VGA@

RV874.99K_0402_1%

VGA@

RV884.99K_0402_1%

UV8

@

96-BALLSDRAM DDR3

VSSQ D1

VSS A9VSS E1VSS B3

NC/ODT1

J1

VDD B2VDD D9

VDDQ H2VDDQ H9

RV934.99K_0402_1%

VGA@

RV934.99K_0402_1%

VGA@

RV83243_0402_1%

VGA@

RV894.99K_0402_1%

VGA@ 1

RV924.99K_0402_1%

VGA@

RV924.99K_0402_1%

VGA@ 1

RV82243_0402_1%

VGA@

RV82243_0402_1%

VGA@

RV81243_0402_1%

UV6

@

96-BALLSDRAM DDR3

VSSQ D1

VSS A9VSS E1VSS B3

NC/ODT1

J1

VDD B2VDD D9

VDDQ H2VDDQ H9

VGA@

RV904.99K_0402_1%

VGA@ 1

CV1600.01U_0402_16V7K

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EDP_TX0-LCD_TXOUT1-_R = LVDS_CLK = EDP_AUXP LVDS_DATA = EDP_AUXN

EDP_TX1-Reserve for EMI request

Carmera & Touch Screen

LCD Control

LCD_INV LCD_VDD

EDP_LCD_TXOUT1+_R

BKOFF#

BKOFF#_R

LCD_TXCLK+

LCD_TXCLK-EDP_LCD_TXOUT2+_REDP_LCD_TXOUT2-_R

BKOFF#_RLED_PWM

INT_MIC_CLK

USB20_N3_RUSB20_P3_R

USB20_N4_RUSB20_P4_R

+3VS+LCD_VDD

EDP_LCD_TXOUT0+_REDP_LCD_TXOUT0-_REDP_LVDS_DATAEDP_LVDS_CLK

+3VS_LVDS_CAMINT_MIC_DATA+5VS_LVDS_TOUCH

EDP_LVDS_HPD

INT_MIC_CLKINT_MIC_DATA

+3VS

Title

R11310K_0402_5%

C170.015u_0402_16V_X7RC17

RB751V40_SC76-2

12

R112100K_0402_5%

R13147K_0402_5%

U16

APL3512ABI-TRG_SOT23-5U16

APL3512ABI-TRG_SOT23-5

VIN5

SS4

FBMA-L11-201209-221LMA30T_0805

12

Vbus5

66

Tiêu đề	Compal La a551p (Zrmae, Zemae)
Trường học	Compal Electronics, Inc.
Thể loại	Schematic
Năm xuất bản	2013
Thành phố	Taipei

Định dạng
Số trang	40
Dung lượng	1,23 MB