Acer aspire switch alpha 12 SA5 271 pegatron P2JCC (HAWAII) rev 0 0 схема

Signal Name EC GPIO Use As Signal Name “EC GPIO Use As SKU Table B2 build Signal Name Title : SKU / Mount Table PEGATRON PROPRIETARY AND GONFIDENTIAL... Microsoft* Windows* 7 System

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SKU Table / Mount Table

CPU(1) _DDI / eDP

PCH(2)_ISH / GPIO / I2C

PCH(3)_HDA / DMIC / SDIO

PCH(4)_USB / PCIE / SATA

96_USB Type-C Receptacle

AO1 Power Tree

USB3.0(2) USB CONN x1 Light Sensor DMIC Page ss Capella/CM32181EA3OP

Speaker (CONN) Realtek / ALC255 LPC EC Smart Battery

Page 36 GPIO Shutdown IC

GMT / G709T1UF

( SDR104) Realtek / RTS5229-GR SM Bus(1) GPIO GMR Sensor

USB3.0(3)

Type C CONN USB2.0(3)

| KeyBoard (POGO Pin) | USB2.0(4)

Page 56

SPI SPI ROM 8MB W25Q64FVSSIQ (MB+BIOS+EC)

VO DB

Battery LED

(B/O) Docking Cable Touch (I2C) Debug CONN Power Buttom

USB2.0 +/-

Engineer: Willy Liao

IPEGATRON | Title : Block Diagram

TRON PROPRIETARY AND

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Signal Name EC GPIO Use As Signal Name “EC GPIO Use As

SKU Table (B2 build)

Signal Name

Title : SKU / Mount Table

PEGATRON PROPRIETARY AND GONFIDENTIAL

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A E537] DDI_TXP[o} EDP_TXP(0] pa EDP_TXPO [45] oO ' ’ F5g_] DDIT_TXNH] EDP_TXNI1] [eq EDP_TXN1 [45] DP x4

¡ạ Remove DDI1 Port : HDMI ' Fb3 | DDH_TXP[1] DDIT_ TXN[2 EDP_TXN[2 EDP_TXPH] [A2 EDB“TXNE tai Z ` WOHD 4L ~ ane

[95] DDI2 TXP0 Bet DDIE.-TXP[0j EDP EDEAUXP F45 <> EDP AUXP [45] AUX For eDP port is ne detected [95] DDl2_TXN1 D52 | DDI2_TXN[1] : port is deteccte

[95] DDI2_TXP2 re hai DD2 Txrjz] DDII_AUXN = No Connect [93] DDI2_TXN3 CBT| DDI2_TXN[3] DDIT AUXP „7 543016 page 824

DDI2_AUXP DDI2_AUXP [95]

DISPLAY SIDEBANDS RNS EXT SGI# B0307 1 AAA 2 10KOHM

'00KOHM @ Ê 20OMm T00KOHM an `

141024 follow PDG V1.0 Table 10-4 1x r0402 +x_r0402 tx_r0402 onm pull down on ide

\ 4 0315 1 2 4ãOhm tx 10402 H PEC = A52 CATERR#

@ ———=—=—=—==m=e em mm mm CPU MISC PROC TCK - *e

H Remove XDP BPM# ! ` D55 | BpMniTi PROC TDO | A61 PROG TDI xe: Ê SE T50 ca DP 100 CPU PCH JTAG TDO _ XDP TDO GPU R0323 2 hs 1_5iOhm

†x_r0402 m============== X|BPMI PROC_TRST#

" T031 @ 1 CPU GPa Ag GPP _ESICPU_GPo PCH JTAG_TCK cL 1 @ T0315 PCH TRST ŒPUN XDP TRST GPUN 1 @ 70317

E6] TP_NT[ —> T013 Tosa 1 CSP GBS EPU GP2 Ayb | GPP B3/CPU_GP2 BAS | GPP_E7Z/CPU GP1 PCH JTAG_TDO PCH _JTAG_TDI DO S PCH JTAG TDI XDP_TDI CPU 1© Toss

GPP_B4/CPU_GP3 POH are PUN XDP TGLK JTAGX XDP TGLK R0324 2

R R

D

= Pu) cl a <T_|THRO_CPU [30]

GND VCCSTG

s * (or Equilvalent)

a — Stubs on JTAG nets should not more than 200ps

— R1, R2 should be placed to within 200ps of PROC_TCK pin, PCH_JTAG_TDO, respectively

7 Rt Fa uae be lode mtn Zp ON Title : cPu()_ppvep

TT GOB9 AO (ECH V1 0Á) GND phe vô) pins, ITP_PMODE, PROC_PREQ#, PROC _PRDY#, RSMRST#,SYS_RESET#, CFG[3], SPIO_IO2 PEGATRON PROPRIETARY AND CONFIDENTIAL

—TP should be laced to within 250ps of the respetive Skylake pins, and the distance between TP and termination (for JTAG, if any) must be Engineer: Willy_Liao

— TP = Test Point Pad (size - 18 mil min, 25 mil preferred) The pad side must meet the industrial standard of Boundary Scan Test Size Project Name Rev

Date: Thursday, March 31, 2016 Bheet 3 of 100

5 I 4 I 3 I 2 I

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IL Channel A[0 63] IL Channel BỊ0 63]

5 oe NIL Channel A[32 47] 988.560! rs Fe SIRES er sor coors Ba NIL Channel Al48 63} perce I1

: - 5 aa DDR0 DGI4; DDRO_CKE[0] _DIM0 GKE0 [16] © = — a DDR1_DQ[4™PDRO_DQ/20 s

Đ, AD AN70_} DDRO_DO[5 DDRO_CKE[1] _DIM0_CKET [16] — TWAT A DDR1_DG[5ØDDR0_DG|21 DDR1_CKE[0] [17]

< AD AN71_| DDRO_DQI6 DDRO_CKE[2] DIMO_CKE2 [16] < WAT DDR1_DQ[6§PDRO_DQ/22 DDR1_CKE[1] 7]

os AD AR7T | DDR0_DGJ1 DDR0_ODT[0| _DIM0_ODT0 [16] GS WAT DDR1_DG[1DDR0_DG[2 DDR1_CS#{1] [17]

WAL BBe5_) DDRO_DCfi DDRO_MA[9}/DDRO_CAA[1}/DDRO_MAIS] |~Ba5a MA A DDR1_DG[1##/DDRO_DC[3 DDR1_MA|5/DDR1_CAA[O/DDR1_MAI5] [Apso MP CAA]

~ AT a 3 DDR0_DG[1ẩWDDR0_ DGI3 DDR0._ MA[7/DDE0_ CAAJ4J/DDR0 MAI7| â vi — wo se DDR1_DO[1#/DDRO_DaTS DDR1 MA[8|/DDR1 CAA[3|/DDR1 MA[8] Tp - —

: ee AY65-| ODRO_DQ[2H/ODRO_Da/s DDR0_MAI12VDDR0_ CAA[6/DDR0 MAI12| a MA 2 sare DDR1_DQ[2/DDRO_DaTs: DDR1_BA[2/DDR1_CAA[5/DDR1_8G[0] -anso ECAR

Q TT BASS] DDR0_ DG|2'DDR0_ DO|3 DDE0_MA[11DDR0._CAA[7]/DDR0 MAI11] | Bazz MA , — T2 DDR1 DGJ2DDRo_DGj5 DDR1 MA[12J/DDR1 CAAIưVDDR1 MAI12] | ANz8 WE CAE

Ø, San BB85-| DDR0_ DGI2DDR0_ DGI3 DDE0_MA1B/DDR0_CAA[8J/DDR0_ACT# | Avsz TA 3 ——— DDR1.DGI2f#DDRo_Do5 DDR1 MA[11J/DDR1 CAA[7JDDR1 MAI11] | ANE5 WO CARS

ø I | c WAT | DO DDRO_| a Z

7 _*

œ = G57] DDR0_ DGI2JDDR0_ DGI4 DDE0_WE#/DDR0_CA8I2l/DDR0_MA[14] | ALE0 TA GS a7 DDR1 DGI2'DDRo_DG[5 DDRi_CAS#/DDR1_CAB|1/DDR1_MA[15] F-ayar Wo CABS

GS a AY61 | DDRO_DO[2H/DDRO_DayA! DDE0_RAS#/DDR0_CABI3]/DDR0_MA[16] | As2 MA > TT DDR1.DGI2#'DDRo_DG[si DDRi_WE#/DDR1_CAB[2/DDR1_MAl14] ayaa WE CABS

> a ASG] DDRO_DQ|24/DDRO_Dal4 DDRO_BA[O|/DDRO_CAB[4/DDRO_BA(O] -ayst MA = se DDR1.DGI2#'DDE0_DGJ[6 DDR1_RAS#/DDR1_CA8I3/DDR1 MA[16] |'BBaZ MB CAEL

AW39-] ODRO_DQ[3#/ODR1_DarO DDE0_MA[10J/DDR0_CA8[7]/DDR0_ MA[10] | BBB0: TA DDR1 DGI3ƒDDR1 DGJ1 DDR1_ 8A[1DDR1_CABI6]DDR1_BAI1] | was WO CREF Ayšy | DDR0_DGI3'DDF1_DGỊ1 DDE0 MA[1]/DDE0_CABI8]DDR0_MA[1] | Xyzp MA ¬ DDR1 DGI3f'DDR1 DGJ1 DDE1 MA[10/DDR1_CAB[7JDDR1_MA[10] aya WE CABS

in AWS7 | DDR0_DGI3fWDDR1_ DG[2 DDF0_MA[0]/DDR0_CAB[9]/DDR0_MA[0] ['ERED =œ DDR1_DGISẨ'DDR1_ DO[1 DDR1_MA[1I'DDR1_CA8[8l/DDR1_MAITI "Bag MB CABO

S, Aä7_| DDE0.DoJ3JDDR1 D5 NỊL Channel BỊ32 47] AMPD MA a mã DDRI1_DG[3'DDR1_DG[2 anne “ DDR1_MAI4| —<

ma BBš7 | DDR0_DGJ3ẨDDF1DGj6 s1 v'0DR0_DQSNI0I [AMgg—M XI a —- DDR1_DQ[3q/DDR1_Daj2aq] NIL Channel B[48 63] AH66_ MA DQS#2

= ® XW Số | DDR0_DGI4[DDRI DOjgĐ_ SPANRe! DDRO_DQ[3#/DDR1_DQI7| A PASTO.71 DDRO_DQSPI0} DDR0_DGSNII] AT TT ——— & 2 —r sn DDR1_DGI3W'DDR1_Do[2 DDR1_DG[4ĂFDDR1—Doj[2jf t Chamnelÿ DG5/9.7] > oDnị- pQspiÐVDDE0-DOSPII | ABđ—IT2-Bšz sDDR1_DOSNI0J/DDR0_DOSNI2| 5

° Aysg-| DDR0_DO|4fDDR1- DOI9 ` a DDRO_DQSPIt] Haas Sa c —- DDR1 DG|4'DDR1 DGj2 + DDRI-DOSN1]/DDR0-DQSNI3] Faoy0—H A0055

o AW5ä3-| DDR0 DG|4ÿDDR1 DOj[1 % „„+**”” DDR8°DGQSNI2JDDR0_DOSNI4] F Xee Tas œ —- DDR1.DGI4#fDDR1 DG[2 »„ cả DDR1_POSP[1/DDRO_DQSPI3] -aRas— MA DOSE

<= Bags] DDRO_DQ|4HPODR1_DaIt % DEE0_DGSF[2J/DDR0_DOSPl4] FAvoi A DOSES 6 —- DDR1_DGJ4fW'DDR1_DGI2‡ se DDR† DQSNI2|/DDR0_DQSNI6] [AReg—M-A DOS6

Oo BAS5 | DDR0_DGI4DDR1_DGỊ1 ` „ĐDR0_DOSNI3|/DDR0_DGSNI5] |-BAgơ ADAGE = —r DDR1_DGJ4#'DDR1_Do[2 DR1_DQSP[2/DDRO_DQSP{6] -aRei— OST

=! Bags] DDRO_DQ[4#/ODR1_Daft „s° DDR0_DQSEI3|/DDR0_DOSPl5] | BA38 Bast = —r DDR1_DGjJ4W'DDR1_DO[2 *„ÐDR1_DOSNI3]/DDR0_DOSN[7] [RR80—M_-A-DOš7

Zz Begs] DDRO_DO|4MPODR1_DaIt DDR9.DESN[4/ODR1_DQSNI0] F-ayag DưS0 Zz —- DDR1DG|4f#'DDR1 DGj3 „*®“DDR1_DGSEI3I'DDR0_DGSPI7] | AT3g ee

= Xväi | DDR0_DGI4f'DDE1_DGỊ1 2ÐB0_DGSRf1J/DDR1_DGSPI0] -aysg Soot DDR1_DGJ4f'DDR1_DGI3 ,„° Dia] .DESN[4/0DR1_DQSN[2] Fangs BASE

= AW31-| ODRO_DQ[4#/ODR1_DQIS at DDE0_DOểN|5J/DDR1_DGSNI1] [-Bašz Basi DDR1_DGI4 „:ÐỞl_DQSP(3JDDR1 DOSPI2I [ATš> BOS

= AYSQ-| DDRO_DQ[4H/DDR1_DQSM vii chanin DDR0 ,3GSP[SJ/DDR1_DGSPI1] | BA30 Bast = —r DDR1_DG[4 m [5/DDR1_DOSNI3] |ƑAEš2 Bass

= = AWa9-] DDRO_DO[SPDDR1_DABM — basia.t.a.5) %- DDR8“DOSNI6]/DDR1 DOSNI4] | Avăo Baer oO —mr DDR1 DGIðI NI chan tUA DDR†,ÐSPI5/DDR1_ DGSPI3] [A35 BOSH

q = BEST] DDR0_ DGI5DDR1_ DGI3 %+ DØR0_DGSPi6J/DDR1.DGSPI4] FAyšs SASS : <r DDR1_DG[5 DGSi2,3,607] „` DDRI DOSNI6] AR27 BASE

a = Bag | ODRO_DO[SHVDDR1_DQIS * DDR0_DOSRIZPDDF1_DGSPI5] |” aa ¬ẫ DDR1_DGI8i v «„DDR1_DGSN[7] arst BAST Controls reset to the memory subsystens,

Sa ce casero TT] _ ¬ oon aero [At Hp yt eo] wo = —MT sa oa — (not applicable to LPDDR3) cea noi

interleaved(Symbol default)| Non-interleaved

BYTE 1 DQS/DQS#[0,1] cl 00402 R0412 R0407

exo [ >00R.P6 GTRL [85] BYTE 4 QS/DQS#[O 7] ChannelB DO[16 31]

BYTE7 DOS/DOSZ[4,5] “ ‘x 10402 BYTE 7 ;

BG1-NB4 Size Project Name Engineer: Willy_Liao Rev

Date: Thursday, March 31, 2016 Bheet 4 ot 100

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SKL 2+2, +V1.8VS_EDRAM / +V_EDRAM_VR /+V_EOPIO_VR

From Intel, SKL-U 2+2 reserve these pins PD to GND

Remove

R0528/R0529/R0530 /R0531 /R0532

R0533/R0534/R0535

Resistor change to Test Point

Delete for power layout limitation

+VGORE

o

G0506 10PF/50V tx_c0201

c =

U0301L

2 Pøe | VOCOPC 1 VCCOPC 2 Vô2 | 'CCOPC_3

VCCECPIO_SENSE VSSECPIO_SENSE

VGG_19 VCC_21 VCC_22 VCC_24 VCC_26 VCC_28 VGG_30 VCC_31 VCC_32 VCC_34 VCC_36 VCC_SENSE VSS_SENSE VIDALERT#

VIDSCK VIDSOUT VCCSTG

+VCORE

°

D64 G20

+VCCFUSEPRG NB_R0402_20MIL_SMALL

@

1%

R0521

1000hm 1x_r0402

VIDSCK_R

+VCŒGST_GPU

R0523 1000hm tx_10402 1%

VIDSOUT_R

0524 1 _I0402_0ohm 2 00hm <<— ]VR_SVID ALERT# [80]

R0522 C0505

45.3Ohm 1UF/6.3V tx_10402 tx_c0402 1%

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[80] VCCGT_VCCSENSE

[80] VGGGT_VSSSENSE

+VGGGT

đè Roso9

1000hm tx_10402 1%

Pull H/L near CPU side

R0610 1000hm tx_10402

VCCGT_55 VCCGT_SENSE

VCCGT_80

VocGTx_1

VocGTx 12 VocGTx 14 VocGTx 16 VocGTx 18 VocGTx 20 VocGTx_ 21 VocGTx 22 VocGTx 24 VocGTx 26 VocGTx 28

VCCGTx_SENSE VSSGTx_SENSE

+VGGGTO———< +VCCGT [80]

+VCGGT

“worst U0301M ọ

CPU POWER 2 OF 4 70 =.s=ss=si

tx 0201 na Ƒ—— sẽ | VGOGL + VOCGT_80 [Rữg—] VOCGI-61 -Re7 ——J Đ ae reserye 1

ooeosoe VCCGT_63 Reg

VCCGT_64 FRI vCCGT_65 FRI]

VCCGT_66 VOCGT_68 VOCGT_70 VOCGT 71 VOCGT_72 VOCGT_74 VCCGT_78 VOCGT_78

1 â T0801

Resistor change to Test Point Delete for power layout limitation

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$—————pDD-—| pt

3MM_OPEN_BMIL 1 10PF/B0V 10UF/8.3V 10UF/8.8V 10UE/6 3 Our 3V 10UE/83 oUF 9 TU, 3V SUG 3V 1UF/8.8V SUFI 3v BB23 | ‘Das WCQO s | A28 4 0201 du) by 202012 txc0201 , | tx c0201 tx_00201 4y

17 12 12 soo tx 00201 ~ tx 60603 102,tB9tx c0603 102,IB9x o0603 of of t0 h89 c0603 t02 of Bb c)ên5 102 a Bn 00608 10 9tx_c0201 - oy tx_c0201 A| tx c0201 tr c0201 5¬ vpno 6 BBS2 Qu VCCIO_6 Fangs _5 AaMs0 1

“141030 Merge Power PDDGU.91 Table5-1

141127 65u sec full load ready

PEGATRON PROPRIETARY AND CONFIDENTIAL

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U0301P U0301R

GND 1 OF 3

>=Í>|[>|>|>|>| |>=|>|>|>‡

>>|

940432

017010000015

U0301Q GND 2OF 3 VSS_141 VSS_209 VSS_142 VSS_210 VSS_143 VSS_211 VSS_144 VSS 212 VSS_145 VSS 213 VSS_146 VSS 214 VSS_147 VSS 215 VSS_148 VSS_216 VSS_149 VSS_217 VSS_150 VSS_218 VSS_151 VSS_219 VSS_152 VSS_220 VSS_153 VSS_221 VSS_154 VSS_222 VSS_155 VSS_223 VSS_156 VSS_224 VSS_157 VSS_225 VSS_158 VSS_226 VSS_159 VSS_227 VSS_160 VSS_228 VSS_161 VSS_229 VSS_162 VSS_230 VSS_163 VSS_231 VSS_164 VSS 232 VSS_165 VSS_233 VSS_166 VSS_234 VSS_167 VSS_235 VSS_168 VSS_236 VSS_169 VSS_237 VSS_170 VSS_238 VSS_171 VSS_239 VSS_172 VSS_240 VSS_173 VSS 241 VSS_174 VSS_242 VSS_175 VSS_243 VSS_176 VSS_244 VSS_177 VSS_245 VSS_178 VSS_246 VSS_179 VSS_247 VSS_180 VSS_248 VSS_181 VSS_249 VSS_182 VSS_250 VSS_183 VSS 251 VSS_184 VSS_252 VSS_185 VSS 253 VSS_186 VSS_254 VSS_187 VSS 255 VSS_188 VSS_256 VSS_189 VSS_257 VSS_190 VSS_258 VSS_191 VSS_259 VSS_192 VSS_260 VSS_193 VSS_261 VSS_194 VSS_262 VSS_195 VSS_263 VSS_196 VSS_264 VSS_197 VSS_265 VSS_198 VSS_266 VSS_199 VSS_267 VSS_200 VSS_268 VSS_201 VSS 269 VSS_202 VSS_270 VSS_203 VSS 271 VSS_204 VSS 272 VSS_205 VSS 278 VSS_206 VSS 274 VSS_207 VSS 275 VSS_208 VSS_276

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-1

+1.8VSUS O——<_] +18VSUS [26,84]

E68 Bay | CFG[0] RSVD_TP_3 bases BBE

K46 BB5 Placeholder only Does not need to be stuffed

XCKá5 | RSVD_9 TP4[Ƒ—< Placement are required for future platform compatibility purpose only

VSS_360 RSVD_TP_7 Remove SNN From'Tritel;-SKL-U 2+2 remove these pins

Intel confirm NC T0818 Cộ T RSVD_VSS_G65 G85 | Wee 361 RSVD-TP.ẽ [AW7ð

Signal Name Description Dir rood Tyre Availability

Configuration Signals: The CFG signals

have 4 default value of '1' if not terminated

on the board Refer to the appropriate

platform design guide for pull-down recommendations when a logic low is desired

Inte! recommends placing test points on the

board for CFG pins

* CFG[0}: Stall reset sequence after PCU

PLL lock until de-asserted:

— 1= (Default) Normal Operation;

No stall

— 0= Stall

* CFG[1}: Reserved configuration lane

Numbering Reversal CFG[2], CFG[6:5) and

— 1= Normal operation CFG[7] are relevant CFG[19:0] — 0 = Lane numbers reversed yo GTL SE | for H and S-processor

CFG[3): Reserved configuration lane line only and test point

* CFG[4]: eDP enable: may be placed on the

— 1= Disabled board for them

— O= Ena CFG[6:5}: PCI Express* Bifurcation

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Bề B7

MA D2 | CA7 = DG7[ƑEii A LA_D[7:0] [4]

MA C2 | CA8 cag p= DQ10 HE °G©s[río bas A 2 -

batt FE

Pearce BO | ba Peter K3 ote ke pats bee bai Hep — tr - MA DI31:24| [4]

[Se oe CKE1 F1 DQ17 H ˆ

pats Frat A DO19

PP — cst_n ` baat Fito i 2

DQ22 L8 — no2 Lên - M_A_D[23:16] [4]

ni Be] DMI | DM0 "“ DG24 DQ25 0 Ầ - bạ] DM2 DQ28 é 2 DMS Bo DQ27 [EïT 2

DNU t2 Min: aio = Close To Memory Die

<S=5——— 8 DQS0_c A8

Gio voD2_15 Fag +1 2V

SSE vest DQSI.c oa 7 hg vDD2_1 F55 4 ¬1-

Tế | VSS 3 VDD2_18 we] VSS_18

‡ Nữ | VSS 14 E2 N5 | VSS 7 VDDCA_1 Fgẽ +1.2V

Bử | VSS 15 VDDCA_2 BE RE] VSS_8 vopca_§ Hs 73] VSS_16 vDDCA_3 ye TH] VSS_4 VDDCA_4

a VDDG_15

‡ Bï2-] vSSQ 1 VDDG 4 [R2 Ga] VSSO_14 VDDQ_16 BTz BïZ-| vssG 2 VDDG_17 FT { ES] VSSO_15 VDDQ _11

at

+——— | vsso 1o Viet(CAI [IS Y.VREE_CA DIMM0

+—— | vsso 5 weibQ@) ——o _+V.vREF~DQ DIMM0

PL ——ï|vwso

“li | vssG 13 cor R#———— w.^ 0M pro 14]

‡ Mẽ | VSSQ 11

1 M2 | ee lý zoo 83 B1801 1 2 AA_ 2 243OHM tx 0402 1%

Bie] VSSQ_7 Ja, -B4 B82 TAA 2 2450HM tx 0402 7 |

Bế | VSSG 18 T6-| VSSG 8 oa Tis] V8SQ_9 VSSQ_19 Nc_2 Lgg— NC_3 Pgs

GND H9CONNNBLTMLAR-NTM 0318-01 1000

0315-01GROPB SKUZ 0315-01960PB SKU3 0315-01GJ0PB SkU4 0315-01A20PB

+1.2V +V_VREF_CA_DIMM0

G1815 10UE/6.8V 10UE/6.3V G1816 —GI817 C1601 G1602

tx_ 60803 102 hậQ] 1UE/68W| 1UE/6.3V 0.047UF/16V,) 0.047UF/16V

1x_p0402 tx_c0402 tx_c0402 tx_c0402 tx_c0402

[4] M_A_CABI9:0]

[4] M_A_DIMO_CLK1 [4] M_A_DIMO_CLK#1 M_A_DIMO_CKE2

ï-| DNU 9 AS 3| DNU 2 VDD1_1 Fx 77] DNU_10 VDD1_ 3 An

5 | DNU 3 VDD1_5 LẠ) ï-| DNU 11 vDD1_7 Fag

5 | DNU 4 VDD1_9 Fg

Z | DNU 6 VDD1_2 Fy ñ5 | DNU 8 VDD1_4 Fg DNU_ 12 VDD1_6 Fy

vDD1_8 Foto vDD1_10

+1.8V

O JP1802 1MM_OPEN_M1M2

@

+1.BV_DDR3

ọ 10UF/6.3V

a| X 00603 i02 hậgj tx c0603 102 hậ9| tx c0603 102_h39

GND

†x_p0402 elle oe CLO SG De Mamouve Dice

‡x 60402 | 1x c0402

G1809 G1810 1UF/63V| 1UF/6.3V 1x 00402 tx_c0402

@ 2 ö

0.047UF/18V _p0402

0 VDD2 5 2 tx_c0402

VDD2 8 B2 VDD2 12 B5 | VSS 1 VDD2_ 7 GE] VSS_10 vbD2_13 Faqs Er] VSS_11 VDD2_20 E5 | VSS 6 VDD2 8 VSS 12 VDD2_2 ƑB VSS 13 VDD2 9 VSS 2 VDD2_14 FT]

VSS 19 vDD2_16 Fy VSS 3 VDD2 18

Mỹ | V5S_18

Na | VSS_14 F2 VSS_7 VDDCA_1 [G5 12V VSS 15 VDDCA_2 Fag

VSS 8 VDDCA_5 [TE VSS 16 VDDCA_3 Fi VSS 4 VDDCA 4 VSS 5

At VSS 17 VDDG 8 FErz ©:1.2V

VDDG_12 [E8

3 VDDQ_1 FET1ø———]

Bộ | VSSCA 1 VDDG_13 F@†2 FT| VSSCA_2 vDDQ_14 Fag Gs] VSSCA_5 VDDQ_2 Fag

Ga | VSSCA_3 VDDQ_5 Fa T2] VSSCA_6 VDDG_9 T M2 | VSSCA_7 VDDG_ 6 [FTTø P5 | VSSCA_8 VDDQ_7 Fg VSSCA_4 VDDQ_3 Faq VDD@_10 F743

VDDG_15 Fg

VSSG 5 Vref(DQ) R——© +V_VREF_DQ_DIMMO0

VSSQ_10

ae VSSQ_12 J8 T9 | VSSG_13 ODT

Mô | V5SG 11 V8SQ_6 B3 2 2430HM_ tx 10402 1%

6 | VS5@_17 200 2_2430HM 10402 1%

B12 | VSSG_7 zat RE] VSSQ_18

Tø | V8SG_8 Cá

NG 1 H9GCNNNBLTMLAR-NTM 0315-011000

Ul 0315-01GROPB SKU2 0315-01960PB SKU3 0315-01GJ0PB SKU4 0315-01A20PB

G1811 G1853 10UF/8.3 10UF/6.3V a| x c0603 i02 hậg| tx c0603 102_h39 GND

+1.8VO——< +1.8V [57,91]

+1.8V_DDR3 O—<——]:18V D0DR3 [17]

+l.2V O—<X ——]+12V_ |4,7,17,18,83]

+0.8VSO——< ——]+0.6VS [17,57,83]

+V_VREF_GA_DIMM0 @—<“——]+V VREF_CA DIMM0 [18]

+V VREF_DQ DIMM0ũ_ O——<—]¿v VREF_DQ DIMM0 [18]

^^ A^-2 68Ohm A_CAB5

G1833 0.1UF/6.3V | 0.1UF/6.3V

Trang 11

LPDDR3 Channel B

We CaaS OG CAS pm DO8 Frio == pas a BaF +V_VREF_DQ_DIMM1 ©—<—]:v vREF_DQ_DIMMi [13]

[4] MB DIM0 CKE1 CKE1 DQ17 D [4] M_B_DIMO_CKE3 CKE1 DQ17 D52 B170 2 Ba0nm I

[4] M_B_DIMO_CS#1 C81 n DG21 D C8§1_n DG21 0 BE RIT

BỆT | DNU 2 voor_1 FA O¿1.8V_DDB3 Bộ | DNU 2 vopi + LÃ O:1.8V_DDR3 a| tx 60603 402 hậgj tx c0603 102 hậ@[ tx c0603 102 h39 R :

U15 — - | U @ Wik} = = LU T T T T MB DIM0 CSƒ1 R1727 m

VDDI_8[ Ủiõ GND Close To Memory Die vDD1_8 [iG GND Close To Memory Die 1UF/6.3Wj[ 1UF/63W| 1UF/6.3W[ 1UF/6.3V MB DIMO CKEI Ri/26 m

B2 |] MB DQS72 LB Sry DQs2_c | VDD2_4 FEE——— 10 G5 I T0PE/80V tx, 0402 B6 [4] 14 we posts M_B_DQ = Pit DQS2_c = VDD2_4 FHE—————O 10 G5 3 T0PE/80V tx, 0402 vv

[4] M_B_Dass QF pass vop2 71 Fe © [4] M_B_DQs7 Qn pass voD2 11 LỆ ©

B3 [4] M_B_DQS#3 Dit_} DOS3_c 0GS3 t VDD2_19 1 [FT ie = GND BT [4] M_B_DQS#7 Fe Díi | D@85_: DQS3_c VDD2_19 -11 [ H2 = GND Hav ©

VDD2 6 Close Toa Mammon Die VDD2 6 Close Toa Mammon Die

Ri T2-| VSS 16 _ VDDCA_3 [p 5 Te R TE] VSS_16 vị VDDCA_3 5 72 Faye c0402| b c0402] b c0402) bx c040 £040: 040; 0402} tx_c0402

ae VSSCA 5 VDDG 2 ae as VSSCA 5 VDDO 2 ae ix 60402 ix 60402 ix 60402 ix 60402 ix 60201 ix 60201 ix c0201 tx_c0201

Beet, C6 years VDDQ Tờ tues Tia 12 Beye, C6 Và q2 VDDQ 17 ues Pi Ri2 f G1740 T1 G1741 G1742 12 G1748 L2 G1746 + G1747 C1748 + Le C1749 LS ay 2h, 22UF/6.3V C1751

Die | yee xã vpport LS Die | yes ‘ope, Lat a| IUF/68W| 1UF/63W| 1UF/63W| 1UF/63W| 1UF/63W| 1UF/63W| 1UF/63W| 1UF/63W| XSR./20% | 22uF/6.3V E6 Mon OL E6 Mà QL x 60402.) x co402] px c0402) px c0402) px c0402) px c0402) px c0402) tx c0402) tx c0803 t02 hài 1x r0402 h28

K10 [8 | VSSG_13 — ODTF d8 M_B_DIMO_ODTO [4] K10 [8 | VSSG_13 — ODT J8 — MB DM0 ODT0 G1788

MIZ VSSQ_17 Lt z00 B3 RÍ701 RT702 Í MIZ Nẽ | VSSG_ 17 f z00 B3 R1703 T770 1 x 10402 h28`` i abe, nae” i bao hoe 5 robe noe! i 10402 ne Di ree ‘ne

Trang 12

+V_VREF_DQ DIMMIO————< ]+V VREF DQ_DIMMI [17]

+V_VREF_CA_DIMMIO—————<_ — ]+V VREF CA _DIMM1 [17]

1%

= : +1.2V 9 vege ChADRAM |] ChA DRAM xà

tx r0402 tx_r0402_short_12mil

af 1% 4V_VREF_CA_DIMM1 R1811

[4] DIMM_VREF_CA [> ~ LrAnvp?2 DIMM_VREF_CA_R SP1802 1 ml 2_0Ohm

G1803 10T220000087 R1810 0.022UF/16V 8.2KOhm

tx_c0402 †x _r0402

- 1%

R1812 24.90hm =

Trang 13

[53] CL_RST# CL_RST# GPP_A14/SUS_STAT#/ESPI_RESET# PM_SUS_STAT# [62]

[30] RCIN# > GPP_A0/RCIN# GPP_A9/CLKOUT_LPCO/ESPI_CLK AY9 CLK LPCT R2002 1 2 220HM ix 10201 hid [1% — 5 CLK_KBGPCI_PCH

Unmount R2013,R2009 Vendor Suggest Pull High Resistor Need To Close To TPM PM_CLKRUN#, INT_SERIRQ Need To Pull 10Kohm To+3V5S at Chipset Side

CRB 0.53 reserve 150k ohm +8VSUS_ORG BBS - Internal weak pull down 20k ohm

Boot BIOS Strap

To enable Direct Connect Interface (DCI},

a 150K pull up resistor will need to be added to PCHHOT#

pin This pin must be low during the rising edge of RSMRST#

Title : PCH(1)_SPI/LPC PEGATRON PROPRIETARY AND GONFIDENTIAL

BG1-NB4 Size Project Name Engineer: Willy_Liao Rev

Date: Thursday, March 31, 2016 Bheet 20 ot 100

Trang 14

Microsoft* Windows* 7 System WHCK Requirement — OEM platforms are

required to include a supported OS debug interface, accessible by an enduser

This allows developers to help in driver debug The supported

Windows 7 debug interfaces are EHCI, 1394 port and COM port

With skylake EHCI Removal, Potential Gap with Windows* 7 Kernel Debug

and OS Installation — Mitigation Required

a | GPP BI 7IGSPIO_MISO @PP_Dio Pog SS STORE To Co MUX SEL [80

“ Gi ENT] GPP_B19/GSPI1_CS# D 3.3V GPIO

57] VDB_PD_EN_PCH# GPP_B21/GSPIi_MISO GPP_D6/ISH_I2CO_SCL ISH I2C0 SCL [41,70] Internal SensorHub

T GPP CS AB2 | GPP_C8/UART0 RXD GPP_D8/ISH_l2C1_SCL ISH_I2C1_SCL [41] Internal SensorHub debug port

To implement UART for WIN7 WHCK requirement if need 1 EPP-ETD WE] GPP_C9/UARTO_TXD

GPP_C10/UARTO_RTS# GPP_F10/l2C5_SDA/ISH_l2C2_SDA

Please refer to Intel document #548689 - RVPS reserve UART T2144 1 GPP Cit AB3 GPP_C11/UARTO_CTS# GPP F11/l2C5_SCLISH_I2C2_ SCL

R2126 1 2 _0Ohm_tx r0402 0ohm WLAN _ON_PCH ADI C 3.3V GPIO

lo] BT ONOFF/ , = Rete? 2 t0hm ———— GPP C22 APEC | Gp-Cø1/UART2-TXD AD3 | = GPP_D13/ISH_UARTO_RXD/SMLOBDATA/I2C4B_SDA a | N lì

R1.2 [8,45] LCD_BKLTEN_PCH fete >8 —— T212 Q1 ——— AĐ° Í Gpp- Cø3/UART2 CTSỹ s s GPP_D15/ISH_UARTO_RTS# TCH PNL APSE PCH A

PCH 1201 SDA us GPP_Ci4/UART1_RTS#/ISH_UART1_RTS# Papa GPP OE

GPP_A21/ISH_GP3 Pay

Sx_EXIT_HOLDOFF#/GPP_A12/BM_BUSY#/ISH_GP6 T2133 1 PCH I204 SDA AFTT

T2134 Cộ ï PCH I2C4 SCL AFT2 | GPP_F8/2C4 SDA GPP_F9/I2C4_SCL

940432 01T010000015

+3VS

PCH l2C0 §DA B213 1 2_2.2kOHM 1x r0402 PCH I2C0 SCL — B2114 1T 2 —2.2kOHM 1x r0402 +3VSUS_ORG +3V§US ORG +3VSUS ORG +3VSUS ORG +3VSUS_ORG +3VSUS_ORG +3VSUS ORG

PCH l2C4 SDA R2la4 1 2 _4.7KOhm 1x r0402

GSPIO_MOSI / GPP_B18 - Internal weak pull down 20k ohm

=> 0: Disable No Reboot mode(default)

GND GND 1: Enable NO Reboot Enable mode

MB Vers 10n ID Memo ry ID Panel ID Default is GPO, to reserve pull high to +3VSUS_ORG

PCB_ID2 PCB_ID1 PCB_IDO

(GPP_D14) (GPP C14) (GPP C13) Hawaii §C build default)(SKU3)

A2 Build 1 0 1 J

Bl Build 1 1 0 Hawaii (B2 build default) Title : PCH(2)_ISH B2 Build 1 1 1 PEGATRON PROPRIETARY AND CONFIDENTIAL _ _

c2 Build 0 0 1 Size Project Name

Trang 15

SP2201 2_0Ohm tx r0402 short 12mil HDA SYNC R BA22

8 HDA-BCLK SP2202 2_ 0Ohm tx 10402 short tamil HDA BCLK R_AY22_| (IDA _SYNCI2SO_SF AM

1 —_ a emove —| I2S1_TXD GPP_G4/SD_DATA3 =

R1.1 RF Suggest “x ToPRI50V | 2 2UFI6.3V coao2 “| œx co402 1 a 1 AK? `“AK§ | ÔPP_F1//2S2_SERM GPP_G5/SD_cD# we GPP_G6/SD_CLK Frys 18 - 4 120

Close To PCH Side Lk = @ —€ = @ i 0 co -AK9 Í sbp F2/2S2 TXD | GPP_F0/292_SCLK GPP_G7/SD_WP - — uSD WP 1 T2205

GND GNP 0 | AMO GPP F3/282 RxD GPP_A17/SD_PWR_EN#/ISH_GP7 | seq ——————_ | Tools

tke=—===—=—====K===e GPP_A16/SD_1P8_SEL -

+3V8 SPKR - Internal weak pull down

0: Disable TOP Swap mode {default}

R2202 1 ụ ARA 2_20KOh 0EOnm SP R2209_ og 1 ARA 2_4.7KOh Ohm † 1: Enable Top Swap Enable

GND

H2Z210 1 „3 2 4/KOhm Default is GPO, to reserve pull high to +3VSUS_ORG

†x r0402

+VCCPAZIO CRB 0.53 reserve 150k ohm

B2203 1 „@ „2 47KOhm HDA SDO_R

HDA_ SDO - Internal weak pull down

tx r0402 GH751H-40AGP_ 2 1

tx_sod323_h39

D2201 ——] pCH FLASH DESCRIPTOR [30] FLASH DESCRIPTOR SECURITY OVERRRIDE

0: Enable security measure defined in the Flash Descriptor 1: Disable Flash Descriptor Security

Trang 16

818} cies ax BẠN 8 Fagg CS Can nha P0 Dài USB3.0 Type C

[53] PCIE.TXPS.WLAN —| 02310 : TXP9 1 2 || TẢ 01UE/16V x c0d02 PCIE TXP9 WLAN © Ags | POIES_TXN PCIES_TXP USB2N_9 Page USB2P_9 USB_PP9_PD [96] PNG PD [96] USB3.0 Type : C

Te wih [ceste 2 | [ lối ¬

[ö3| PGIE TXP WiGig C2312 2 {1 01UE/16V_ tx 60402 POIE TXP WiGig © C23 PCIE10_TXP USB2_COMP oN ii nà + fot =.=s “sen

USB2_ID ‘GND support Dual Role, then _ :

COO TIE ROOM EB] PCIE_RCOMPN USB2_VBUSSENSE ‘GND - “Too

XEST | PGIE11 TXN/SATA1B_ TXN GPP_E6/DEVSLP2 Ear] PGIE11 TXP/SATA1B_TXP

ae PCIE12_RXN/SATA2_RXN GPP_EO/SATAXPCIEO/SATAGPO Hệ — — ——- aoe | Ề oor be — — 1_O T2 RSE] PCIE(2_RXP/SATA2_RXP GPP_E1/SATAXPCIE1/SATAGP1 FRST——S A < ] SATA_SSD1_PEDET [BI]

<=] PCIEI2_TXP/SATA2_TXP - - GPP_E8/SATALEDy | HỦ_ STA LED£_ R2304 Í „/Ä A 2 10KOhm tx (0402 O:3VS

1 © 12325

940432

Features | Base-U | Premium-U | Premium-Y OCT # O02# 2309 R2310 1 1 2 0Ohm x 10402 Oohm 2 Ohm tx 10402 0ohm USB_OC1# PCH USB_OO2E-PCH [547 [Be USB30 port2

Total Intel® storage Devices RST capable PCIe and SATA Express* | 0 | 2 | 2 OC3# R2322 1 2 0Ohm_ †x r0402 0ohm USB_OC3# PCH [ge] - ia IVPSC

Notes:

1 USB 2.0 port numbers: 1-8 Figure 16-18.USB 3.0 Dual Role and DP x 2

2 USB 2.0 port numb 1

3 USB 2.0 port numbers: 1-

4 SATA Express Capable Ports (x2) +3VS

SKYLAKE

Table 1-3 PCH-LP HSIO Detail —_ =

SKU 1 2 3 4 5 6 7 8 9 10 11 12 13 14 5 16 USB3TX1

3.0/ 3.0/ 3.0 3.0 LAN LAN LAN LAN N US83RXI+

oT SSIC

U 3.0/ 3.0/ 3.0 3.0 USB USB LAN LAN LAN SATA SATA LAN LAN + SATA

oT SSIC 3.0 3.0

Y 3.0/ 3.0/ 3.0 3 USB USB LAN LAN LAN SATA SATA LAN LAN ”

š

— DP ML1+ H Capture from 545659_545659_SKL_PCH_LP_EDS_Rev1_0_pub OP ML1

Please refer the latest Doc

Note: The figure above is a high level example implementation block; actual implementation

Trang 17

GLK REO4 WLANE R_ R24Z9 1 2_ 10kOhm ty t0402

GLK REO4 WLANER_ R2408 1 „ @ „ 2 10KOhm tý r0402

[E5] MCSI_1_DATAD_DN 236 csi2_DNo CSI2 CLNo HESS MCSI_1_BLK_DN [S8] —Ị +VCC RTCQ—<C—] +VCC_RTC [25,26,96]

Rear Camera (5M) [B5] MCSI-1-DATAD-DP CSI2_DF0 CSI8 CLKPD MCSI-1-CLK_DP [55] Rear Camera (5M)

B5] MCSI-1DATA1-DN Dàn | CSI2.DN1 CSI2-CLKN1 [3z +8VAO ——<C—] +3VA [30,88,53,58,57,70,81,93,95]

[B5] MCSI-1 DATA1_DP Da | CSI2-DN2 CSI2_DF1 CSI2 CLKF1 [E55 CSI2-CLKN2 [O +8W§O-—<—]_ +3V8 [34,20,21,22,23,30,32,38,40,41,44,45,50,51,53,55,58,87,82,70,/01,02]

o<BSe{ csi2_pr2 CSI2 CLKP2 [Re CSI2-DNä CSI2-CLKN3 apex +8V§USO——<C——] _+3V§U§ I4,25,28,28,30,51,53,82,08,81,84,92,95]

CSI2-DF3 CSIZCLKPS Fx

cat £13 csi2_ COMP R24181 A J4@A_2 100Qhm_ by r0402 J)

par] C812 ONE COMP a7 GPP D4 1 CƠ 1202 Ht o<BSr{ csi2_DP4 GPP_D4FLASHTRIG

CSI2-DNS +3VA

“Số | CSI2DFs ewe Bsr] CsI2_DNE AP2 XS] CSI2 DF5 GPP_F1¥/EMMC_DATAO AT

dB | CSI2-DN7 GFF~F14/EMMC_DATA1 [A3

~>* | csiz prz GFF~F1S/EMMC_DATA2 LANB

Ai GFF~F1ð'EMMC-DATAä LẠNT + + csi2_DNB GFF~F17IEMMC_DATA4 LẠNZ“

BH csi2-prs GFF~F18IEMMC_DATAS Pana & toe Fete

D28 | CSI2_DN CSI2-DFs GEE_F13/EMMC_DATAB | AMT GPP_F20EMMC_DATA? < tụ r0402_Dohm 1402 Tự r0402 % B7] CSI2-DN10 AM, ¬ ¬ CSIE-DE0 x GPP F2VENMICRCLK PARIS x ` sero sc — | 318-318 een cis sourced inNon-G3 state platform designers must ensure fom Voattng3 o VeCOSW_3p3 the

oP) Gsi2“pP11 GPP.Ƒ18/EMMCOMD | “®< v tHrective voltage ot VCERTC doesnot exceed 320

ATA EMMC RCOMP R24181 , ye, 2 2000hm ty 10402 J, R2424

C24011 || 2 10PE/0V |h, I 1

x c0201 NPO/i5%

R2438 1MOhm X2401

x rane 2aMHz|

0304 m

o 106k sianaLs SP2401

2XTAL 24M QÙT R G24022 || 1 10PE/S0V | lÏ—w s20 —| +VCC_RTC

t {T241 1 sw GI‹OUT PCIE NO ĐP Í cự oUT POIE No đOhm

t Remove SNN { SBEIO Gpp_as/SRCCLKREGOE ae CLKOUT_PCIE_F0 tị r0402_shor_12mll SP2402 R2403 1 2_20KOhm

1 t B42 Fa == = 1

1 t Xã | CLKOUT FCIE_NI CLKOUTITPXOP_N Feast Dolete xDP elle SPEBOY 18ND 0402

~A 7| CLKOUT-PCIE-F1 CLKOUT-ITPXDE-P Delete XDP clk "mm

1 t 2] GPP_B6/SRCCLKREQH# BAI? SUSCLK PCH ~ “| ceans

1 @ 724024 sh cLKOUT PCIE N2 041 | our pore Ne GPD8/SUSCLK J 2 2UFIB.OV

PCIE E37

a >=] GPP_B7/SRCCLKREG2# XTAL24_OUT PSO 27T 1% benh +120ppMUSPE, CLK PCIE.WAlg# Pê wane CuK eLKOUT PCIE N8 XOLK BIASREF XGLK BIASREE R24171 BP dob tr xtal_2p_126%x59

110402 shot _i2mil CLK PCIE WiGig PCH R C40 PCIE = R24227 2-§040m

Clik PCIE WiGig PCH ‘Dat REOS WiGig# R A CLKOUT PCIE P3 AM18 XTAL 32K XI

CLK REOäS WiGigt - GFP_B8/SRCCLKREGS# - RICKY RTCx | AM2D — xTAL 32k xe C24042 || 1 8PE/S0V |} GND CLK_PCIE_WLANS_PCH > — TH ECE a oH Bat CLOUT FCIE_N4 “sư am Ự CLK_PEIE-WLAN ECH sig] CLKOUT_PCIE_P4 SRTCRST# LẠNIE—Ơïc Bi R2404 1 2 20KOh CLK REOZ WLANE —m——— —————¬ GFP_B8/SRCCLKREGM# RICRSTE +

tr 0402 NĨNN

B2428 1 SCLK PCH R 2435 1 2 00hm — SUSCLK PCH

10402 - 'x_10402-VONNh

RB435 1KOhm

tr 10402 B2438 1

Trang 18

SUSWARN#/SUSPWRDNACK unction / non-A

R9229 10KOhm tx_10402

†x_r0402

tx_r0402_0chm

internal pull high PME# R2527 1 @ ~_2_10KOhm }

RSMRST# SLP SUS# 72510 If Deep Sx is not implemented on the platform, this signal may be left as no connect

tx00201 gy +VDDQ/+VCCST_CPU/+VCCSTG to VCCST_PWRGD must > 1ms

Ss" vec

DELAY_ALL_SYSTEM_PWRGD R2529 1 2 0Ohm tx 10402 0ohm H_VCCST_PWRGD_L ERR =

EC delay ALL_SYSTEM_PWRGD 2ms ALL SYSTEM PWRGD R2530_1 2 0Ohm 1x r0402 0ohm ƒ 3 leno yy 4 H_VCCST_PWRGD_R R2524 1 Wp p~_2_60.40hm H_VCCST_PWRGD_MCP

Cc - |

= _ tx_10402 SN74AUP1G07DCGKR tự

Trang 19

VCCMPHY_ 1p0 Icc Adder Per HSIO Lane near AG15

1x 00402 @

Ice (A) Details SATA Gen3 Port X 10

PCle Gen2 Lane X 1 q 628131 |[ 2 1U210V |:

0.064 All HSIO disabled USB3 PortX2 near Y16

° * 0.154 Each PCIe Gen3 Lane AIL HSIO disabled (basic comsunption} tx_c0402 @ D

=0.154x110.132x110.132x4+0.064 = 1.01A B2801 1 2 _0Qhm bx ¡0402 0ohm 0.102 | Each PCle Gen2 Lane

0.132 | Each USB3 Port G2801

— — CPU POWER 4 OF 4 +VCCPGPP, 0.004A 0.006A

|

Decoupling cap for internal power W2n| VGCPRIM_CORE_2 VGCPGFFE | AET % 10402 Oohm 43VSUS_ORG

2 _0Qhm_ix_10402_dohm tx‹ 60201 10đ08 hi4 LTB | VCCAMPHYPLL_1P0_1 DCPRTC near BB1B58/+/-10% 1X 00201 G2818 1 2_1UF/10V |iano near AK19

@ near K15 0 026A X5 Í VSGAPLL 1P0

3VSUS_ORG “ =

+ ° x near V15 = E2606 1 A A A2 0Ohm tx 10402 dol 0 118A ADIT VOCDSW 3p 1 VocoL«a LNED _ an33^

1 2 +WGCPAZIO T7 | VCCDSW_3p3_2 L19

†x_r0402 1

nm PEGATRON Title pcx7_power

PEGATRON PROPRIETARY AND GONFIDENTIAL

Trang 20

N

N ` X

[20] SPI_WP# IO2 [20] SPI SO [20] SPI GS#0 [30] F_CS#_EC [30] F_SDIO_EC

@ WW36MOW (for ES Sample) SPIO_IO# Should be 1K

G2801 0.1UF/18V

DI(IO0) _SDI_EG [30]

| SPI

WW48MOW(ES

In Skylake Platform Design Guides (PDG) under “Platform Debug & Test Hooks”

chapter, HOOK[3] pin from XDP/CMC header needs to be routed to PCH SPIO_MOSI pin The termination resistor can be a value from 1K to 3K ohm pull up to Always rail (not Core rail) with voltage value from 0.8V to 3.3V This will ensure PCH hardware straps are not overridden unintentionally and cause boot issues

FSPI œ0 A_A 8528

7VN

U2801 A_A 8587

Trang 21

WLAN WAKE#

tx r0402_0ohm U3001

R302_ 1 2 00hm VBAT_PIN3 J4 VBAT ADCO/GPIO aie AD IINP [88]

tx r0402_0ohm 43VAPLL E4 Kế] VSTBY(PLL) ADGI/GEI | G12 ADG2/GPI2 [Eg AL SYSTEM J PwRED [25,92] 25,92)

r0] VSTBY2 ADC6/0SR18/GPl8 [E13— XE De WLAN_WAKE# [53]

+3VA EC VSTBY1 ADG7/GTS1#/GPI7 AC DET# [89]

M5 BWMO/GP AO NS CHG BLUE LED# Tb pers BST) Ta0Te {> PWALBLUE_LED [s6]

oo

+3VAOC AVOG BW M2IGPA2 Ne PWR ORG_LEDE TH peLGS TL) THOS {> CHG_ORG_LED [56]

IT8528, IT8587 connect to +3VS ñ3023 1 2 00hm EC VGC J5 | vào PWM4/GPAZ Loe — — — — EC SH J2C SCL [70]

PWMB/SSCK/GPAG ["K7_PD_VBUS_OFF_ECH PDLVBUS_OFF_EG# [96]

TH ES BT_ON/OFF# EC Ha038 1 2_0Ohm_t 10402 Oohm BT_ONOFF# [21,53]

cOhm 002 hat anda k 81N6/p4BEarul /OKS2KOUTILPCRSTW/GPB7 Ê— TT SMESH: 3 PM RSMRSTf [25]

B28 tà TH HH base

JE04482] LPC-AD2 NOE Sha Ta LAD2 LAD1/QPMI K13

D2282] LPC ADa Ohm tx 10402_short_temil _ LADS HZ-| LAD2GPM2 KSO16/SMOSIGPC3 [ŒZ — AC IN OC EC SP3008 1 2_ 0Ohrh‹ (0402 shorL 12ml AONOC ,——]AcNOC B8]

[20] GUK KBCPOL PCH 2 0Ohm Ix ¡0402 shot 12ml CLK KBOPCLEC K2 | LÀD3/GPM3 JMRI/GP€4 [ JTØ a

ES2269621 TT ST BUF ———— ———— Pl 0 PWUREQ#BBO/SMCLK2ALTIGPG7 Me AC PRESENT [29

7 SERIRO/GPM6 Dom Ex10202 shơi-TmI——EXT-SMZ.EC

Bán san: AM roo shor tamil EXT SCHEEC FT] ECSCHHIGPDS 4| EGSMI#/GPD4 RI1#/GPD0 NI PM SUSBE 3067 _1_/SEQS EB Ohm tx 10402 Oohm Pu susce (25,68) SYS PWROK 588

TAGHIA/TMA1/GPD7 yeus 2 N li, aan sã

KSIS Z | KSIENIẺ AE LAI DELAY ALL SYST nwRep [25]

Bottom ST Kae EGGLKGBEA AS CPU VRON

T3019 KSlB PWRSW/GPE4 LN8—TIM-SET 2 oOhm COO Ooh Ne ae << DEAL SvS PGD HW [68]

T3020 KSI6 RTS1#/GPEB LID 9W# MRP nb Ipc2t 58 ï T3018 _ IS]

KSOoepo (801L A/GPE7 ——¬ mm¬ m——— LID_SW# MR_P [46,70]

KSO11/ERR# GTX1/SOUTI/GPH2/SMDATS/ID2 LARS — HOME KEY# EC 1 F308

— 3] H_PECLEC T-| SMDAT1/GPG2 T-| SMGLK2/PECIGPF6

lãi Bên: ng Fig008 1 2 00m Ix r0402 0ohm MDAT2/PEGIROT#/GPF 43VA

[81] USB CPW EN 3082, 0Chm _ tx r0402 0onm EC oe DAC3/TACHIB/GP.J3 Fgpes

ler Bi VÀ RA VOL_DOWNE 30301 2_0Onm 10402 _oohm VOL_DOWN# EG Di3 ĐÀ TACH0BIGPJ2 tx_10402_Oohm

fer'sel VOLLUP# VOL_UP# B051 ðOhm- bc r0402-0ohm VOLUPE EC E12 | OMT ceo

«

F2 EB Ion sore +3VA I2C MUX

[AI SWV RTCRST OT 2 ñÔNm Ix70202.06m 1| CK32K/GPJ6 vSsI F§—† ||ISMP_¡ eno ‘

Này Ls tx_c0201 O.1UF/6.3V

E5] F SDLEC † E SDIEC BS ry cều ae VSS6 3095 = [28] FSDIO_EC | —°?2==—°Ì riscyepos AVSS [10 he IEC._ ASND rô ( gah usooe

10PF/S0V 067380000084 (2m) eco MUx.seL [> vn 2 5 Soc att 2 Ì: <] PcHiaco scl [21,70] ( )

l2co_ MUX SEL CMe ST = — gi|Í_— 2 PCH C0 S2A <_] PCH_2Co_SDA [21,70] ( soc }

tx r0608 0ohnY D2 +3VA_EC +3VA_EC +8VAPLL

EC_AGND

c

For PU / PD

+3VA_EC 3VA EC

S088 1 2 8lKOhm tx ¡0402 — SMB1 DẠT COR TOY USBPD_DETH 10K Ohm 10402

[Foes TS NF TBROM tC 10402 — SMBI CIK ORM be — SHE CT coe ~—“ytitr Power detect OD source” -

3VA EC

9 BN3001A 1 2 4.7KOHM_ tx 2400402 h20 SMB0 CLK ‘|

SUSC_EC#

30161 2 10KOhm tx 10402 VOL UP#

ñ3082 1 2 10KOhm txr0402 — HOME KEY#

PEGATRI ON TIe : EC IT8587EFX

PEGATRON PROPRIETARY AND CONFIDENT!

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PEGATRON Title : RST_Reset Circuit

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Audio Codec

Digital ' eD4DE 102 h8 | Close to J3602 Close to J3602

3A

= [L c3e28 = C3630 1Z17-11NV000

L1 T] ai + A 15DDPF/SDV (| | _ 15DDPF/50V

si c eobsrp Hess Sue dy 60402

Z4 50mA SEMI 55 0b aaa AT 51UEHeV QỊ tensnỆ t02_t0e

118W isco Ế gỗ, Ÿ 1z0Onnyronhl lz = Š kbhEsc Sẽ Seer 3 v4 0402 vv ALCasSCGT

Fos Sung 9 EEDE ee Place close to Bin 36 RaB37 Digital teToloooon7a Tư 07T1800n0028 tưnnmn 07T180000028

txesd_2p_34_36x24_inpaq tạ Esd 2p_ 34, 36x24_npaq Add this Filter to avoid other ar = fof usene sett J3801

components/chips be inflyenced L; ˆ Analo

+3 Components/chip / Lsep2 kể 2 ures Tung th Ềnn rên FỆ— are) LỆ — UNE 5 wisp pw 2 tan 4 SHŒk BS 2 tow spice segs 1 200mm Hs spr 8

i — DMhz KrWErizrEEir Ï xrl ——— — LNETAMORTCR) TER) TINET PCB trace width of SLEEVE & RING? are required at least 40 HH SPKB- Rsozg 1 '_r0ED3_Dohm_hZ4 ZnOhm H SPKR- R - 2

~ ~ FL SPRL SPOUT-Ls le DAE Case TEE ya ee il and it TVHFEDEDIADD, TẤHFEDEDTACD

‹| ng L sco oe Ea ¬iNg MIC2-RIPORT.EẨn9LEEUC 1Ï | it 07T180000028 07T180000028 9x r0ED3, Dohm,h24 WTOB_CON_2P

C3622 '1DUF/B.3V = 3 102_t [ ø1UEiav + SPKEL SPK-OUT-R MIC2-L(POR BAF -LYRING ‘esc Zp_34_ 38x24 Inpaq tị_psd_Zp_34_ 30x24_jnpad, verirepsnoes

DE —if-| SPDIF-OUTiGPIo2 Po SPOOR MIGATLINGE vbUDE) HPILINN —JD(ID1) PP ——ESErs.s 1 - Pa at mì TH % ———— 1spBEElsuV ¬Ï ad TRghneany 1217-81N9000

mi - - | sụp < R3BD4 10DKOhm tx (0402 1% 43V8_AUDIO txcoan2 “I SỈ tx coanz

=> 20 Es ~ Trace width for SPK-Ls/SPK-L-/SPK-Rt (SPK-R-

1DUEIE 3 Csens a3 Place close audio codec Speaker 5 QO mil Imex 0.898, Tevg: 0.707

‘x_cf6n3_¢02_h99 0 1UE/IBV 20201 oak Sš.8 az,

+3V8_AUDIO ALC255-CGT RPP PEP s

— dus tau ace | ER oe

¬ I pc Beep cso + || 2 nweiey — „ PcsEE> 360s 1 2 22k0hm -—] H0APKR p3 Rabsz cseos Ff lo} H Em

D402 te coaoe : tŨ2_h28 A ad I “e*70%02_Dohm u PI) cops R3B18

SEIS TOORFISOY & 4 7KOhm

[21] GP_SD# sld Bls|El ————1 oa saAc [22]

(21) oP HDA BSTz 2 - Place close topind SEl aay 314 RR (22) CY b cnana e ‘tx D402

check platorm level,

BATS4AW bã "¬.= 7 DMiC interface HoA_sDIn [22] na

° 10KOhm | 1UE/B.3V gout 2 Ohm tx 0402 ooh D3804 2 4 0402| bị c0402

See im v Supported iPhone/Nokia headset, Headphone,

— a <—] HA sbo al 5| a ex] 790803 t02_hse Line-In and Microphone through SW popup menu

2015.04.08 YenP enPin, gcAttention>> For power_on/off Note : 3675 4 22 2kOHM tx AI! (D402

BỊ Ä&BÑhoaio moat SRWLvS

43V8_AUDIO 43V8_AUDIO_DMIC sae ae +1 ifyou want the system make warning signal cher per on, viene let EC! MUTE High ——

7 7 7 +2 lÝ tr desi I, for example No CPU or Mem« installation or Bad BIOS,

tị r0402_Dohrt Us602 SLEEVE > iz RING? CON

bị PP T3605 7_ > 12DOHNI/1DDNIELZ Ẵ JU4D2 h2: FR T CON

mg trr0En3_Dohm_h24| TINE? VEEEO F609 -4.7KOHm

+5VS 9 Digital Analog +8V§_ALDIO g R38241 nOhm ‘ik :ũeÙ8-nøhr-T2Ả| 2 R3833 1IDKOHNL 10DKOHM 3631 q[ Nmnzac ee TTL

D402 <ˆ bị r040Z2 th aol23_2d3_ h44 R38231 ngụy 2 je je mà TÍk-]a 1515 ˆ<*|¬

Mave not haa +3 AUDIO ele 8 ale 13 Ss 313 aaa sels cass RS6224 pohm 2 SLEEVE

: + “vo sơn Close to J3603

In order to prevent the built-in LDO damaged from GND GND_ALDI al lọ 0402 ea) th aol23_2d3_ NX7OD2AK h44 Us603

over-voltage on +5VSYS or Standby power line, we =>

suggested using this Voltage suppressing device

ca Nkron2aK t_sol2s_2d4_hia Cao3 20A TWFEnanrACD TWFEnanrACD

Tơ solve the background noise while combojack connecting to an active speaker 07T18nnnnn2s 07T18nnnnn2s

d system entry into $3/S4/55 without analog power SDky_1.05°0,68°0.55_Vrwm oy 1 Vhm Sv_SSpF_Vel ey Sv_s5pF_Vel 6 hạ ssd_2p,_ 34_38424_Inpaq esd op 34, 30x24

Bley 1.05°0.65°0.95_Viwm 5v, 35

3604 U36 ¬ er

HP CON ve_2 ov HP L CON ve_2 tuo HDA BCLK TWPEnmAen TWPEnmAen HDA BSTz 07T180000028 07T180000028

- tạ Esd 2p_34, 36x24, npi t_Esd 2p_34,.36x24_npaq : SN 160020 5, VramS, SEpP,VelB+ 0 E60 55_ tim 5v, 35p a) we risoy | ‘orveay

tx_c2m «00201 HỆ ,ID# C3pg51 || 2 q0DPE/SpV HP JDg — VC 2 tow Reserve for Noise te coane

Close To Audio Codd TVHFBDEDTADD 07T180000028

t_Esd 2p_34,.36x24_npaq 30ler_1.0800.850.56, Vwwm 5 35p|

EZ DMIC_CLkp PCH [>> DMIC_CLKD_PCLL 3857 1 gQ 2 0Ohm_tx 10402 Dohm DMIC CLK D 3661 1 2_0Ohm tx r0402 Dohm DMIC R CLK

DMIC DATD_PCH, 3858 1 gQ 2 0Ohm_tx 10402 Bohm DMIC DAI D 3662 1 2 0Ohm tx rD402 Dohm DMIC R DẠT

nes 1.08°0.65°0.55_Vrwm Sv_s5pF_4HI sự 3853 1 2 4a 7kOhm 38541 @ „ 2 47KOhm,

tị psd vn 34_3824_inpaq 5D, 65°D

ay 55_Vnum 5v_s5pF_ bì By

KNINHDSDTDZD-TEDS 04TASDDDDDET

Trang 24

RN4000B tx_2r4p1234_choke_4p_colay

GND”

——C4013 0.1UF/16V tx_c0402

Close to connector CON4001 Pin4

Mã an xoa R4000 SD CIK RS | ore

Trang 25

+3VS_ISH_debug

ISH_12C1_SCL ISH_l2C1_SDA

R4102 1KOhm

ISH debug port

Trang 26

DEBUG CARD CONN

PEGATRON Title : pesucconn

PEGATRON PROPRIETARY AND CONFIDENTIAL BG1-NB4 Engineer: Willy_Liao

B HAWAII 0.0

Date: Thursday, March 31, 2016 Sheet 44 of 100

Trang 27

+LCD_VCG 2 | SIDE2 SIDEI [ï „‡:LGD_VGG L4504 (SN PDgS20An4-17W ° ==c4544 w

a | 1 20 | 38 19 2 EDP_TXP1_C 2.2kOHM 100KOHM „| 1UF/16V LCD BAOK PWM TBD ‡

1 28 | 24 2225 EDP_TXP2 C

Discharge Cireuit _| _ ld=100mA/Pd=150mW EDP TXN3 G G4538 1 2 _OAUFA6V_tx c0402 EDP TXN3 [3]

Rated current: 0.3 A => ¬

Contact resistance: Max 90m Ohm EDP_TXN2 GC C4528 1 2 0.1UF/16V tx c0402 EDP_TXN2 [3]

EDP_TXP2 C C4527 1 2 0.1UF/16V tx c0402 =—] EDP_TXP2 [3]

EDP_TXN1_C C4523 1 2 0.1UF/16V tx c0402 EDP IXP1 C C4524 1 2 0.1UF/16V tx c0402 =—] EDP Tx a EDP_TXNO C C4521 1 2 0.1UF/16V tx c0402

Ned 2 01UE/I8V— b-c0402< EDP_TXNO [3]

D4503 1 2_GH751H-40AGP LOD BKLTEN PCH [3,21 - C4546 tx‹ r0402_0ohm

› tx_sod423_h39 <_] te CH 321] U4502 0.1UF/16V @

+LCD VCC 1 2 4LCD VCC R 1 + NES a| 22PF/25V ,| 22PF/25V Qv| 100PF/50V ¿| 100PFS0V ~~ 100KOHM_ 1MOhm R4529 1 m2 @

Oty ou tx_00402 tx_00402 tx_00402 tx_00402 _| 10402 tx_r0402 ane achm

+3V$O——< — ]+3VS |3,4,20,21,22,23,24,30,32,36,40,41,44,50,51,53,55,56,57,62,70,91,92]

Size Project Name Rev

A3 HAWAII 0.0

Thur March 31, 2016 Sheet 45 — oí 100

Tiêu đề	Acer Aspire Switch Alpha 12 SA5 271 Pegatron P2JCC (Hawaii) Rev 0 0 Schematic
Trường học	Pegatron
Thể loại	Sơ đồ
Năm xuất bản	2016
Thành phố	Taipei

Định dạng
Số trang	55
Dung lượng	3,36 MB