Acer aspire one AOP531H d520 (compal LA 5141p) schematics diagram

NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.. NEITHER THIS SHEET NOR THE IN

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Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC

SCHEMATIC,MB A5141 B

Tuesday, March 10, 2009

Compal Electronics, Inc.

Title

Intel Diamondville Processor with Calistoga(945GSE) + DDRII + ICH7M

KAV60 Schematics Document

REV: 1.0

Compal Confidential

2009-03-06

ZZZ

LS-5143P REV1 CARDREADER/B

DA60000BT10 DA2@

ZZZ

LS-5143P REV1 CARDREADER/B

DA60000BT10 DA2@

ZZZ

KAV60 LA-5141P LS-5141P/5142P/5143P

DAZ08400100

DAZ@

ZZZ

KAV60 LA-5141P LS-5141P/5142P/5143P

DAZ08400100

DAZ@

ZZZ

LS-5142P REV1 SDIO/B

DA60000BU10 DA2@

ZZZ

LS-5142P REV1 SDIO/B

DA60000BU10 DA2@

ZZZ

LS-5141P REV1 PWR/B

DA20000FM10 DA2@

ZZZ

LS-5141P REV1 PWR/B

DA20000FM10 DA2@

ZZZ

LA-5141P REV1 M/B

DA60000BO10 DA2@

ZZZ

LA-5141P REV1 M/B

DA60000BO10 DA2@

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Title

Compal Confidential

Model Name : KAV60

X2 mode

File Name : LA-5141P

Touch Pad

CRT Conn

LPC BUS

page 20

27x27mm

page 24 page 14

page 21

Int.KBD

page 25

400/533MHz

ALC272

DMI

Diamondville SC

FSB

Transfermer

Power ON/OFF

& LED CONN

page 25

page 13

FCBGA8

DDRII-SO-DIMM

Calistoga GSE FCBGA998

SPI ROM

page 4

1.8V DDRII 400/533

page 4,5

page 27

Aralia Codec

Memory BUS(DDRII)

31x31mm

page 6,7,8,9,10

ICH7M BGA652

Thermal Sensor

page 11

page 15,16,17,18

page 27

ENE KBC KB926

AMP & INT Speaker

10/100 Ethernet AR8114A

page 24

PCI-Express

EMC1402

LCD Conn.

page 27

page 19

LVDS

page 28

USB Port X1

SPI

INT DMIC CONN HeadPhone &

MIC Jack

RGB

page 22

I/O Board X2

page 22

to I/O board CONN

page 24

RJ45 DC/DC Interface

3VALW/5VALW

1.8V/VCCP

1.5VS/0.9VS/

2.5VS

CPU_CORE

Clock Generator CK505 page 12

page 21 page 13 page 26

page 29

page 37

page 33

page 35 page 36

USB

BlueToothX1 CMOS CAM

page19 page13

HDA

page 31

page 32

page 34

CHARGER

DC IN

BATT IN

437Pins 22x22mm

page 22

to I/OBoard CONN

SATA

WLANX1

page19

WWANX1

page19

RTS5159E

P/N : DA60000BO00

JP7

SATA CONN USB Port X2 USB Card Reader x1 RTS5159E I/O board

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Title

ON SLP_S3#

S5 (Soft OFF)

S4 (Suspend to Disk)

S3 (Suspend to RAM)

LOW

ON ON ON ON

HIGH

OFF OFF OFF

OFF OFF

SLP_S4#

OFF

ON ON

LOW LOW

LOW

OFF OFF

SLP_S5#

HIGH HIGH HIGH HIGH

HIGH HIGH HIGH

LOW LOW LOW

+VALW

HIGH

+V +VS Clock

S1(Power On Suspend)

Full ON

STATE

OFF OFF

ON

OFF OFF ON

ON

+CPU_CORE

1.5V switched power rail

OFF Voltage Rails

+2.5VS

+1.5VS

0.9V switched power rail for DDR terminator +0.9VS

OFF OFF ON Adapter power supply (19V)

1.8V power rail for DDR

B+

VIN

S5

+1.8V

S3 S1

VCCP switched power rail Core voltage for CPU

AC or battery power rail for power circuit.

OFF ON OFF ON

Description Power Plane

N/A N/A N/A

OFF

SIGNAL

Address

1001 100X b

0001 011X b

EEPROM(24C16/02)

1010 000Xb

DDR DIMMA

IDSEL #

1101 001Xb ICH7M SM Bus address

Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.

Address

Clock Generator (SLG8SP556VTR)

Device

PIRQ

EMC1402

1010 000X b

External PCI Devices

Device

EC SM Bus1 address

Smart Battery

Device

EC SM Bus2 address

No PCI Device +VCCP

ON OFF OFF

+5VS

3.3V always on power rail

5V always on power rail 3.3V switched power rail

+3VALW

+3VS

+5VALW

5V switched power rail

ON ON ON ON

OFF ON

ON

OFF ON

2.5V switched power rail

ID

0 8.2K 18K R01 (EVT)

NC R03 (PVT)

0V 0.25V 0.50V 3.3V R02 (DVT)

R10A (MP)

Rb Vab

BRD ID

0

1

2

3

BOARD ID Table(Page 25)

Ra NC 100K 100K 100K

Trang 4

H_DBSY#

H_ADSTB#0

H_ADS#

H_A20M#

H_THERMDA

H_REQ#4 H_REQ#2

H_DEFER#

H_THERMTRIP#

H_LOCK#

CLK_CPU_BCLK

H_HITM#

H_DRDY#

H_REQ#0

H_BPRI#

H_BR0#

H_TRDY#

H_ADSTB#1

H_THERMDC

H_REQ#1

H_HIT#

H_RESET#

H_REQ#3

H_FERR#

H_BNR#

H_A#7

H_A#18 H_A#10

H_A#28

H_A#12

H_A#26 H_A#29

H_A#9

H_A#13

H_A#23

H_A#27 H_A#22

H_A#4

H_A#19 H_A#15

H_A#21 H_A#17 H_A#11

H_A#24

H_A#8

H_A#14

H_A#3 H_A#5

H_A#20 H_A#16

H_A#31 H_A#6

H_A#30

H_A#32 H_A#34

H_AP1 H_AP0

H_A20M#

H_IGNNE#

H_IERR#

H_INIT#_R

H_RS#1

ITP_TMS ITP_TDI

ITP_TCK ITP_TRST#

H_PROCHOT#_R ITP_TRST#

ITP_TDO ITP_TDI ITP_TCK PREQ#

ITP_TMS

H_D#57

H_D#36

H_D#11

CPU_BSEL2

H_D#3

H_D#12

H_D#39 H_D#32

CPU_BSEL0

H_DINV#3 H_D#59

H_D#40

H_D#23 H_D#18 H_D#16 H_DINV#0

H_D#52 H_D#48 H_D#43

H_D#25

H_DSTBP#2 H_DINV#2

H_D#55

H_D#46 H_D#42

H_D#14

H_PWRGOOD H_D#62

H_D#44

H_D#26

H_D#50 H_D#33

H_D#31

H_D#24 H_D#20

COMP1

H_D#7

H_D#37 H_D#34

H_D#21 H_D#1

COMP0

CPU_BSEL1

H_DSTBN#2

H_D#27 H_D#2

COMP3

H_CPUSLP#

H_D#63

H_D#6

H_D#51

H_D#29 H_D#22 H_D#17

H_D#15 H_DSTBP#0

H_DPSLP#

H_D#61 H_D#58 H_D#56

H_D#41 H_D#38

H_D#30

COMP2

H_DPRSTP#

H_D#8

H_D#54

H_DSTBP#1

H_D#47 H_D#10

H_D#0

H_D#53

H_D#5

H_D#45 H_DSTBN#0

H_D#9

H_D#28 H_D#19

H_DSTBP#3 H_D#13

H_DINV#1

H_DP#0

H_DP#1

ACLKPH DCLKPH

H_DP#2

H_DP#3

H_DPWR#

H_THERMDA H_THERMDC

EC_SMB_CK2 EC_SMB_DA2 ITP_TDO

H_SMI#

H_INTR H_STPCLK#

H_NMI

PREQ#

H_PROCHOT#

H_A#[3 16]

(6)

H_DINV#0 (6)

CPU_BSEL0 (12) CPU_BSEL1 (12) CPU_BSEL2 (12)

H_RESET# (6)

H_THERMTRIP# (6,16)

H_BR0# (6)

H_HITM# (6)

H_DEFER# (6) H_BPRI# (6)

H_A20M#

(16)

H_REQ#[0 4]

(6)

H_HIT# (6)

H_ADSTB#1

(6)

H_ADS# (6)

H_TRDY# (6)

H_FERR#

(16)

H_BNR# (6)

H_DBSY# (6)

CLK_CPU_BCLK (12) H_LOCK# (6)

CLK_CPU_BCLK# (12)

H_ADSTB#0

(6)

H_IGNNE#

(16)

H_DRDY#(6)

H_A#[17 31]

(6)

H_INIT# (16)

H_RS#[0 2] (6)

H_PROCHOT# (37)

H_DPSLP# (16) H_DINV#3 (6)

H_CPUSLP# (6)

H_DINV#1 (6)

H_DPRSTP# (16,37) H_DINV#2 (6)

H_PWRGOOD (16)

H_D#[48 63] (6) H_D#[32 47] (6)

H_D#[16 31]

(6)

H_D#[0 15]

(6)

H_DSTBP#0 (6) H_DSTBN#0 (6)

H_DSTBP#1 (6) H_DSTBN#1 (6)

H_DSTBN#2 (6) H_DSTBP#2 (6)

H_DSTBN#3 (6) H_DSTBP#3 (6)

H_DPWR# (6)

EC_SMB_CK2 (25) EC_SMB_DA2 (25)

H_SMI#

(16)

H_STPCLK#

(16)

H_INTR

(16)

H_NMI

(16)

+CPU_GTLREF

+VCCP

+CPU_GTLREF +VCCP

+VCCP

+CPU_CMREF

+VCCP

+CPU_EXTBGREF

+3VS

Title

SCHEMATIC,MB A5141 Custom

Title

H_THERMDA, H_THERMDC routing together.

Trace width / Spacing = 10 / 10 mil

Close to CPU pin within 500mils.

Zo=55ohm

This shall place near CPU

Zo=55ohm

Layout note:

COMP0,2 connect with Zo=27.4ohm +/-15%, make trace length shorter than 0.5"

COMP1,3 connect with Zo=55ohm +/-15%, make trace length shorter than0.5"

Address:100_1100 CPU THERMAL SENSOR

Close to CPU

Modify schematic by 10/21 change BOM structure 11/14

R234 1K_0402_1%

R206 @56_0402_5%

R2061 2@56_0402_5%

R49 2K_0402_1%

R2051 2 68_0402_5%

R29 1 2 1K_0402_5%

R2001 2 56_0402_5%

C351 2200P_0402_50V7K C351

2200P_0402_50V7K

C352

4Z 1

2

@

R209 54.9_0402_1%

R209 1 54.9_0402_1%

2 T13 PAD

U5A

AU80586GE025512_FCBGA437

N270@

U5A

AU80586GE025512_FCBGA437

N270@

A[10]#

M19 A[11]#

H21 A[12]#

L20 A[13]#

M20 A[14]#

K19 A[15]#

J20 A[16]#

L21

A[17]#

C19 A[18]#

F19 A[19]#

E21 A[20]#

A16 A[21]#

D19 A[22]#

C14 A[23]#

C18 A[24]#

C20 A[25]#

E20 A[26]#

D20 A[27]#

B18 A[28]#

C15 A[29]#

B16

A[3]#

P21

A[30]#

B17 A[31]#

C16

RSVD1 A3 RSVD2 C1 RSVD3 C21

A[4]#

H20 A[5]#

N20 A[6]#

R20 A[7]#

J19 A[8]#

N19 A[9]#

G20

A20M#

U18

ADS# V19

ADSTB[0]#

K20

ADSTB[1]#

B19

BCLK[0] V11 BCLK[1] V12

BNR# Y19

BPM[0]# K17 BPM[1]# J18 BPM[2]# H15 BPM[3]# J15

BPRI# U21

BR0# T20

BR1# V15

DBSY# Y18 DEFER# T21 DRDY# T19

FERR#

T16

HIT# AA17 HITM# V20 IERR# F16

IGNNE#

J4

INIT# V16

LINT0 T15 LINT1 R15

LOCK# W20

PRDY# K18 PREQ# J16

PROCHOT# G17

REQ[0]#

N21 REQ[1]#

J21 REQ[2]#

G19 REQ[3]#

P20 REQ[4]#

R19

RESET# D15 RS[0]# W18 RS[1]# Y17 RS[2]# U20

SMI#

U17 STPCLK#

R16

TCK M17 TDI N16 TDO M16

THERMTRIP# H17

THRMDA E4 THRMDC E5 TMS L17 TRDY# W19

TRST# K16

NC5 K5 NC4 K4 NC3 H6 NC2 G6 NC1 D6

NC6 M15

A[32]#

A17 A[33]#

B14 A[34]#

B15 A[35]#

A14

NC7 L16

AP0 D17

AP1 M18

T5 PAD T5 PAD

U17

EMC1402-1-ACZL-TR_MSOP8 U17

EMC1402-1-ACZL-TR_MSOP8

DN 3 DP 2 VDD 1

ALERT# 6 SMCLK 8

THERM#

SMDATA 7

R1981 2 56_0402_5%

R57 27.4_0402_1%

R47 1K_0402_1%

R2181 2 56_0402_5%

T7 PAD T7 PAD

T15 PAD T15 PAD

R48 2K_0402_1%

R239 @ 1K_0402_5%

R2391 @ 21K_0402_5%

R31 1 2 1K_0402_5%

T10 PAD

R51 1K_0402_1%

U5

CPU N280 N280@

U5

CPU N280 N280@

R34 1 2 1K_0402_5%

C342 1U_0402_6.3V4Z C342 1U_0402_6.3V4Z

1

2

C65 0.1U_0402_16V4Z C65 0.1U_0402_16V4Z

1

2

R202 22_0402_5%

R2021 222_0402_5%

R304 10K_0402_5%

R304 10K_0402_5%1 2

R1991 2 56_0402_5%

R2131 2 56_0402_5%

R30 1 2 1K_0402_5%

R238 2K_0402_1%

R208 27.4_0402_1%

R208 1 27.4_0402_1%

2

R201 56_0402_5%

MISC

U5B

AU80586GE025512_FCBGA437 N270@

MISC

U5B

AU80586GE025512_FCBGA437 N270@

COMP[0] T1 COMP[1] T2 COMP[2] F20 COMP[3] F21

D[0]#

Y11 D[1]#

W10

D[10]#

W15 D[11]#

AA13 D[12]#

Y16 D[13]#

W13 D[14]#

AA9 D[15]#

W9

D[16]#

AA5 D[17]#

Y8 D[18]#

W3 D[19]#

U1

D[2]#

Y12

D[20]#

W7 D[21]#

W6 D[22]#

Y7 D[23]#

AA6 D[24]#

Y3 D[25]#

W2 D[26]#

V3 D[27]#

U2 D[28]#

T3 D[29]#

AA8

D[3]#

AA14

D[30]#

V2 D[31]#

W4

D[32]# R3 D[33]# R2 D[34]# P1 D[35]# N1 D[36]# M2 D[37]# P2 D[38]# J3 D[39]# N3 D[4]#

AA11

D[40]# G3 D[41]# H2 D[42]# N2 D[43]# L2 D[44]# M3 D[45]# J2 D[46]# H1 D[47]# J1

D[48]# C2 D[49]# G2

D[5]#

W12

D[50]# F1 D[51]# D3 D[52]# B4 D[53]# E1 D[54]# A5 D[55]# C3 D[56]# A6 D[57]# F2 D[58]# C6 D[59]# B6

D[6]#

AA16

D[60]# B3 D[61]# C4 D[62]# C7 D[63]# D2

D[7]#

Y10 D[8]#

Y9 D[9]#

Y13

DINV[0]#

W16

DINV[1]#

Y6

DINV[2]# L1

DINV[3]# C5

DPRSTP# R18 DPSLP# R17 DPWR# U4

DSTBN[0]#

Y14

DSTBN[1]#

Y4

DSTBN[2]# K2

DSTBN[3]# E2

DSTBP[0]#

Y15

DSTBP[1]#

Y5

DSTBP[2]# K3

DSTBP[3]# F3

GTLREF A7

PWRGOOD V17 SLP# N18 BSEL[0]

J6 BSEL[1]

H5 BSEL[2]

G5

ACLKPH U5 BINIT#

T17 DCLKPH V5

DP#0 V9

DP#1 R4

DP#2 M4

DP#3 D4

EDM R6

CORE_DET A13 CMREF[1] B7

EXTBGREF M6 FORCEPR#

N15 HFPLL N6 MCERR#

P17 RSP#

T6

R27 330_0402_5%

R58 54.9_0402_1%

C62 0.1U_0402_16V4Z C62 0.1U_0402_16V4Z

1

2

T12 PAD T12 PAD

R331 2 1K_0402_5%

R240 @ 1K_0402_5%

R2401 @ 21K_0402_5%

@

Trang 5

CPU_VID1 CPU_VID3 CPU_VID5 +1.5VS

VCCSENSE

VSSSENSE

CPU_VID0 (37) CPU_VID1 (37) CPU_VID2 (37) CPU_VID3 (37) CPU_VID4 (37) CPU_VID5 (37) CPU_VID6 (37)

VCCSENSE (37)

VSSSENSE (37)

+VCCP

+CPU_CORE

+VCCP

+1.5VS

+CPU_CORE

Title

SCHEMATIC,MB A5141

B

Title

SCHEMATIC,MB A5141

B

Title

SCHEMATIC,MB A5141

B

Length match within 25 mils The trace space 7 mils, Zo=27.4ohm

PLACE IN CORRIDOR AND CLOSE TO CPU PLACE IN CAVITY

PLACE IN CAVITY

2 x 330uF(9mohm/2)

130mA

C334 10U_0805_10V4Z

C334 10U_0805_10V4Z 1

2 C328

10U_0805_10V4Z C328

10U_0805_10V4Z

1

2

C327 1U_0402_6.3V6K

C327 1U_0402_6.3V6K 1

2

C299 10U_0805_10V4Z

C299 10U_0805_10V4Z 1

2

C295

0.1U_0402_16V7K C295

0.1U_0402_16V7K

1

2

C311 1U_0402_6.3V6K

C311 1U_0402_6.3V6K 1

2 C309

1U_0402_6.3V6K

C309 1U_0402_6.3V6K 1

2

C304

10U_0805_10V4Z C304

10U_0805_10V4Z

1

2

+C331 330U_D2_2.5VY_R9M

@

+C331 330U_D2_2.5VY_R9M

@ 1

2 U5D

AU80586GE025512_FCBGA437 N270@

U5D

AU80586GE025512_FCBGA437 N270@

VSS99 AA12 VSS98 AA15 VSS97 AA18 VSS96 AA19 VSS95 AA20

VSS9 B1

VSS84 N4 VSS83 M21 VSS82 M13 VSS81 M9 VSS80 M7

VSS8 A20

VSS79 M5 VSS78 M1 VSS77 L19 VSS76 L18 VSS75 L15 VSS74 L13 VSS73 L9 VSS72 L7 VSS71 L6 VSS70 L5

VSS7 A19

VSS69 L4 VSS68 L3 VSS67 K21 VSS66 K15 VSS65 K13 VSS64 K9 VSS63 K7 VSS62 K6 VSS61 K1 VSS60 J17

VSS6 A18

VSS59 J13 VSS58 J9 VSS57 J7 VSS56 J5 VSS55 H19 VSS54 H18 VSS53 H16 VSS52 H13 VSS51 H9

VSS5 A15

VSS49 H7 VSS48 H4 VSS46 H3 VSS45 G21 VSS42 G13 VSS41 G9

VSS4 A8

VSS39 G7 VSS38 G4 VSS37 G1 VSS36 F18 VSS35 F17 VSS34 F7 VSS33 F6 VSS32 F5 VSS31 F4 VSS30 E19 VSS29 E16 VSS28 E15 VSS27 E8 VSS26 E7 VSS25 E6 VSS24 E3 VSS23 D21 VSS22 D18 VSS21 D14 VSS20 D8

VSS2 A4

VSS19 D5 VSS18 D1 VSS17 C17 VSS16 C8

VSS158 N17 VSS157 P3 VSS156 P4 VSS155 P5 VSS154 P6 VSS153 P7 VSS152 P9 VSS151 P13 VSS15

P15 VSS148 P16 VSS147 P18 VSS146 P19 VSS145 R1 VSS144 R5 VSS143 R7 VSS142 R9 VSS141 R13 VSS140 R21

VSS14 B20

VSS139 T4 VSS138 T5 VSS137 T7 VSS136 T9 VSS135 T10 VSS134 T11 VSS133 T12 VSS132 T13 VSS131 T18 VSS130 U3

VSS13 B13

VSS129 U6 VSS128 U7 VSS127 U15 VSS126 U16 VSS125 U19 VSS124 V1 VSS123 V4 VSS122 V6 VSS121 V7 VSS120 V8

VSS12 B8

VSS119 V13 VSS118 V14 VSS117 V18 VSS116 V21 VSS115 W1 VSS114 W5 VSS113 W8 VSS112 W11 VSS111 W14 VSS110 W17

VSS11 B5

VSS109 W21 VSS108 Y1 VSS107 Y2 VSS106 Y20 VSS105 Y21 VSS104 AA2 VSS103 AA3 VSS102 AA4 VSS101 AA7 VSS100 AA10

VSS10 B2

VSS1 A2

VSS159 N13 VSS160 N9 VSS161 N7 VSS162 N5

C323

1U_0402_6.3V6K C323

1U_0402_6.3V6K

1

2 C314

1U_0402_6.3V6K C314

1U_0402_6.3V6K

1

2

C307 0.1U_0402_16V7K

C307 0.1U_0402_16V7K 1

2 U5C

AU80586GE025512_FCBGA437 N270@

U5C

AU80586GE025512_FCBGA437 N270@

VCCQ1 A9 VCCF V10

VCCPC63 F13 VCCPC62 E14 VCCPC61 E13

VCCQ2 B9

VCCA D7

VTT9 H14 VTT8 H8 VTT7 G14 VTT6 G8 VTT5 F9 VTT4 F8

VTT32 U14 VTT31 U13 VTT30 U12 VTT3 E9

VTT29 U11 VTT28 U10 VTT27 U9 VTT26 U8 VTT25 T14 VTT24 T8 VTT23 R14 VTT22 R8 VTT21 P14 VTT20 P8 VTT2 D9

VTT19 N14 VTT18 N8 VTT17 M14 VTT16 M8 VTT15 L14 VTT14 L8 VTT13 K14 VTT12 K8 VTT11 J14 VTT10 J8 VTT1 C9

VID[0] F15 VID[1] D16 VID[2] E18 VID[3] G15 VID[4] G16 VID[5] E17 VID[6] G18

VSSSENSE D13 VCCSENSE C13

VCCP1 A10 VCCP2 A11 VCCP3 A12 VCCP4 B10 VCCP5 B11 VCCP6 B12 VCCP7 C10 VCCP8 C11 VCCP9 C12 VCCP10 D10 VCCP11 D11 VCCP12 D12 VCCP13 E10 VCCP14 E11 VCCP15 E12 VCCP16 F10

VCCP33 L12 VCCP32 L11 VCCP31 L10 VCCP30 K12 VCCP29 K11 VCCP28 K10 VCCP27 J12 VCCP26 J11 VCCP25 J10 VCCP24 H12 VCCP23 H11 VCCP22 H10 VCCP21 G12 VCCP20 G11 VCCP19 G10 VCCP18 F12 VCCP17 F11

VCCP34 M10 VCCP35 M11 VCCP36 M12 VCCP37 N10 VCCP38 N11 VCCP39 N12 VCCP40 P10 VCCP41 P11 VCCP42 P12 VCCP43 R10 VCCP44 R11 VCCP45 R12

VCCPC64 F14

C324 1U_0402_6.3V6K

C324 1U_0402_6.3V6K 1

2

C325

1U_0402_6.3V6K C325

1U_0402_6.3V6K

1

2

C337

1U_0402_6.3V6K C337

1U_0402_6.3V6K

1

2

R221 100_0402_1%

C322 1U_0402_6.3V6K

C322 1U_0402_6.3V6K 1

2

C335

10U_0805_10V4Z C335

10U_0805_10V4Z

1

2

C320 1U_0402_6.3V6K

C320 1U_0402_6.3V6K 1

2

C326

1U_0402_6.3V6K C326

1U_0402_6.3V6K

1

2

R220 100_0402_1%

C46 10U_0805_10V4Z

C46 10U_0805_10V4Z 1

2 C300

10U_0805_10V4Z C300

10U_0805_10V4Z

1

2

C303 10U_0805_10V4Z

C303 10U_0805_10V4Z 1

2

C338 0.1U_0402_16V7K C338 0.1U_0402_16V7K 1

2

C308

1U_0402_6.3V6K C308

1U_0402_6.3V6K

1

2

C315 1U_0402_6.3V6K

C315 1U_0402_6.3V6K 1

2 C312

1U_0402_6.3V6K C312

1U_0402_6.3V6K

1

2 C310

1U_0402_6.3V6K C310

1U_0402_6.3V6K

1

2

C321

1U_0402_6.3V6K C321

1U_0402_6.3V6K

1

2

+C51 330U_D2_2.5VY_R9M

+C51 330U_D2_2.5VY_R9M 1

2

C47 10U_0805_10V4Z

C47 10U_0805_10V4Z 1

2 C302

10U_0805_10V4Z C302

10U_0805_10V4Z

1

2

+

C57

220U_B2_2.5VM_R35

+

C57

220U_B2_2.5VM_R35

1

2

C298

10U_0805_10V4Z C298

10U_0805_10V4Z

1

2

C301 10U_0805_10V4Z

C301 10U_0805_10V4Z 1

2

C341 1U_0402_6.3V6K

C341 1U_0402_6.3V6K 1

2

C313 1U_0402_6.3V6K

C313 1U_0402_6.3V6K 1

2

Trang 6

+H_VREF

H_D#55 H_D#37

H_D#14 H_D#12 H_D#2

H_XRCOMP

H_D#52

H_D#42 H_D#36 H_D#33 H_D#17

H_XSCOMP H_D#54

H_D#7 H_D#5

H_D#56

H_D#18

H_D#44

H_YRCOMP +H_SWNG0

+H_SWNG1

H_D#27 H_D#25

H_D#15 H_D#11

H_D#63 H_D#61

H_D#41 H_D#34

H_D#20 H_D#10 H_D#1

+H_SWNG1

H_D#46 H_D#40 H_D#26

H_D#59

H_D#30 H_D#19 H_D#0

H_D#57 H_D#49

H_D#28 H_D#24 H_D#22 H_D#8

H_D#58

H_D#50 H_D#47

H_D#35 H_D#32

H_D#6 H_D#3

H_D#16 H_D#13

H_D#23 H_D#9

H_D#53 H_D#51

H_D#43 H_D#39

H_YSCOMP

+H_SWNG0

H_D#62 H_D#60 H_D#48 H_D#38 H_D#29

H_D#45

H_D#31 H_D#21

H_A#3 H_A#5 H_A#7

H_A#11 H_A#8

H_A#12 H_A#10

H_A#15 H_A#13

H_A#17

H_A#20 H_A#18 H_A#21 H_A#19 H_A#22

H_A#27 H_A#25 H_A#23

H_A#28 H_A#31

H_A#24

H_A#29 H_A#16

H_ADS#

H_ADSTB#1 +H_VREF H_BNR#

H_BPRI#

+H_VREF H_RESET#

H_BR0#

CLK_MCH_BCLK#

CLK_MCH_BCLK H_DBSY#

H_DEFER#

H_DINV#2 H_DINV#0 H_DINV#3 H_DINV#1 H_DPWR#

H_DRDY#

H_DSTBP#0 H_DSTBP#2 H_DSTBN#3 H_DSTBP#1 H_DSTBN#1

H_HIT#

H_HITM#

H_LOCK#

H_CPUSLP#

H_TRDY#

H_RS#0 H_RS#2 H_REQ#4

H_REQ#0 H_REQ#2

DMI_RXP0

DMI_TXP0

DMI_RXN0 DMI_TXN0

DDR_CS1#

M_ODT1 DDR_CKE0

M_CLK_DDR1

M_CLK_DDR#0

M_ODT0

SMRCOMPN

MCH_CLKSEL0 MCH_CLKSEL2

PM_EXTTS#0

CFG5

ICH_POK PLTRST_R#

H_THERMTRIP#

PM_EXTTS#1

CFG3 CFG6

H_D#[0 63]

H_ADS# (4) H_ADSTB#0 (4)

H_BNR# (4) H_BPRI# (4) H_RESET# (4) H_BR0# (4)

CLK_MCH_BCLK# (12) CLK_MCH_BCLK (12) H_DBSY# (4) H_DEFER# (4)

H_DINV#3 (4) H_DINV#0 (4) H_DINV#2 (4) H_DPWR# (4) H_DRDY# (4)

H_DSTBN#[0 3] (4)

H_DSTBP#[0 3] (4) H_HIT# (4) H_HITM# (4) H_LOCK# (4)

H_RS#[0 2] (4) H_CPUSLP# (4) H_TRDY# (4) H_REQ#[0 4] (4)

DMI_TXN0 (17) DMI_TXN1 (17) DMI_TXP0 (17) DMI_TXP1 (17) DMI_RXN0 (17) DMI_RXN1 (17) DMI_RXP0 (17) DMI_RXP1 (17)

M_CLK_DDR0 (11) M_CLK_DDR1 (11)

M_CLK_DDR#0 (11) M_CLK_DDR#1 (11)

DDR_CKE0 (11)

DDR_CS0#

(11)

M_ODT0 (11)

MCH_CLKSEL0 (12) MCH_CLKSEL2 (12)

MCH_ICH_SYNC# (15) PM_BMBUSY# (17) PM_EXTTS#0 (11) PM_DPRSLPVR (17,37) ICH_POK (17,25)

CLK_MCH_DREFCLK# (12) CLK_MCH_DREFCLK (12) MCH_SSCDREFCLK# (12) MCH_SSCDREFCLK (12) MCH_CLKREQ# (12)

PLTRST# (15,17,19,24,25,27) H_THERMTRIP# (4,16)

DDR_CKE1 (11)

DDR_CS1#

(11)

M_ODT1 (11)

+VCCP

+VCCP +VCCP

+VCCP

+1.8V

+3VS +DIMM_VREF

Title

Layout Note:

H_XRCOMP / H_YRCOMP / H_VREF / H_SWNG0 / H_SWNG1 trace width and spacing is 10/20.

*

Low = DMI x 2 High = DMI x 4 CFG5

Strap Pin Table

Layout Note:

+DIMM_VREF trace width and spacing

is 20/20.

10uA

C50 be placed <100mils from GMCH pin

4Z 1

2

1

2

R188 10K_0402_5%

@ R188 10K_0402_5%

@

Calistoga-GSE_FCBGA998

U1A

H_XRCOMP A10 H_XSCOMP A6 H_XSWING C15 H_YRCOMP J1 H_YSCOMP K1 H_YSWING H1

H_D#_0 C4 H_D#_1 F6 H_D#_2 H9 H_D#_3 H6 H_D#_4 F7 H_D#_5 E3 H_D#_6 C2 H_D#_7 C3 H_D#_8 K9 H_D#_9 F5 H_D#_10 J7 H_D#_11 K7 H_D#_12 H8 H_D#_13 E5 H_D#_14 K8 H_D#_15 J8 H_D#_16 J2 H_D#_17 J3 H_D#_18 N1 H_D#_19 M5 H_D#_20 K5 H_D#_21 J5 H_D#_22 H3 H_D#_23 J4 H_D#_24 N3 H_D#_25 M4 H_D#_26 M3 H_D#_27 N8 H_D#_28 N6 H_D#_29 K3 H_D#_30 N9 H_D#_31 M1 H_D#_32 V8 H_D#_33 V9 H_D#_34 R6 H_D#_35 T8 H_D#_36 R2 H_D#_37 N5 H_D#_38 N2 H_D#_39 R5 H_D#_40 U7 H_D#_41 R8 H_D#_42 T4 H_D#_43 T7 H_D#_44 R3 H_D#_45 T5 H_D#_46 V6 H_D#_47 V3 H_D#_48 W2 H_D#_49 W1 H_D#_50 V2 H_D#_51 W4 H_D#_52 W7 H_D#_53 W5 H_D#_54 V5 H_D#_55 AB4 H_D#_56 AB8 H_D#_57 W8 H_D#_58 AA9 H_D#_59 AA8 H_D#_60 AB1 H_D#_61 AB7 H_D#_62 AA2 H_D#_63 AB5

H_A#_3 F8 H_A#_4 D12 H_A#_5 C13 H_A#_6 A8 H_A#_7 E13 H_A#_8 E12 H_A#_9 J12 H_A#_10 B13 H_A#_11 A13 H_A#_12 G13 H_A#_13 A12 H_A#_14 D14 H_A#_15 F14 H_A#_16 J13 H_A#_17 E17 H_A#_18 H15 H_A#_19 G15 H_A#_20 G14 H_A#_21 A15 H_A#_22 B18 H_A#_23 B15 H_A#_24 E14 H_A#_25 H13 H_A#_26 C14 H_A#_27 A17 H_A#_28 E15 H_A#_29 H17 H_A#_30 D17 H_A#_31 G17 H_ADS# F10 H_ADSTB#_0 C12 H_ADSTB#_1 H16 H_VREF0 E2 H_BNR# B9 H_BPRI# C7 H_BREQ0# G8 H_CPURST# B10 HCLKN AA6 HCLKP AA5 H_DBSY# C10 H_DEFER# C6 H_DINV#_0 H5 H_DINV#_1 J6 H_DINV#_2 T9 H_DINV#_3 U6 H_DPWR# G7 H_DRDY# E6 H_DSTBN#_0 F3 H_DSTBN#_1 M8 H_DSTBN#_2 T1 H_DSTBN#_3 AA3 H_DSTBP#_0 F4 H_DSTBP#_1 M7 H_DSTBP#_2 T2 H_DSTBP#_3 AB3

H_HIT# C8 H_HITM# B4 H_LOCK# C5 H_REQ#_0 G9 H_REQ#_1 E9 H_REQ#_2 G12 H_REQ#_3 B8 H_REQ#_4 F12 H_RS#_0 A5 H_RS#_1 B6 H_RS#_2 G10 H_SLPCPU# E8 H_TRDY# E10 H_VREF1 E1

1

2

R181 2.2K_0402_5%

R1811 2 2.2K_0402_5%

T32 PAD

@PADT32

@

R211 100_0402_5%

R203 0_0402_5%

R203 0_0402_5%1 2

1

2

R187 10K_0402_5%

R1871 10K_0402_5%2

U1B

U1B DMI_RXN_0 Y29 DMI_RXN_1 Y32 DMI_RXP_0 Y28 DMI_RXP_1 Y31 DMI_TXN_0 V28 DMI_TXN_1 V31 DMI_TXP_0 V29 DMI_TXP_1 V32

SM_CK_0 AF33 SM_CK_1 AG1 SM_CK_2 AJ1 SM_CK_3 AM30 SM_CK#_0 AG33 SM_CK#_1 AF1 SM_CK#_2 AK1 SM_CK#_3 AN30 SM_CKE_0 AN21 SM_CKE_1 AN22 SM_CKE_2 AF26 SM_CKE_3 AF25 SM_CS#_0 AG14 SM_CS#_1 AF12 SM_CS#_2 AK14 SM_CS#_3 AH12 SM_OCDCOMP_0 AJ21

SM_OCDCOMP_1 AF11

SM_ODT_0 AE12 SM_ODT_1 AF14 SM_ODT_2 AJ14 SM_ODT_3 AJ12 SM_RCOMPN AN12 SM_RCOMPP AN14 SM_VREF_0 AA33 SM_VREF_1

D_REFCLKP A26 D_REFSSCLKN J33 D_REFSSCLKP H33

THRMTRIP# J15 PWROK AB29 RSTIN# W27

PM_BMBUSY# G21 PM_EXTTS#_0 F26

CFG_0 C18 CFG_1 E18 CFG_2 G20 CFG_5 J20 CFG_6 J18

PM_EXTTS#_1 H26 RESERVED8 F18

CLKREQ# J22

CFG_3 G18

PM_ICHSYNC# E31

RESERVED9 A3 RESERVED7 C17 RESERVED1 K32 RESERVED2 K31

R232 80.6_0402_1%

R2321 280.6_0402_1%

R228 80.6_0402_1%

R2281 280.6_0402_1%

T33 PAD

@PADT33

@

Trang 7

DDR_A_DM0

DDR_A_DM3 DDR_A_DM1

DDR_A_DM4 DDR_A_DM6 DDR_A_DM2

DDR_A_DM5 DDR_A_DM7 DDR_A_DQS0 DDR_A_DQS2

DDR_A_DQS6 DDR_A_DQS3

DDR_A_DQS7 DDR_A_DQS4

DDR_A_DQS#1

DDR_A_DQS#4 DDR_A_DQS#6 DDR_A_DQS#2

DDR_A_DQS#5 DDR_A_DQS#7 DDR_A_DQS#0

DDR_A_D43

DDR_A_D27

DDR_A_D32 DDR_A_D2

DDR_A_D58

DDR_A_D26

DDR_A_D49

DDR_A_D15 DDR_A_D11

DDR_A_D47 DDR_A_D41 DDR_A_D6

DDR_A_D48 DDR_A_D46

DDR_A_D36

DDR_A_D40

DDR_A_D1

DDR_A_D8

DDR_A_D20

DDR_A_D54

DDR_A_D14 DDR_A_D10

DDR_A_D24

DDR_A_D63 DDR_A_D57

DDR_A_D39

DDR_A_D45 DDR_A_D37

DDR_A_D18

DDR_A_D9 DDR_A_D4

DDR_A_D30

DDR_A_D16 DDR_A_D13

DDR_A_D62

DDR_A_D17

DDR_A_D51 DDR_A_D19

DDR_A_D61 DDR_A_D52

DDR_A_D3

DDR_A_D38

DDR_A_D50

DDR_A_D12

DDR_A_D44 DDR_A_D29

DDR_A_D59

DDR_A_D0

DDR_A_CAS#

SA_RCVENIN#

SA_RCVENOUT#

DDR_A_WE#

DDR_A_BS0

DDR_A_D55

DDR_A_D22

DDR_A_D25

DDR_A_D34 DDR_A_D28

DDR_A_D33 DDR_A_D31

DDR_A_D56

DDR_A_BS2

DDR_A_MA13 DDR_A_MA11

DDR_A_MA1

DDR_A_MA6

DDR_A_MA9 DDR_A_MA10 DDR_A_MA12 DDR_A_MA5 DDR_A_MA0

DDR_A_MA7 DDR_A_MA4 DDR_A_MA2

DDR_A_BS0 (11) DDR_A_BS1 (11) DDR_A_DM[0 7]

(11)

DDR_A_DQS[0 7]

(11)

DDR_A_DQS#[0 7]

(11)

DDR_A_MA[0 13]

(11)

DDR_A_CAS#

(11) DDR_A_RAS#

(11)

DDR_A_WE#

(11)

DDR_A_D[0 63] (11)

DDR_A_BS2 (11)

Title

SCHEMATIC,MB A5141

Custom

Title

SCHEMATIC,MB A5141

Custom

Title

SCHEMATIC,MB A5141

Custom

U1C

SA_DQ_0 AC31 SA_DQ_1 AB28 SA_DQ_2 AE33 SA_DQ_3 AF32 SA_DQ_4 AC33 SA_DQ_5 AB32 SA_DQ_6 AB31 SA_DQ_7 AE31 SA_DQ_8 AH31 SA_DQ_9 AK31 SA_DQ_10 AL28 SA_DQ_11 AK27 SA_DQ_12 AH30 SA_DQ_13 AL32 SA_DQ_14 AJ28 SA_DQ_15 AJ27 SA_DQ_16 AH32 SA_DQ_17 AF31 SA_DQ_18 AH27 SA_DQ_19 AF28 SA_DQ_20 AJ32 SA_DQ_21 AG31 SA_DQ_22 AG28 SA_DQ_23 AG27 SA_DQ_24 AN27 SA_DQ_25 AM26 SA_DQ_26 AJ26 SA_DQ_27 AJ25 SA_DQ_28 AL27 SA_DQ_29 AN26 SA_DQ_30 AH25 SA_DQ_31 AG26 SA_DQ_32 AM12 SA_DQ_33 AL11 SA_DQ_34 AH9 SA_DQ_35 AK9 SA_DQ_36 AM11 SA_DQ_37 AK11 SA_DQ_38 AM8 SA_DQ_39 AK8 SA_DQ_40 AG9 SA_DQ_41 AF9 SA_DQ_42 AF8 SA_DQ_43 AK6 SA_DQ_44 AF7 SA_DQ_45 AG11 SA_DQ_46 AJ6 SA_DQ_47 AH6 SA_DQ_48 AN6 SA_DQ_49 AM6 SA_DQ_50 AK3 SA_DQ_51 AL2 SA_DQ_52 AM5 SA_DQ_53 AL5 SA_DQ_54 AJ3 SA_DQ_55 AJ2 SA_DQ_56 AG2 SA_DQ_57 AF3 SA_DQ_58 AE7 SA_DQ_59 AF6 SA_DQ_60 AH5 SA_DQ_61 AG3 SA_DQ_62 AG5 SA_DQ_63 AF5

SB_CAS# AG19 SB_RAS# AG21 SB_WE# AG20

SB_MA_0 AN20 SB_MA_1 AL21 SB_MA_2 AK21 SB_MA_3 AK22 SB_MA_4 AL22 SB_MA_5 AH22 SB_MA_6 AG22 SB_MA_7 AF21 SB_MA_8 AM21 SB_MA_9 AE21 SB_MA_10 AL20 SB_MA_11 AE22 SB_MA_12 AE26 SB_MA_13 AE20

SA_CAS#

AJ17 SA_RAS#

AK18 SA_RCVENIN#

AN28 SA_RCVENOUT#

AM28 SA_WE#

AH17

SA_MA_0 AJ15 SA_MA_1 AM17 SA_MA_2 AM15 SA_MA_3 AH15 SA_MA_4 AK15 SA_MA_5 AN15 SA_MA_6 AJ18 SA_MA_7 AF19 SA_MA_8 AN17 SA_MA_9 AL17 SA_MA_10 AG16 SA_MA_11 AL18 SA_MA_12 AG18 SA_MA_13 AL14

SA_DQS#_0 AC29 SA_DQS#_1 AK30 SA_DQS#_2 AJ33 SA_DQS#_3 AM25 SA_DQS#_4 AN8 SA_DQS#_5 AJ8 SA_DQS#_6 AM3 SA_DQS#_7 AE2

SA_DQS_0 AC28 SA_DQS_1 AJ30 SA_DQS_2 AK33 SA_DQS_3 AL25 SA_DQS_4 AN9 SA_DQS_5 AH8 SA_DQS_6 AM2 SA_DQS_7 AE3

SA_DM_0 AB30 SA_DM_1 AL31 SA_DM_2 AF30 SA_DM_3 AK26 SA_DM_4 AL9 SA_DM_5 AG7 SA_DM_6 AK5 SA_DM_7 AH3

SA_BS_0 AK12 SA_BS_1 AH11 SA_BS_2 AG17

SB_BS_0 AH21 SB_BS_1 AJ20 SB_BS_2 AE27

T9 PAD T9 PAD T8 PAD T8 PAD

Trang 8

LCTLA_CLK LCTLB_DATA

LCTLA_CLK

L_IBG LCTLB_DATA

GMCH_CRT_R

GMCH_CRT_B GMCH_CRT_G

LVDS_ACLK#

LVDS_ACLK

LVDS_A0 LVDS_A1#

LVDS_A1 LVDS_A2#

LVDS_A2 LVDS_A0#

PEGCOMP

CRT_IREF

LVDS_SDA LVDS_SCL

GMCH_CRT_G GMCH_CRT_B GMCH_CRT_R

GMCH_CRT_VSYNC_R

GMCH_CRT_VSYNC_R GMCH_CRT_HSYNC_R

CLK_MCH_3GPLL#

(12) CLK_MCH_3GPLL (12)

GMCH_CRT_DATA (14)

GMCH_CRT_R (14)

GMCH_CRT_G (14)

GMCH_CRT_CLK (14)

GMCH_CRT_B (14)

GMCH_ENVDD (13)

LVDS_ACLK (13) LVDS_ACLK#

(13)

LVDS_A0#

(13) LVDS_A1#

(13) LVDS_A2#

(13) LVDS_A0 (13) LVDS_A1 (13) LVDS_A2 (13)

GMCH_ENBKL (25)

LVDS_SCL (13) LVDS_SDA (13)

GMCH_CRT_VSYNC

(14)

GMCH_CRT_HSYNC

(14)

+3VS

+1.5VS

+1.5VS_PCIE

Title

SCHEMATIC,MB A5141

B

Title

SCHEMATIC,MB A5141

B

Title

SCHEMATIC,MB A5141

B

Close to U4.H25

Disable TV

Place R282,R296 close to F27,D27 11/18

R82 1 150_0402_1%

U1F

SDVO_CTRLCLK J27

G_CLKN Y26 G_CLKP AA26 SDVO_CTRLDATA H27

TV_DACA A21 TV_DACB C20 TV_DACC E20 TV_IREF G23 TV_IRTNA B21 TV_IRTNB C21 TV_IRTNC D21

CRT_DDC_CLK H20

CRT_DDC_DATA H22

CRT_BLUE A24 CRT_BLUE#

A23 CRT_GREEN E25

CRT_GREEN#

F25 CRT_RED C25 CRT_RED#

D25 CRT_VSYNC F27

CRT_HSYNC D27 CRT_IREF H25 L_BKLTCTL H30 L_BKLTEN G29 L_CLKCTLA F28 L_CTLBDATA E28

L_DDC_CLK G28 L_DDC_DATA H28

L_VDDEN K30 L_IBG K27 L_VBG J29 L_VREFH J30 L_VREFL K29 LA_CLKN D30 LA_CLKP C30

LA_DATAN_0 G31

LA_DATAN_1 F32

LA_DATAN_2 D31

LA_DATAP_0 H31

LA_DATAP_1 G32

LA_DATAP_2 C31

SDVO_RED N28 SDVO_GREEN M32 SDVO_BLUE P33 SDVO_CLKP R32

SDVO_RED# P28 SDVO_GREEN# N32 SDVO_BLUE# P32 SDVO_CLKN T32

SDVO_TVCLKIN M30 SDVO_INT P30 SDVO_FLDSTALL T30

SDVO_TVCLKIN# N30 SDVO_INT# R30 SDVO_FLDSTALL# T29

EXP_A_COMPI R28 EXP_A_ICOMPO M28

LB_DATAN_0 F33

LB_DATAN_1 D33

LB_DATAN_2 F30

LB_DATAP_0 E33

LB_DATAP_1 D32

LB_DATAP_2 F29

LB_CLKN A30 LB_CLKP A29

TV_DCONSEL0 G26 TV_DCONSEL1 J26

R92 1 150_0402_1%

R192 10K_0402_5%

R1921 10K_0402_5%2 R191 10K_0402_5%

R1911 10K_0402_5%2

R183 255_0402_1%

R1832 255_0402_1%1

R190 24.9_0402_1%

R282 39_0402_5%

R102 1 150_0402_1%

R1712 1 100K_0402_5%

R296 39_0402_5%

R184 1.5K_0402_1%

R1842 11.5K_0402_1%

Trang 9

+1.5VS +VCCP

+VCCP

Title

U1E

U1E VSS_1 AH33 VSS_2 Y33 VSS_3 V33 VSS_4 R33 VSS_6 AK32 VSS_7 AG32 VSS_8 AE32 VSS_9 AC32 VSS_10 AA32 VSS_11 U32 VSS_12 H32 VSS_13 E32 VSS_14 C32 VSS_15 AM31 VSS_16 AJ31 VSS_17 AA31 VSS_18 U31 VSS_19 T31 VSS_20 R31 VSS_21 P31 VSS_22 N31 VSS_23 M31 VSS_24 J31 VSS_25 F31 VSS_26 AL30 VSS_27 AG30 VSS_28 AE30 VSS_29 AC30 VSS_30 AA30 VSS_31 Y30 VSS_32 V30 VSS_33 U30 VSS_34 G30 VSS_35 E30 VSS_36 B30 VSS_37 AA29 VSS_38 U29 VSS_39 R29 VSS_40 P29 VSS_41 N29 VSS_42 M29 VSS_43 H29 VSS_44 E29 VSS_45 B29 VSS_46 AK28 VSS_47 AH28 VSS_48 AE28 VSS_49 AA28 VSS_50 U28 VSS_51 T28 VSS_52 J28 VSS_53 D28 VSS_54 AM27 VSS_55 AF27 VSS_56 AB27 VSS_57 AA27 VSS_58 Y27 VSS_59 U27 VSS_60 T27 VSS_61 R27 VSS_62 P27 VSS_63 N27 VSS_64 M27 VSS_65 G27 VSS_67 C27 VSS_68 B27 VSS_69 AL26 VSS_71 W26 VSS_72 U26 VSS_73 AN25 VSS_74 AK25

VSS_77 J25 VSS_78 G25 VSS_79 A25 VSS_80 H23 VSS_81 F23

VSS_111 J16 VSS_112 AL15 VSS_113 AG15 VSS_114 W15 VSS_115 R15 VSS_116 F15 VSS_117 D15 VSS_118 AM14 VSS_119 AH14 VSS_120 AE14 VSS_121 H14 VSS_122 B14 VSS_123 F13 VSS_124 D13 VSS_125 AL12 VSS_126 AG12 VSS_127 H12 VSS_128 B12 VSS_129 AN11 VSS_130 AJ11 VSS_131 AE11 VSS_132 AM9 VSS_134 AB9 VSS_135 W9 VSS_136 R9 VSS_137 M9 VSS_138 J9 VSS_139 F9 VSS_140 C9 VSS_141 A9 VSS_142 AL8 VSS_143 AG8 VSS_144 AE8 VSS_145 U8 VSS_146 AA7 VSS_147 V7 VSS_148 R7 VSS_149 N7 VSS_150 H7 VSS_151 E7 VSS_152 B7 VSS_153 AL6 VSS_154 AG6 VSS_155 AE6 VSS_156 AB6 VSS_157 W6 VSS_158 T6 VSS_159 M6 VSS_160 K6 VSS_161 AN5 VSS_162 AJ5 VSS_163 B5 VSS_164 AA4 VSS_165 V4 VSS_166 R4 VSS_167 N4 VSS_168 K4 VSS_169 H4 VSS_170 E4 VSS_171 AL3 VSS_172 AD3 VSS_173 W3 VSS_174 T3

VSS_5 G33

VSS_133 AJ9

VSS_175 B3 VSS_176 AK2 VSS_177 AH2 VSS_178 AF2 VSS_179 AB2 VSS_180 M2 VSS_181 K2 VSS_182 H2 VSS_183 F2 VSS_184 V1 VSS_185 R1

VSS_66 E27

VSS_70 AH26

VSS_75 AG25 VSS_76 AE25

VSS_82 B23 VSS_84 AJ22 VSS_85 AF22 VSS_86 G22 VSS_83 AM22

VSS_87 E22 VSS_88 J21 VSS_89 H21 VSS_90 F21 VSS_91 AM20

VSS_100 AF18 VSS_99 AH18 VSS_98 AM18 VSS_96 W19 VSS_95 D20 VSS_94 AF20 VSS_92 AK20 VSS_93 AH20

VSS_97 R19

VSS_101 U18 VSS_102 H18 VSS_103 D18 VSS_104 AK17 VSS_105 V17 VSS_106 T17 VSS_107 F17 VSS_108 B17 VSS_109 AH16 VSS_110 U16

U1G

U1G NC1 W33 NC2 AM33 NC3 AL33 NC4 C33 NC5 B33 NC6 AN32 NC7 A32 NC8 AN31 NC9 W28 NC10 V27 NC11 W29 NC12 J24 NC13 H24 NC14 W32 NC15 G24 NC16 F24 NC17 E24 NC18 D24 NC19 K33 NC20 A31 NC21 E21 NC22 C23 NC23 AN19 NC24 AM19 NC25 AL19

NC29 AN3 NC30 Y9 NC31 J19 NC32 H19 NC33 G19 NC34 F19 NC35 E19 NC36 D19 NC37 C19 NC38 B19

NC41 G16 NC42 F16 NC43 E16 NC44 D16 NC45 C16 NC46 B16 NC47 AN2 NC49 Y7 NC50 AM4 NC51 AF4 NC52 AD4 NC53 AL4 NC54 AK4

NC57 AH4 NC58 AG4 NC59 AE4 NC60 AM1

NC64 Y5 NC63 AL1 NC62 Y6 NC61 W30

RESERVED26 Y25 RESERVED27 Y24 RESERVED28 AB22 RESERVED29 AB21 RESERVED30 AB19 RESERVED31 AB16 RESERVED32 AB14 RESERVED33 AA12 RESERVED34 W24 RESERVED35 AA24 RESERVED36 AB24 RESERVED37 AB20 RESERVED38 AB18 RESERVED39 AB15 RESERVED40 AB13 RESERVED41 AB12

NC28 AH19 NC26 AK19 NC27 AJ19

NC39 A19 NC40 Y8

NC48 A16

NC55 W31 NC56

NC65 Y10 NC66 W10 NC67 W25 NC68 V24 NC69 U24 NC70 V10 NC71 U10 NC72 K18

NCTF

U1H

NCTF

U1H VCC_NCTF1 T25 VCC_NCTF2 R25 VCC_NCTF3 P25 VCC_NCTF4 N25 VCC_NCTF5 M25 VCC_NCTF6 P24 VCC_NCTF7 N24 VCC_NCTF8 M24 VCC_NCTF9 Y22 VCC_NCTF10 W22 VCC_NCTF11 V22 VCC_NCTF12 U22 VCC_NCTF13 T22 VCC_NCTF14 R22 VCC_NCTF15 P22 VCC_NCTF16 N22 VCC_NCTF17 M22 VCC_NCTF18 Y21 VCC_NCTF19 W21 VCC_NCTF20 V21 VCC_NCTF21 U21 VCC_NCTF22 T21 VCC_NCTF23 R21 VCC_NCTF24 P21 VCC_NCTF25 N21 VCC_NCTF26 M21 VCC_NCTF27 Y20 VCC_NCTF28 W20 VCC_NCTF29 V20 VCC_NCTF30 U20 VCC_NCTF31 T20 VCC_NCTF32 R20 VCC_NCTF33 P20 VCC_NCTF34 N20 VCC_NCTF35 M20 VCC_NCTF36 Y19 VCC_NCTF37 P19 VCC_NCTF38 N19 VCC_NCTF39 M19 VCC_NCTF40 Y18 VCC_NCTF41 P18 VCC_NCTF42 N18 VCC_NCTF43 M18 VCC_NCTF44 Y17 VCC_NCTF45 P17 VCC_NCTF46 N17 VCC_NCTF47 M17 VCC_NCTF48 Y16 VCC_NCTF49 P16 VCC_NCTF50 N16 VCC_NCTF51 M16 VCC_NCTF52 Y15 VCC_NCTF53 P15 VCC_NCTF54 N15 VCC_NCTF55 M15 VCC_NCTF56 Y14

VCCAUX_NCTF1 AD25 VCCAUX_NCTF2 AC25 VCCAUX_NCTF3 AB25 VCCAUX_NCTF4 AD24 VCCAUX_NCTF5 AC24 VCCAUX_NCTF6 AD22 VCCAUX_NCTF7 AD21 VCCAUX_NCTF8 AD20 VCCAUX_NCTF9 AD19 VCCAUX_NCTF10 AD18 VCCAUX_NCTF11 AD17 VCCAUX_NCTF12 AD16 VCCAUX_NCTF13 AD15 VCCAUX_NCTF14 AD14 VCCAUX_NCTF15 K14 VCCAUX_NCTF16 AD13 VCCAUX_NCTF17 Y13 VCCAUX_NCTF18 W13 VCCAUX_NCTF19 V13 VCCAUX_NCTF20 U13 VCCAUX_NCTF21 T13 VCCAUX_NCTF22 R13 VCCAUX_NCTF23 P13 VCCAUX_NCTF24 N13 VCCAUX_NCTF25 M13 VCCAUX_NCTF26 AD12 VCCAUX_NCTF27 Y12 VCCAUX_NCTF28 W12

VSS_NCTF1 AN33 VSS_NCTF2 AA25 VSS_NCTF3 V25 VSS_NCTF4 U25 VSS_NCTF5 AA22 VSS_NCTF6 AA21 VSS_NCTF7 AA20 VSS_NCTF8 AA19 VSS_NCTF9 AA18 VSS_NCTF10 AA17 VSS_NCTF11 AA16 VSS_NCTF12 AA15 VSS_NCTF13 AA14

VTT_NCTF1 T10 VTT_NCTF2 R10 VTT_NCTF3 P10 VTT_NCTF4 N10 VTT_NCTF5 L10

VCC_NCTF57 W14 VCC_NCTF58 V14 VCC_NCTF59 U14 VCC_NCTF60 T14 VCC_NCTF61 R14

VCCAUX_NCTF29 V12 VCCAUX_NCTF30 U12 VCCAUX_NCTF31 T12 VCCAUX_NCTF32 R12 VCCAUX_NCTF33 P12 VCCAUX_NCTF34 N12 VCCAUX_NCTF35 M12 VCCAUX_NCTF36 AD11 VCCAUX_NCTF37 AD10 VCCAUX_NCTF38 K10

VCC_NCTF62 P14 VCC_NCTF63 N14 VCC_NCTF64 M14

VTT_NCTF6 D1

VSS_NCTF14 AA13 VSS_NCTF15 A4 VSS_NCTF16 A33 VSS_NCTF17 B2 VSS_NCTF18 AN1 VSS_NCTF19 C1

RSVD_3 M10 RSVD_4 A18 RSVD_5 AB10 RSVD_6 AA10

CFG_19 K28 RESERVED10 K25 RESERVED11 K26 RESERVED12 R24 RESERVED13 T24 RESERVED14 K21 RESERVED15 K19 RESERVED16 K20 RESERVED17 K24 RESERVED18 K22 RESERVED19 J17 RESERVED20 K23 RESERVED21 K17 RESERVED22 K12 RESERVED23 K13 RESERVED24 K16 RESERVED25 K15

Trang 10

U4_AA1 U4_A14

U4_F1 U4_A7

+1.5VS_3GPLL

+2.5VS_CRTDAC

+1.5VS

U4_AM32 U4_AB33

+VCCP

+1.5VS

+VCCP

+1.5VS +3VS

+1.8V

+1.5VS_MPLL +1.5VS_HPLL +1.5VS_DPLLA +1.5VS +2.5VS

+1.5VS +1.5VS_3GPLL

+1.5VS

+1.5VS_DPLLA +1.5VS_DPLLB

+2.5VS

+1.5VS_PCIE

+1.5VS_3GPLL +2.5VS

+2.5VS +2.5VS

+VCCP

+1.5VS

+2.5VS

+1.5VS

+2.5VS

+VCCP

+2.5VS

Title

PCI-E/MEM/PSB PLL decoupling

45mA Max.

close pin B31

Route +2.5VS from GMCH pinN33 to decoupling cap <200mil to the edge.

CRTDAC: Route FB within 3" of Calistoga

Disable TV

40mA Max.

780mA

400mA

Route VSSACRTDAC gnd from GMCH to decoupling cap ground lead and then connect to the gnd plane.

2mA 20mA

10mA

60mA

70mA

40mA 2940mA

1250mA

144mA

45mA 50mA 150mA 45mA

533 MTS=1720mA

400mA

70mA

45mA Max.

10mil 10mil

10mil

10mil 10mil

10mil

10mil 10mil 10mil

close pin C29/D29

To be confirmed 11/14

add net name(+VCCP_D)

20mil 12/10

Co-layout with C249 add C268 01/22

change C249 BOM structure(@) 01/23 Del C249 02/18

4Z 1

2

1

2

+

M_R35 +

1

2

1

2

1

2

1

2

1

2

1

2

R172 10_0603_5%

R172 10_0603_5%1

@

1

2

1

2

1

2

1

2

C25

0.47U_0603_16V4Z C25

0.47U_0603_16V4Z

4Z 1

2

1

2

1

2

1

2

D15 RB751V-40TE17_SOD323-2

@ D15 RB751V-40TE17_SOD323-2

@

1

2

1

2

1

2

1

2

6K 1

2

C319 1U_0402_6.3V4Z C319 1U_0402_6.3V4Z 1

2

1

2

6K 1

2

R210 0_0603_5%

1 2

1

2

1

2

+

M_R35 1

2

R168

10_0402_5%

@

R168

10_0402_5%

@

C248 0.47U_0603_16V4Z C248 0.47U_0603_16V4Z 1

2 C283 0.47U_0603_16V4Z C283 0.47U_0603_16V4Z

1 2

L20 FBM-L10-160808-301-T_0603 L20

FBM-L10-160808-301-T_06031 2

1

2

R45 0_0603_5%

1 2

+C13

1

2

U1D

U1D VCC0 T26 VCC1 R26 VCC2 P26 VCC3 N26 VCC4 M26 VCC5 V19 VCC6 U19 VCC7 T19 VCC8 W18 VCC9 V18 VCC10 T18 VCC11 R18

VCCDHMPLL1 AE5 VCCDHMPLL2 AD5

VCCADPLLA B26 VCCADPLLB J32 VCCAHPLL AD2 VCCAMPLL AD1

VCCACRTDAC0 C24 VCCACRTDAC1 B24 VSSACRTDAC B25 VCCSYNC J23

VTT0 A14 VTT1 D10 VTT2 P9 VTT3 L9 VTT4 D9 VTT5 P8 VTT6 L8 VTT7 D8 VTT8 P7 VTT9 L7 VTT10 D7 VTT11 A7 VTT12 P6 VTT13 L6 VTT14 G6 VTT15 D6 VTT16 U5 VTT17 P5 VTT18 L5 VTT19 G5 VTT20 D5

VCCA3GBG N33 VSSA3GBG M33 VCCA3GPLL V26 VCC3G0 U33 VCC3G1 T33 VCCTXLVDS1 C29

VCCSM0 AB33 VCCSM1 AM32 VCCSM2 AN29 VCCSM3 AM29 VCCSM4 AL29 VCCSM5 AK29 VCCSM6 AJ29 VCCSM7 AH29 VCCSM8 AG29 VCCSM9 AF29 VCCSM10 AE29 VCCSM11 AN24 VCCSM12 AM24 VCCSM13 AL24 VCCSM14 AK24 VCCSM15 AJ24 VCCSM16 AH24 VCCSM17 AG24 VCCSM18 AF24 VCCSM19 AE24 VCCSM20 AN18 VCCSM21 AN16

VCCHV0 E26 VCCHV1 D26 VCCHV2 C26

VCCALVDS B31

VCCDLVDS0 C28 VCCDLVDS1 B28 VCCDLVDS2 A28

VCCDTVDAC F20 VCCDQTVDAC F22

VCCATVBG D23 VSSATVBG E23

VCCATVDACA0 B20 VCCATVDACA1 A20 VCCATVDACB0 B22 VCCATVDACB1 A22 VCCATVDACC0 D22 VCCATVDACC1 C22

VCC12 W17 VCC13 U17 VCC14 R17 VCC15 W16 VCC16 V16 VCC17 T16 VCC18 R16 VCC19 V15 VCC20 U15 VCC21 T15 VCCAUX1 AD33 VCCAUX2 AD32 VCCAUX3 AD31 VCCAUX4 AD30 VCCAUX5 AD29 VCCAUX6 AD28 VCCAUX7 AD27 VCCAUX8 AC27 VCCAUX9 AD26 VCCAUX10 AC26 VCCAUX11 AB26 VCCAUX12 AE19 VCCAUX13 AE18 VCCAUX14 AF17 VCCAUX15 AE17 VCCAUX16 AF16 VCCAUX17 AE16 VCCAUX18 AF15 VCCAUX19 AE15 VCCAUX20 J14 VCCAUX21 J10

VCCAUX26 AD8 VCCAUX27 AD7 VCCAUX28 AD6

VCCTXLVDS0 D29

VCCSM22 AM16 VCCSM23 AL16 VCCSM24 AK16 VCCSM25 AJ16 VCCSM26 AN13 VCCSM27 AM13 VCCSM28 AL13 VCCSM29 AK13 VCCSM30 AJ13 VCCSM31 AH13 VCCSM32 AG13 VCCSM33 AF13 VCCSM34 AE13 VCCSM35 AN4 VCCSM36 AM10 VCCSM37 AL10 VCCSM38 AK10 VCCSM39 AH1 VCCSM40 AH10 VCCSM41 AG10 VCCSM42 AF10 VCCSM43 AE10 VCCSM44 AN7

VTT22 U4 VTT23 P4

VCCSM45 AM7

VTT24 L4 VTT25 G4 VTT26 D4 VTT27 Y3 VTT28 U3 VTT29 P3 VTT30 L3 VTT31 G3 VTT32 D3 VTT33 Y2 VTT34 U2 VTT35 L2 VTT36 P2 VTT37 G2 VTT38 D2 VTT39 AA1

VTT45 Y1

VCCAUX22 H10 VCCAUX23 AE9 VCCAUX24 AD9 VCCAUX25 U9

VSSALVDS B32

VTT44 U1

VTT41 P1 VTT42 L1 VTT43 G1 VTT40

F1

VCCSM46 AL7 VCCSM47 AK7 VCCSM48 AJ7 VCCSM49 AH7 VCCSM50 AN10 VCCSM51 AJ10

VTT21 Y4

1

2

6K 1

2

1

2

@ C287

@ 1

2

1

2

+

M_R35 1

2

C267

1

2

1

2

L2 FBM-L10-160808-301-T_0603 L2 FBM-L10-160808-301-T_06031 2

C22

0.47U_0603_16V4Z C22

0.47U_0603_16V4Z

1

2

+

+

1

2

1

2

R38 0_0603_5%

1 2

1

2

6K 1

2

1

2

R177 0_0805_5%

R177 0_0805_5%1 2

1

2

1

2

1

2

Tiêu đề	Acer Aspire One AOP531H D520 (Compal LA 5141P) Schematics Diagram
Trường học	Compal Electronics, Inc.
Chuyên ngành	Electronics
Thể loại	Tài liệu kỹ thuật
Năm xuất bản	2009
Thành phố	Taipei

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Số trang	12
Dung lượng	596,31 KB