Acer aspire e1 v1 v3 531 571 COMPAL LA 7912p REV 02

NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC... NEITHER THIS SHEET NOR THE I

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Model Name :Q5WV1/Q5WS1

Compal Project Name :

File Name : LA-7912P

MB PCB

[pasooo0svoo |PCB 0N4 LA-7912P REVO M/B |

Security Classification Compal Secret Data Compal Electronics, Inc

AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE GUSTODY OF THE COMPETENT DIVISION OF R&BIZ?

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NI3P GS/GL Sandy/Ivy Bridge BANK 0, 1, 2, 3 page 11,12

USB 3.0 conn x1 MINI Card x1 LAN(GbE) & port 1 porto port 2

Fresco FL1009 WLAN Card Reader SATA HDD

page 46~59 eve Security Classification Compal Secret Data Compal Electronics, Inc

DECARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS ING, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS | CSP 4019ID 5

Date:

Ï

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+CPU_CORE Core voltage for CPU ON | OFF| OFF|

+VGA_CORE Core voltage for GPU ON | OFF] OFF | +VGFX_CORE Core voltage for UMA graphic ON | OFF| OFF | +0.75VS +0.75VP to +0.75VS switched power rail for DDR terminator ON | OFF| OFF |

+1.5VS +1.5V to +1.5VS switched power rail ON | OFF| OFF |

+1.8VS (+5VALW or +3VALW) to 1.8V switched power railto PCH & GPU ON | OFF| OFF|

+3VS +3VALW to +3VS power rail ON | OFF| OFF |

+5VS +5VALW to +5VS switched power rail ON | OFF| OFF |

Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF

EC SM Bus1 address EC SM Bus2 address

internal USB SKU:

eDP SKU: EDP@

SIGNAL

$3 (Suspend to RAM) Low Low | HIGH HIGH ON oN OFF OFF S4 (Suspend to Disk) Low Low Low | HIGH ON OFF OFF OFF

Board ID / SKU ID Table for AD channel

UHCIO 0 USB3.0 colay USB2.0 Coni

1 USB/B (Right Side)

UHGTL : USB/B (Right Side)

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC

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JGPU1A

PEG ICOMPI PEG COMP spacing =15mils

PES IcOMPO Ties ——F

<15> DMI_GRX_PTX_NO DMI_RX#[0] PEG_RCOMPO

<15> DMI CRX PTX N3 DMI_RX#[3] PEG RX#[0 PE a Hae ae 1 2 ae Lo 0

<15> DMI_GRX_PTX_PO DMI_RX[0] PEG_ RX#[2 E “HN E 1 poe = =

<15> DMI CRX PTX P1 DMI_RX[1] PEG_AX#[3 = SHAY Gạo T2 Cšere 0

<I5> DMI CEX PTX P2 DML_ RX[2] HH PEG _RX#l4 PEG GIX CG HRX N10 _C71_4 ||» GSGL@_0-

<15> DMI CTX_PRX N0 92L Í DMI_TXz[0] Q PEG_RX#[7 Ee ae “— HE

<15> DMI CTX_PRX N2 Ee MIT xa] PEG_RX#[9 FC ĂGTx CTRx SiIU là Do 0

<15> DMI CTX PRX P1 Can | DMI TXH1] PEG RXZ[13 Ee GTO CHAK S59 DềĐ—0

<I5> DMLCTX PRX P2 E20 Í DMI Txị2] Ứ)_ PEG RXMiI4 PEG GTX CHEK NO Cla | [> Dis

<15> DMI CTX PRX P3 DMI_TX{3] C) PEG.MHS =— x E^— 2

PEG GIX G_HRX P15_C47 GSGL@_0

1 PEG_RXI0 EG GIX © HRX F14 C50 : 2š rễ 0

a PEG AX EG GTX_C_HRX C52 ¡ || 2 GSGL@ 0

a EG GIX GC HRX Pl2_G L@ 0

<15> FDI_CTX PRX N0 22T | FDI0._TX#[o] Ay PEG_RX[3 pee cy Ễ TRE Km L] +23 lộ 0

<15> FDI GTX PRX N1 E19 | FDI0 TX#[1] Kí PEG_ RX[4 EGuET+ C HRY Sea | re

<I5> FDI GTX PRX N2 E12 FDlo Txef2] PEG_RX[5 Em lạ FSO

<15> FDI CTX PRX N3 bi | FDI0 TX#[3] 4 œ PEG_RX[6 EG GTX © TRY Se L2 bề [@ 0

<15> FDI CTX PRX N4 BếT | FDI1TX#i0] CD PEG_ RX[7 PEG CTX CTRXPT co Om

<15> FDI_CTX_PRX_N5 G20 FDI _Txalt] A PEG_RX{8 PEGGTXC HAY PE C100-L] Lo DIS@0

PEG_RX11 EG GIX_G HRX C17 1 || 2 DISG —0

A22 — PEGAGAL 2 PEG GIX GC HRX P2 C119 4 || 2 DIS@ 0

<15> FDI_CTX_PRX_PO £22 FIO TX{0] Œ +% PEG_ RX[13 PEG GIG HRX Pi C135 1 | [> DĐ —0

<15> FDI CTX PRX P1 B1 | FDI0 TXÍT] œ_ PESRXI4 =e GDC Oe HAX SïEDRR Do 0

<15> FDI.GTX PRX P2 C20 | FDI0 T12] — E5 PEG_AX[15 — = p2 DIS@ 0

<15> FDI CTX PRX P3 218 Í rDIo TX[3] PEG HTX GR C 0

<15> FDI CTX PRX P4 B20) FDH_Tx{0} " BỊ PESTXMD PEG HT ay 3 cers | 2886 Lo 5

<15> FDI CTX PRX P5 112 |rDI1 TXH] q@ PEG_TX#[1 BEG HTX GRY E520 + || > -G8cLo 0

<15> FDI GTX PRX P6 D19 | FDII TXi2] 44) MPEG Txal2 FO HICERX Nia Chad] [> GSELO 0

<15> FDILCTX_PRX_P7 FDI1- TX[3] Cc OQ, PEG Tals FST CRY Se | esclo 0

eDP COMPIO and ICOMPO signals should *1-°VS_VTT <15> FDI_FSYNCO EE——*2 FDIO_FSYNC HH <i BEG Dats een ep eee

be shorted near balls, <15> FDILFSYNG1 FDI_FSYNC Irị BEG Ty PEG _HTX_GRX C544 { || 2 GSGL@ 0

Trace Width for EDP_COMPIO=4mils, <15> FDI_INT [>2] rpị nt Seg Eee E2 RS

EDP _ICOMPO=12mils — , <15> FDI_LSYNCO FDIO_LSYNG - À1 PEG TX#[10 PEG TX#9 CEN EG _HTXGA sms c5 ree 0 8

and both length less than 500 mils 15> FDILLSYNC1 FDI1_LSYNG Opes putt PEG HTX GRx ST Am 2

should not be left floating 24.9 0402 1% Ay PEG Txzj12 EG HTX GRY Ne E558 4 2 DIS@ 0

" Pe TiS E GR C560 { || 2 DiS@ 0

PEG_TX[2 EG HDCGRXPI2 Cane 1 ||-2-GSGL@ 0

<81> EDP_AUXP G15) op AUX PEG Td Ee HT GRE eee 1} 2 Bete 8

Add eDP circuit <31> EDP-AUXN — D15 Í eDp_AUX# PEG TX[5 EG HTX Gay Flo ch a |e ese ra 0

Oy BEG TAY EG HTX _GRX C5451 [2 CSCL@ 0

<31> EDP_TXPO SIZ] pp _Tx{o] ^ PEG_TX{8 sea Saag bo Bee

<31> EDP_TXP1 pet oO pee EG HDT GRY P S:bIIREI > _DIS@ 0

+1.05VS_VTT GIB opp Tx{3] PEG_TX{11 EOI CRE cae mm nse

— <31> EDP_TXNO cm eDP TX#[0] PEG TX[13 PEG_TX[12) PEG HTX GRY P EG HTX GRY Pe G557 1 C559 2 Di§@—0 DI 0

¥1.05VS_VTT BEG _ICOMPI and PEG_RCOMPO signals should be

shorted and routed, max length = 500 mils,trace width=4mils

249 0402 1% PEG_ICOMPO signals should be routed with - max

length = 500 mils,trace width=12mils

GE

Typ- suggest 220nF The change in AC capacitor

value from 100nF to 220nF is to enable

AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF Ri DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC

SCHEMATIC,MB A7912

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SNB_IVB# had changed the name to

PROC_SELCT#,function for future platform,

connect to the DF_TVS strap on the PCH

BCLK Pape ee Cu DE ——S Tr Bet CLK_CPU_DMI <14>

<17> H_SNB_IVB# <——+T—————“°- proc seLecte ©) Œ) BCLK# GLK CPU DMI# <14>

4 © 4 DPLL_REF_CLK# DPLL_REF_CLK [age CLK CPU DFLLE <€—|CLK CPU DPLL# <14È` CLK_CPU_DRLL <i> pe? | | CLK CPU _DPLL B516 2 JVIS@ { 1K 0402 5% l

CLC CPUDPLEF B18 > aye 11K 0402 5% Ì/2O105VS VTT

use integrated without eDP

Processor Pullups <18,40> H_PECI H_PEC! PECI SM_DRAMRST# SM_DRAMRST# SM_DRAMRST# <6> DPLL_REF SSCLK# PH 1K 5% to +1.05VS VTT

oo aS SM RCOMPE Ad SM RCOMP2 R712 YAY A_1 200 0402 1%

<18> H_THRMTRIP# A THRMTRIP# THERMTRIP# FH DDR3 Compensation Signals vo

PRDY# DẬEZ9

Tok |-4826 TEK @ pap tes § “aS

TMS LẬRZ—————=-—®& PAD 167

<18> H_PM_SYNC H_PM_SYNG PM_SYNC a TReT> TRSTE PAD tes ©

UNCOREPWRGOOD:3ECOREZHUROK CĐ tø XDP DBRESET#

LAL35

PM DRAM PWRGDR_ PM DRAM PWRGD A va | SM_DRAMPWROK E6 wy)

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JCPU1C

N RAD RA Da | SA-DG15] DE SA DOf4] SA_CLK{1] SA_CLK_DDR1 <11> ` ABD E— SE SB DOI3) B24 sp Dara] SB_CLK{1] SB_CLK_DDR1 <12>

` A B38 J5 Í SA DO[38 > SA_DQS#[1] -~GS —BBR A DOSE \ B ise ANI SB DG[38 > s8 DOS#Il E——EEE si

` RA DSS R 4 AIS) sa Dai39 I mì SA_DOSul2] | 13 | PDR A DOSHe R ` RB DSS RB D4 AP2 1 SB DQI39 _ [r] SB DQS#[2] SE = BBE_B DOSH2 | RB

ee a Ala sa" Da{40 SA_Doszl3| LM8—BBE-2-Dđšïi E-E-Bẩ——AF 2| s8 Do[4o = se_Dosaisl L4 _—XSm-gBđSï†—4

\ RA D4 AK9 Í SA DO[43 SA_DOS#(6] -AB12 DDR A DOSi6 ` RB D4 ATS Ì sB DO[43 SB_Dosz[s| | AK12_ĐDH Ð D6

` na RA Dd ALB SA_DO|44 7 > SA_DOS#[7] I AMIS _DDR_A_DOS#? ` ne D4 AB Dd APE! SB Dal44 | = $B _DOS#[7] | FARIS DOR _B_DOS#7

BDE-A-D: AH3_| SA DOj45 [x] RE Di ANH | sB_DG[45 [x]

\ A D&S AL1LÍ SA DOI53 SA_Dasi|4] FALE DDR A DUS4 \ B _D53 ABE Ì sp DO[53 S8 DOsij4] | ẠN6_—EP

` BS AP12 Í SA DG[54 ~~ SA Dass] FAM2—BBR A DOSS ` RB Dod A.J12_Í SB DO[54 os $B Dass] FALE PB

RA DoS ANI? | a Daiss SA_DQs|6] FABLL—BOR A Doss RE DSS ALI? Se pass ¬ SB_DOSis| |[âKLL—CEE Doss

HA BE ——~H+| sA_Do[5ẻ a SA_Dasi7] PAMI4 DDR A DQS/ — ⁄ RE P88 AT11_1 cap ajng OQ $B_Dasj7] FAP14 DDR B Das? /

` DORA De0arta | oe POLS RA DSS AK15 Í SA DOJ59 ¬ mf >DDR A MAI0.15] <11> ` RB DSS E12 sẽ po[so AT14 sp pase D {> DDR_B_MA[O 15] <12>

CC CC CC C7 7 C7 C7 7 7 C7 C7 7C CS 7C TC C7 TC TC CS CS CS CC CONN@ ` eẮee CONN@

<5> SM_DRAMRST# [_ > SWeRANESL a an mm ^^” { > DIMM_DRAMRST# <11,12>

0.1U 0402 16V4Z chị 4.99K 0402 1% RST GATE hgih ,MOS ON

SM DRAMRST# HIGH,DIMM DRAMRST# HIGH

s3

<11,12,14> RST_GATE RST GATE Low ,MOS OFF

SM DRAMRST# lo,DIMM DRAMRST# HIGH

Dimm not reset

0.047U 0402_16V7K SM DRAMRST# lo,DIMM DRAMRST# low Issued Date 2011/06/02 2012/06/02 Title

SCHEMATIC,MB A7912

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TYCO_2013620-2_IVY BRIDGE CONN@

Be S90 GFGi0] V§S DIE SENSE -AH28 @ @ PAD T74

ANSI CEG i13] Rsvp34 M33

ANZE CEG 14] RSvp35 Ade AM2Z 4 CFG [15]

Aa GCFG[16]

VESAYG VAI "SENEF VAXG_VAL_SENSE RSVD39 |H1Š—~- attached to Embedded Display Port

VEC VAT SENEE TẠI | VSSAXG, VAL SENSE RSvD40 C18

connected to the Embedded Display Port

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDE! - : Site Document Number SCHEMATIC,MB A7912 ev

AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custpm 4 1 ID f B MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC

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fD2a | VCC27 =e vociozs FELL

An | VOC30 th VCCIO28 Faas

AC | VGC31 ry VCGIO2g [ĐT

Tao | VCC33 AY VCCIO31 [ E1»

AA32 Í vGG44 AÀ3D Í VGG46

M34 | VCOá2 a Q VIDALERT# p4l22_—t OR a LẪ~2 - VR SVID ALRT# <52>

wa voces Q Ky VIDSGLK 2»50—TTEPU-SVIĐAT Rado a do VR_SVID_CLK <52>

List VOC75 VGG77 Wee) voc7e

+CPU_CORE L2] VCC80

poz _| YOC9s VSS_SENSE VCCIO| Š R163 !

fy a — —! Should change to connect form

Yn power cirucit & layout differential

—

SCHEMATIC,MB A7912

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+VGFX CORE

2 | VAXGI Tr] 3 vaAxe SENSE VOC AXG SENSE <52>

ATI8B

Ane vaxcs mf SM 7 7 7 ỐC

AE 1ê | VAXGII SM_VREF |_ÂL1 +

REO VAXG16 CG sA_DIMM_VREFDQ SS DINN-VRETOG SA_DIMM_VREFDQ <11>

2 1E | VAXG17 t>> SB_DIMM_VREFDQ SB_DIMM_VREFDQ <12>

BETZ VAXG18 ANE VaXG20 VAXG21 AN20

ALT | Vaneau 4 VccsA1 LMez +VCGSA BI37 1 /Ñ „ 2 0 0402 5% +VCGSA SENSE

ALET Ì VAXGBI VOGSA4 28 he fs ans fs fae

R528 S080 5% ch ¬ ¬ + ao | a0 cH VCCPLL2 % © VGGSA VID[o | Ê2Z eee H VGGSA VID0 <51>

,82 fe fe 2 | ce fl ce VCOPLL3 lên VGCSA VID[I] “4 H VGGSA VID1 <51>

RSVD26 had changed the name to VCCIO_SEL

R909 10K_0402_5%

R913 10K_0402_5%

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DDR_A DQS#1 2 bose 1 vn r1 DDR_AO_DM1

lạ All VREF traces should ———— TT DDR_A_DQS1 DDR A DIO 4L] vssii 29 | 5481 REserz vssi2 F824 [20 DDR3_DRAMRST# DDR A Did =O < ] DIMM_DRAMRST# <6,12> Ị z2 zQ c8 c8

DDR_A D16 PS vs512 38 poie vsst4 Lộ 4 DQ20 DDR_A_D20 DDR A D2 = 8 S8 o> ==£# > = 8 > = >

44 4 œ

DDR A Dose 421 nase vssi7 [484 DDR A D22

DDR_A Dig p25} S520 534 Dats VSSi9 F244 DQ28 DDR A D28 BA ¬ CC CC CC S777 7 7õ 7õ 7c 7c 7 7 7 7 7c 7 7 c7 7 | DDR ADs S—Í po24 DGQ2g [28

DDR_A0_DM3 tea tee oe 84 DDR_A_DQS3

<6> SA_CLK_DDRO SA_CLK_DDRO Tôi CKO ao lùa SACL DDR! SA_CLK_DDR1 <6> : ts “L's “I's

<6> SA_CLK_DDR#O SA CLK DDREG 103 _Í <koz GKiz [104 ĐĂNG.LK_ DUE SA CLK DDR#1 <6> „1s T8 T5 72s le

— — DDR_A MA10 105 107 FAP VDD12 Bay (408 pon ee DDR A BS! <é> | bò œ 2 bP? œ 3 bị œ 3

<6> DDR A BSO [_ > DDR A B50 ing BAO RASH ig DDR_A RAS# <6> | $ $ $

D13 VDD14

<6> DDR_A_WE# DDR_A WEE 1a] Wee So 114 a —=¬ DDRA_CS0_DIMMA# <6> 4

<6> DDR_A_CAS# E> DDR _A CASH 1154 casi ODT0 [118 SA ODT0 <6» 1K_0402_5%

DDR A MA13 va] YOO" Opt 120 SA ODT! <]SA.O0T1 <6> | Vv

<6> DDRA_CS1_DIMMAa >>DDRA CS1_DIMMA# d1 St# NG2 H2

12p | VDDI7 SỈNGTEST VREF GA VDD18 [756 +VREF CA Poo TT 7 7 777777 77 7 7 7 7 7 7 7 7 T7 7T ẽ Sẽ n1

DDR_A D32 2 \ssz; vsses AY DDR_A D36 © |

DDR_A_D33 181) Dass DQ@32 DQ36 [T22 DQ37 DDE A D37 Đo = 20 R266 +0.75VS ọ

por ADQszs ‡ Sa] boas vee = DDR_AQ_DM6

DDR A Dose 121) nose vss43 T4 DDR A D54 Poo 7C 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 |

DDR A D50 [| hòn Da | 17 DDBA DSS DDR A Dei IZ 5051 VSS45 L4 DDR A D60

AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF Ri Custbm B DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 4 1 ID

ONICS, INC

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTR › Date: Friday, January 06, 2012 [Sheet 7 of m

1

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3

+1.5V

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

M3 support 00402_5% | | © © DDR B DO BI hon Pos ES DDR B D5 Po C7 7 7 7 7 7 7 7 7 T7 T7 T7 TS TS TT TT

<9> SB_DIMM_VREFDQ > TA ^^ ¡e8 | le8 C8 | Ck BOR OF 9Í vsea Dat pos# 10 vssa ä—4 DDR B DQSz0

—=ễˆ > DDR Ð DASHO.7] <b>

DDE-B-D9 2| Do8 pare [3 DDRCEDTS OR A 15] <>

DDR B DOST 29 Í poài REsETz L30 DDR DRAMRST#e—] DIMM_DRAMRST# <6,11>

have 10 mil trace width DDR 8 Dĩi 35 | ni pare 46 DDR 8 D15 lv isy Place near JDIMM2

DDR _B_D26 LÊ] pene vest La DDR B D30 [TT TT TT TT TT TT TT

TL] vs525 vsSas | 24

| se] se] se] se

<6» DDRB CKE0 DIMMB [_—>>—DDBB GKE0 DIMMB 3Í c«co GKEi Z£ DDRB CKEI DIMMB_———DDRB CKE1 DIMMB <6» | HCR AES ft CS h Fs

SB_CLK_DDRO Tại | VD VDD10 [T SB_GLK DDRI

DDR B MA13 Ta yO vonts T20 $B ODT1 <—]s8.00T1 <> — | Š Š 2

DDR 8 _Ds0 Me boro Does L 1/8 DDR 5 Dồ5 ¡ —=ăẽ ¬

| 5 § l Security Classification Compal Secret Data Compal Electronics, Inc

Date:

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5

¡ +RTCVCG 398

+8VALW_PCH ° hE kHð RTCX) PCH A20 |pTcxi FWH0/LADo Cä8—E=<_AR? LPC_ADO <40> | |

- | C36 ZO PCH RTCK2 © FWHI/LaD1 PASE a LPC ADI <40» | -

c + 1.5V when smapled high On Die PLL VR Select is supplied by Ị Ị C356 OS = mi SM_INTRUDER# TT 2g INTRUDERE oO 4 LDRO1# / GPIO23 KSB Q1#/G LDRQo# ĐE38< | HQLUấ£ =— Sp HOLDe SH —” ) 7 | WP# HOI D# SCLK S! pe _PCH [> BCH SPI MISO_2 SPI MOST 2 c

1.8V when sampled low _0603_ se —————=— —CI/]INrvRMEN SERIRo [MB——>—®———<— ]srRlRo <40- MXZBLT6DBEM2LT2G SO8

380402 5% act PCH <42> HDA_SDINO HDA SDINO HDA_SDINO SATA2RXN SATA_PRX_DTX_N2 <34> | voi fy Raa 33P_0402_50VBK | «

Boot BIOS | GPIO51 | GPIO19

Issued Date 2011/06/02 Deciphered Date 2012/08/02 Title SCHEMATIC MB A7912

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDE! Kp 2 79

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custbm 4 1 ID B MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC

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SE nó PRXDTCPI PCIE PRX DIX PÍ —B44 | pep sy SMBAIERT#/ GION PCH GPIO11 _ ] Wr

° 7> PCIE PRX DTX N2 PCIE_PRX DIX N2 — RE44 | aren SMBDATA PCH SMBDATA CH SMBDATA <37> PCH SMBCLK B67 1 AA, 2 — 22K 0402 5%

SỈ? POIE.PTX-C DRX P2 C877 rn | TU_0402 167K PCIE_PTX_DAX P2 ava? | bets n ast GATE

©

<87> MINH_CLKREQ# [[—> MINIT CLKREQ# Mle) pclECLKRQI# / GPIO18 CLKOUT_DP_N/ CLKOUT_BCLK1_N4 CLK CPU DPLL# LK_GPU_DPLL# <5 |

CLKOUT_DP_P/GLKOUT BCLK1 P 4 GLK GPU PLL LK CPU DPLL <ã-120 MHz £or eDP PGH SMLIDATAa ]4&[ + EC SMB DÀ2 ,—EG SMB_DA2 <22,40>

PCH_SML1GLK 3 TT ¿ EC SMB CK2 EC SMB CK2 <2240

<35> CLK PCIE LANE SLK_PCIELANH _ya7 | vOUT pGIESN LẦN DMIE Né B440 — GLKIN GND1# B563 1 2A A2 10K 0402 5% | Ị —<— <—>Fc_§MB GK2 <2240>

PCIE LAN <35> CLK PGIE LAN Sf CEK POGIE LAN — So cess CN DMIZ p4 BGäo— CLKIN-GNDï BBBI 1 AVAVA 2 10K 0402 5% 2 Q388

<35> LAN_CLKREQ# = [> RFE OH ABQ PCIEGLKROSH/ GPIO25 CLK_BUF_DREF_96Mé _R220 10K _0402_5% for using internal Clock

GLKIN DOT SỌN GLKIN DỌT 96p + P2 C—=S=~ CLK-BUE-DREE-96M — B22i ee A Ae ee ef CL T0K 0402 5% L FF

<22> GLK PEG_VGA# Do» CLK PEG VGA K PEG Ss CLK PEG VGA — AB40 CLLOUT PEQ.B.P LKOUT_PEG_B_N iBEenB_] XTAL25 OUT XTAL25 IN‡X4——Sm— 3+4 XTAL2SOUT váo XTAL25_OUT 10P_0402_50V8J _0402- _ _ 10P_0402_50V8J _0402-

>348 PCLKOUT PGIE7N „ GLKOUTFLEX0/GPIO644 GLK FLEXO @ Tạ PAD LÍ

>3 ÿGLKOUT_PCGIE7P = v Ù CLKOUTFLEXI / GPIOes4 E47 CLK FLEX1 e @ T73 PAD Reserve for EMI please close to U33

Ö CLKOUTFLEX2/ GPIQe6 q-H42_ +58 “See ly T29 PAD Ị

| Red4 R668 | Security Classification Compal Secret Data Compal Electronics, Inc

] 2.2K_0402_5% 0402 | 2.2K_0402_5% £ or sare _0402_ £ | issued Date 2011/06/02 Deciphered Date 2012/08/02 The SCHEMATIC,MB A7912

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC -

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| +8VALW_PCH Ị <4> DMI_CTX_PRX_N0 D er PA 4 8G24_Ì DWIoRXN FDI_RxNo _È14 oe 0 FDI GTX_PRX N0 <4>

<4> DMI_CTX_PRX_N2 š SOBRE a} DMIZRXN FDI RxN2 -REL4_— no ae FDI_CTX_PRX_N2 <4>

“ww <4> DMI GTX PRX 4> DMI CTX PRX PO DMI_CTX PRX SR P0 — BE24 DMIORXP LDI_ RXN4 FDI_RXN5 [E12 EDI eee CTX PRX FO CDC PRX NS M4 |_CTX_PRX_N5 <4>

R610 2 AA-1 10K 0402 5% b Rl# | <4» DMI GRX PTX N0 DMI_CRX_PTX_NO DMI-CRX-PTX NI A22] DMI0TXN FoL_RxPo PRS g EDI RXP1 LEE1f DỊ CTX-PRX ÉTX PRXE EDI GC PM PÓ <d> EDI_CTXSRAX_P1 <d>

<4> DMI CRX PTX N2 = DMI2TXN FDI_RXPa [BE FT FDI CTX PRX P3 <4»

LÍ R597 2 AVAVA-L 200 0402 1% PM DBAM PWRGD St, DML-CRX.PTX_Nã C XNG — —AV18_] DMISTXN "me FDI_RXP4 BE T2 Pole * ne FDI CTX PRX P4 <4> LJ

NN | <4> mm DMI_CRX_PTX | .=e.ằốằằ.- a BT DMIOTXP Z| E19 Bes PASI FDI_RXP6 KT Foret ar = ro ore Pre <b _CTX_PRX P6 <4»

H552 — 2 A/AvÀ—L 10K 0402 5% — PCH HSMHST# <4» DMILCRX PTX PI DMI-CE-BTSCPE—— A2 | DMI1TXP FDI_RxP7 |BH9 ĐI GIÁ PHX L FDI GTX_PRX_P7 <4»

Ho - 5-5-7 + - 7 [| DMI_ZCOMP FDI_FSYNCO FLL _FSYNGO FDIFSYNC0 <4>

ao 55 sa 9 0402 1% OMe DMI_IRCOMP FDI_FSYNC1 LDỊ TSYNG! FDILFSYNG1 <4> |

asp BH21 | DMI2RBIAS FDI_LSYNC0 cee FDI LSYNC0 <4» Ô

4mil width and place FDI LsyNc1 } BBO EDI LSYNG1 > rnLsNGL < DSWODVREN - On Die DSW VR Enable |

OSWVRMEN DSWODVREN

I==—=—=——=—-—-— -—-— — -—— PWROK {4 ® SUS_STAT#/ GPIO61 — SUS _STAT# Tee PAD @ | PCH PCIE WAKE# Cl C # R@i3 6 LAA ,p2 10K 0402 5° OK_0402 5% | |

— SUSWARN SUSWARNE Kg | SUSWARN# /SUS_PWR_DN_ACK/GPIO30 SLP_S3# pea PM sip ssw [7 PM SUP S3# —, PM_SLP_S3# <40>, Can be left NC

<40> PBTN_OUT# [> PBTN OUT# E201 PWRBTN# SLP_A# beia Tạ P^P - T7 _———S c “_=_=_-_- — | platfrom

<40,44,47,48> ACIN a) CÍ75IH-A0PT SOD2232 ACPRESENT / GPIO31 SLP sUs# 18 Hà ean | Deep S4,S5 can NG | B

Issued Date 2011/06/02 Deciphered Date 2012/06/02 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDE Kp D N SCHEMATIC,MB A7912

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS: Custpm 4019ID B MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC -

I

Trang 16

<31> PGH_ENVDD<C——]†————4**>] L vpp EN SDVO_TVCLKINP4AP45

<31> DPST PWM <—]——————4*'Ì L_bxLTcTL SDVO_STALLN Pada

<40> ENBKL < ENBKL R532 2 AA pL 0402 5% IGPU BKLT EN | <31> PCH LCD_DATA <S> X47ÌL DDC DATA SDVO INTN |_ẬP39

CTRL CLK SDVO_INTP FAPSO, SDVO_CTRLDATA strap pull high

C2043 ==c2044 q 2 1 LVDS IBG _ Ars LVD_IBG SDVO_GTRLCLK4 SDVO SGLK SDVO_SCLK <33>

10P_0402_50V8J b nạn 0402 508) say 1% »âF36 Í Lvp vBG SDVO_CTRLDATA Pisa —SbVO-SDATA SDATA > SDVO SDATA <33>

BI A A Arne bck 0402 Se TRL CLK <31> PCH_TXQUTO- eo LVDSA_DATA¥O J DDPB_1N A43 SEE PCH _DPB_N1 <33>

R158 LAA, 22 22K 0402 5% a CTRL DATA | <31> PCH_TXOUTI- <31> PCH_TXOUT2- PÉT TXOUTZ- LVDSA_DATA#1 LVDSA_DATA#2 ® 3 DDPB_2N [2H28 DDPB 1P ee —EETTDPB PCH DPB P1 <33> POH DPB _N2 <S8> HDMI D1 DMI DO

B156 22K 0402 5% PCH LGD CLK | PCH TXOUTO yw ‘a DoPB-an -AWAZ PCH poe PCH_DPB_NS <335

<31> PCH_TXOUTI+ Lela POUNCE LVDSA_DATA1 ® 7

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custbm 4 1 ID B MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Dat rd 5 06 DOTS Ish 7 Tế 7 cũ

ate: friday, January A eel G

Trang 17

@

C184 TPio NV_DQ3/ NV_103 FALL NBD tpi} NV_DQ4/ NV_104 FAS

ed TP12 NV_DQ5/ NV_105 FAT

AMS TPis5 NV_DQ8 / NV_lo0g FBBLx

OR lTpis S NV DO9/NV IOg | Bâ3>

>24 tpi7 Z- NV DOi0/NV lOio EBS

»4B45 Í Tpao a NV DO13/NV IO13 BEB

> NV DO14/NV IO14 BEDS

2 NV DO15/NV IO1s BEB BAY Tp} NV_ALE A5 orp PAY DE TVS

PCH USB3 TX1 N = TP32 USBP0N |_C2# Em ae USB20_NO <39

<39> PCH_USB3_TX1_N TP33 USBPoP _Â24 USB20.Po 30JSB Comn Colay USB3.0

TP34 USBP1N 625— SE USB20 N1 <39 TP35 USBPIP -a2s {S620 FI USB20.P1 -3eJSB/B (Right side)

PCH USB3 TXi P TP36 USBP2N _C28— 33820 Be USB20 N2 <39 _=

<39> PCH_USB3_TX1_P TP37 USBP2P -A28 USB20_P2 <aoÙJSB/B (Right side)

›âM28 | Tpao USBP4P |_H28¬

USBP4P |_-DZ28>‹

USBP5N C2 USBP5P |_Â28—<

USBPäN F€2#>~ ;— ——————=—=—=—=——=——=—————-—-—-—-— ——-

EEI EIRSRr PIROA# USBP7N [M28 ! Some PCH config not support USB port 6 & 7

Re Rg PIROBr PIRQC# O USBP8N eee ne USB20_N8 <37> Mini Card 1 (WLAN)

—————““——— $d piope 0, USBP8P USB20 P8 <37>

USBPON E805 DGPU HOLD RST#

—EEN GIEO REOI#/ GPIO50 m USBP9P FE40~ làn Nịo

SON S229 REoe: GPIO52 U USBP10N SEO PIG USB20.NI0 <I> Ang ¢ LVDS

<14,25,44,51,53> VGA_LON <8 ON 40d REQ3# / GPIOS4 5 USBP10P 4SB20- P40—<34>— amera ( )

USBP11N USB20_N11 <39>

et sot ee Dg GNT1#/GPIO51 USBP11P USB20_P11 <39> BlueTooth | BET

SBIR 2 GNT2# / GPIO8S USBP12N S82

EÉH epicg S220] PIRQEZ / GPIO2

ST GPIOE C42C| PIRQG# / GPIO4 USBRBIAS#

€ PIRQH# / GPIO5

PAD TỊ8 @y 10 rey USBRBIAS ROS Modify

OG1#/GPIO40

————ï>— ”—^v\~L ee eet Be CLKOUT PIO OG3# / GPIO42

Be AA oe otk TS 14 CLKOUT_PCIt OC4#/ GPIO43 PAD Tioư@ ® Em Pế olde > CLKOUT._PCI2 OC5#/GPIO9

PLT_RST#

U15 MC74VHG1G08DFT2G_SC70-5

DF_TVS Rư26 TK 0402 5% HLSNB IVB# <5» CLOSE TO THE BRANCHING POINT poe ee

+3VALW_PCH

oO

SCHEMATIC,MB A7912

Trang 18

PCH _GPIOO BMBUSY# / GPIO0 TAGH4 / GPIO68 PCH GPIO66

TO Deep S4,S5 wake event signal <39> 39> WL EN# [_——>——————————^+ WL_ WL_EN# ` TACHI / GPIO1 TACH5 / GPIO69 EBH,L———~-—— PCH_GPIO69

No use PD to GND Check 1ist1.0 P.70 <46» EG SMW [_ >——~*” Git) apios -| 10K 0402 5% []

! MSATA_DET# O PECI p-ALie PCM PEC) ae MaKe <> 0.0402 5901256 FLPEG <5,40> 00 = ¬ | PRCT CPU-EC |

Dep PwRok TAGHO / GPIO17 is 5 PROCPWRGp FAY {> H_cGPUPWRGD <B> - —-—- —-—-——-— — 4 fon CPU power ok |

<37,39> BT_ON# STP_PCl# / GPIO34 AKA

PCH CPions SATA2GP / GPIO36 akin ——! TS_vssl~4

When used as GP input Security Classification Compal Secret Data Compal Electronics, Inc

SCHEMATIC,MB A7912

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS: Custpm 4019ID B

Trang 19

+VCCADAC should be powered up during S0~

system state,Note that Thermal” Sensor™

+VCCADAG

U33G POWER rod foot FT:

veCTX_LVDS[4] C305 C310 22U 0805 6.3V6M

| VCCFDIPLL,VCCAPLLEXP,VCCAPLLDMI2 | AN17 Í wccIo(iej Oo vad LL cat

|_,VCCAPLLSATA, | 3711mA | = VG3_37] 1U 0402 16V7K V PROC TO 1.05 0.001 | Processor I/F

fee as [ce eon fice en fice on | cs œ8 VGCIO[22] Ol Hi es OQ 47mA C344 VecADAC 3.3 0.001 supplied by the core well poy 3 p

& 5 & & Š AP28 Í vecIot2a| oD veciopt] F4886 1U_0402_6.3V6K

HH

Ngo vocs_3[3] a VCGPNAND(2] L Gug/CCDETHRM should PH +1.8VS or +3V§ VecDMI 1.05 0.042 DMI Buffer Voltage

/ 2 APTZ Í Viccio(27] "

VccALVDS 3.3 0.001 only)

AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF Ri

SCHEMATIC,MB A7912

Trang 20

rm VCC3_3 = 266mA detal waiting for newest spec

‹ * PAD TÍ7 G @_— +:PGH VCCDSW DCPSUSBYP vcclopsa) | 1#

—======—=—=—=—=-=—=-=—=—=-—-—-——=- “PAD TH @ gy +VGGAPLL GPY PGH — BH23 | và.-2 | DI 95mA VOGSUS3_317] + +

2 +1.05VS,VCCA B_DPL s s g AD28 Í /ecAsW[12] 9 VCCSUSS_3[4] + evs

sEa089861298 TT 3 Wel vecaswiig) = ty LO voos_sft] AAI

D20U 2.5VMB2 Ì ® wea | vocaswrt đó vcs sre) Ma LÍ cma G343 | | c309

+1.05VS VCCA A DPL VCCADPLLA 8O, CoP gap) aap pan nnn + Qn-Die PLL Voltage Regulator |

+108V§ VTT MESADPLLB = + VGCAFDI VaM | VCCFDIPLL,VCCAPLLEXP, VCCAPLLDMI2 |

| i att |b core 1h cat | Are veciofs] 55mA veciorz) FACIE $

| Place | Place Place AG48 AD17 1U_0402_6.3V6K

Issued Date 2011/06/02 | Deciphered Date 2012/06/02 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDE! Kp D N SCHEMATIC.MB A7912

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custbm 4 1 ID B MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC

Trang 21

AD39 AD4 VSSI33 VSS[112 AP30 AP32

Ba, | VSS[167 VSS[267] 5a

Ba vss[168 vss[268] 38 Eat vss[169 vss[269] Fee ae] VSSI170 VSSf270] [rap

Ea | VSS[171 VSSI271] [tt Eth vss[t72 vss[272| Atle BEL vssit73 yssj273] -RLS

BB20 | VSS[175 vss|275| | M22 BB22 | SS[176 vss[276] Med BB24 | VSS[177 vss[277] |-M40

Bea vss[t79 vssje79] |-Met baa | VSS[180 VSS[280] vet sae | V9S[181 VSSI281] [2>

Be 2| VSS[192 vssl2g2l F2 BOAR vssi193 Vssl2a] [E L5] VSS[194 vss[2e4] FES

ao | V9S[195 vss[295] FBS BEaa | VSS[198 vss[296] Fes Beet vss[197 VSSI297] T2 RE] VSSJ 198) VSSl2a] [+2 REICH vSS[199) VSS[299] [+2 BEie| VSS[200) VSS[300] [+

BEaa_| VSS[202) VSS[302] 74 BES vss[203 VSSja0g] F2 BE2e-| VSS[204 VSSj304] [nh Broe | VSS[205) VSSI305] [1y

bó | VSS[206) VSS[306] Fig Bzan_ | VSS[207] VSS[307] [V2 Ban —| VSS[208) vss[308] Fee Geet) VSS[209) vss[309] FS

BEB | vss[211 VSS[311] | a8 BGI7 Í vss212) vsS[312] R28

BC vss[2i3 vss[313] FY B22 | VSS|214 VSS[314] [FT — bón | VSS[215 vss[315] Fig Bre] YSsi216 VSSI316] Fw Bots vssi2t7 VSSI317] [2

Bia | VSS[219 vSSI31o]

La | VSS[220 VSS[320] FYag Bia vssi221 vss[s21] Fs Brel vss|222 vss[s22] Aas BEAL vss[223 vss[s23] ae Bee | VSS[224 vSSI324] [XÃ

D | VSS[233 VSSI347] [14 D22] VSS|234 VSSI336] [TT Ệ

De | VSS[240) VSSI346] [T22 Eic | VSS[241 VSSI347] 454

Ea | VSS[242 VSSI348] LÊ

=2] VSS243 VSSj34o] [E18 Sản] VSSI244 VSs[350] sete Góc | VSSJ245 vss[351] FREE

628 1 vss[247)

G36

Saa—| VSS[248) tủa | VSS[250

Lo | VSSI251 toa | VSS[252

tr | VSS[254 tia, | VSS[256

=a | VSS[257 VSS[258

COUGARFOINT_FCBGA989~D

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDE Kp D N SCHEMATIC.MB A7912

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS: Custpm 4019ID B MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC

Trang 22

SẼ PEG.HTX <4> _HTX C GRS P4 €_GRX | ANS BEX RX2_N PEX RX3 GPIO4 FE vip 4 GPIO5 F-———==—— } Š se fe! fe! S pS GO JŠ |

TTX 6 GRX PE aXe oO eplol2 GPU_ACIN | vido R GPIO4 | O | LCD BLEN

<4> PEG_HTX_C_GRX_N10 PEX_RX10_N /GPIO20 FE2— + gi KE KE OE KE | se

<4» PEG HIX € GRX P12 THITXC GBXT AN24 Ï bEx nx12— | N132/M = NC 21020, 21 se eB.c Ase se So _)se Yo _)se So _)s8 Se

+ ông <4> _HTX_C_GRX_ nh PEX RX15 DAGA_RED Lo | | PE EERE roe Ƒ Ƒ FT :

DACA_BLUE ^L2>-

<4> PEG _GTX_HRX P3 PEX TX3 wo DACA_VREF 422

<4> PEG GTX HRX N3 PEX_TX3_N DACA_RSET ƑAP3-

<4> PEG GIX HRX P6 PEX TX6 Ww

<4> PEG GTX HRX N6 PEX TX6 N mm

<4» PEG_GTX_HRX_N8 PEX_TX8_N baz l2CBSO PCB SCL _ ; | GPIO16| O | THERM_LOAD_STEP_UP

<4> PEG GTX HRX N10 PEX TX10_N WN scocsoLF ren tim

<4> PEG GTX HRX N13 PEX TX13_N

<4> PEG GTX HRX P14 PEX TX14

PLLVDD PEX_WAKE_N

3WepePU ono Se] se CLK PEG VGA TÔ SP PLLVDD m PLLVDD TassGpU GPIO22| UO | SLL RASTER_SYNC

-0402 5| 14> GLK PEG VGA# PEX_REFCLK_N VID_PLLVDD

wo wo

se se

SCHEMATIC,MB A7912

Custpm

9ID

Trang 23

Na FBA_D4 FBA D5 P28 EBA D7 FBA D8 FBA_D10 FBA_D11 FBA D13 FBA D14 FBA D15 FBA_D16 FBA D18 FBA D20 FBA D21 FBA D22 FBA D24 FBA_D26 FBA_D28 FBA D30 FBA D31 FBA D33 FBA D34 FBA_D36 FBA_D38 FBA D40 FBA D41 FBA D42 FBA D44 FBA D46 FBA_D48 FBA D50 FBA_D5I FBA D53 FBA_D54 FBA_D56 FBA_D58 FBA D60 FBA D61 FBA D62

[J fh ko

FBA_CMD22 |-AAga Aarne Ree BS BB _D22 FBB_CMD22 1# =

< FBA-CMb2e | 40 eee ee DILÍ rap D2s FBB_CMD26 f-D16 =

FBA_CMD_RFUO Paces Bến G24] 88 D365 = FBB_CMD_RFuUo Fle

PBA CLK „=> Beas D40 Í FBp_ D47 FBB_CLK1 LKC1 <30>

màng Cả | rBB D49 De: FBB_D50

De: FBB_D51

Ree Bed | FBB_Deo

DC62 B26 >

| Under GPU | DGSErE EBB_DQS_RNB Gnd, a x BLMT6PG330SNi_2P= ¥

| close to ball : U27, BOSCH FBB_DOS_RN6 CV4B Under GPU Sip Monn (88-002 | Seo

issued Date 2011/08/02 Deciphered Date 2012/06/02 Tite SCHEMATIC MB A7912

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custpm I B MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC -

Trang 24

A — o> + Le hs {se o> œ

IFPA_TXDS_N 7 NC Poza b # x # # # x x Loe mousy SD084100289 SD034100280

Nc Pa S Sx Bs\es Ss 3 Gs des

AP = ‘| — MS lo o> Ww

AL 8Ä Irpp-TxDz N VCOSENSE VGA + Bi $D034100280 $D034100280

— — VDD_SENSE L4 near 1 2 [ >>VCCSENSE_VGA <53>

AKT IFPC_LO All IFPC_LO_N

AN ANH 4 IFPD L0 TESTMODE AK11 ioe, DIS@ 2 10K 0402 5% oY »

Al4d) irpp_L2.N JTAG_TMS FAP a er @ PAD 14 g

aD QO F10657 TÚK 0402 55 For N13P-GS(ES) strap table

AC | IEPE Lo ADS IFPE_LO_N

ACI IrpE L1 N

‘A att 7 Lo ROM CS# R1064{ D 2 10K 0402 5% 9

AC4d IroEL2EN ROM Ser P14 HOM SGLK Nhu 128M" 16*8 | Hynhk R R R R R R R R

AC4 irpELa- rp) ROM sị | Hồ— BOM SI N13P-6S 900 MHz 2GB SA00003YO20 PU4BK PD3BK PD15K PDSK PDIOQK PD35K PU 10K PU 5K

A IFPE L3 _N ROM SO H—E€M SỐ

AEA iFPF_LO_N AE4+ Í irpr Lị mal

AD4 Ì irpr 12

8 A IFPF_L3_N - CEC 1810661 R10664 RIGS, _2_10K 0402 5% oi 3vsDGPU PI 10K 0402 5%

; ULTI STRAP_REF0 GND R1067/ V 402K D402 1% 2GB SA00003YO20 | PU45K PD 45K PU10K na Wa PD 35K PD 10K PD 15K

\

Ị IFPD_AUX_12CX_SCL STRAP2 [“Ê THAp IFPD_AUX _I2GX_SDA_N STRAPS TRE

TU TÔ STRAP4 -ä AP For N13M-GS(QS) strap table

\ IFPE_AUX_I2GY_SCL

` Z

N13P-PES-A1_FCBGAQ08 GF108@

Trang 25

<14,17,44.51,53> VGA_ON

DIS@ L_

C603 0.1U_0603_25V7K

DIS@

| DIS@

C612 0.1U_0608_25V7K

- _ = = — N N = A eT FBVDDO aa 0 PEX IOVDD_0 2A1 acto 7 z ` | Pes a5 2S ,RaS | a5) as, {| a Ros as aS as = as =

¡35 [3s [3a [3a [Sa [Say AEZ7 FBVDDO 6 \ total 2700mA, Near GPU Under GPU : )

ni = = h h h Nó E124 EVDDO 11 Eid | FBvDDQ 12 PEX IOVDDQ_3 PEX IOVDDO 4A5 5 ¬gZ Tes 5S soe of bse Les bss sŠ bss sŠ hss Sẽ hss Sẽ

LÌ #3 | Số | $2 | Ca l Hog § EBYDDO 26 bis ; | 2 B5 B5

HO HP HO s | H24 Ễ raVDDO 26 G1049 oma] zy) Ề

Tản { -EVDDO 36 J8 +VDD33 ‹- 120mA > bà Be GL@N TSP 0 0803 5% 0 0803 5%

Mao] FBVDDQ 42 FBVDDQ_43 TÊN PLVDD +|FPAB PLLVDD_ Ri1301 D 10K _0402 5%

+IFPEF PLLVDD R10811 D 10K 0402 5%

IFPEF_PLVDD IFPEF RSET [-ADS 1082 2 1K 0402 5% 9

v Irer Iovpp 2c? #IEPEF IOVDD — R1083{ DJĐ@_ 2 10K 0402 5% °

IFPF_IOVDD

rose CC Security Classification Compal Secret Data Compal Electronics, Inc

SCHEMATIC,MB A7912

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDE Kp D TNumnber v

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS: Custbm 4019ID B MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC -

1

Date:

Trang 26

10015

31 GND 83 GND_183 FA aL] GND 84 GND_ 184 ASE B10) GND_85 GND_ 185 2+

B22 GND_86 GND_1e6 Fats B25] GND_87 GND_187 FS B26) GND_88 GND_ 188 FWA Đai Í GND 89 GND_ 189 F-“18

dt GND 90 GND_ 190 [Z8 BA) GND_91 GND 191 [2E

Ca | GND 92 GND_192 SE C11] GND 92 GND_193 S131 GND 94 GND_194 U4 C127 GND 95 GND_ 195 FAs C7 16ND 92 GND_ 196 XE G25 GND_97 GND_197 Fat Z8 Ï GND sẽ GND_198 Fes GND_99 GND_199 FAH

GND_OPT ols GND_OPT

SCHEMATTIC,MB A7912

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDE! Kp D TNunber v

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custbm 9ID B MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC -

1

Date:

Trang 27

<23,28> DGSA#[7 0] +MEM_VREFO, VREFCA pato Eâ DA12 +MEM VREF1 VEEFCA "= DA3

<23,28> MDA[63 0] —= Mee CMD AY] ao PZ a4 pars -Š DOL4 |2 HA DA‘ Group 1 uPA C DAI1 NEY ao Pz lạ; DOL3 r8 DOL4 |2 nà DAQ xoup ù CMDB 2 Aa

SMA Ad pat7 PH2 TL MbAt4 l SMR Ad pat7 FEZ DAS CMD1O BA A4

R.1084 EMDA2B—Nr | 1! Dal Fag DAZ? CMDAZE 7 § A! D004 Faa DA28 CHDI4 Al AT5

240.0402154 al eerie la a2 voo Fat —<*Đ*22 — 2 | saa vpp CHD18 ODT_H

— t€WDAS — ko] LMDAS CKE/CKEO VDD E2 +15VSDGPU — CWDA3S — to] CMUAŠ CKE/GKEO VDD E2 +1.5VSDGPU CMD2 1 AB A8

+1.5V§DGPU CMDA2 — KIÍ Tomạẹ vppolAl EHDA—kL{Onropo vopoE2i

CMDASD a CSC VDDG €1 ee 2 RAS vane Fa

DIS@ CMDAT3 — 12 | VDDO |-D2 CMDATS dục

VDDO F-Le

<23> CLKAO | | DIS@ ~—JLÏ NG/ODT1 vsso h1 DIS@ ~—ILÏ Nc/opT: vsso B1 aun CMDA ¬ Rivets O 2 5 0402 command Bit |Default Pull-down

@ | Ri 069 ~—LLÏ ciési vssa 42 1090 LU Ncest ssa F2 en bến 2—

Ị 160_0402 1% Ị >—!3]nczoi vsso D8 veeg Pez >—l# ÏNCzo1 vsso D8 yee Tee AND CMDAT9 = R1096 2 2 5 0402 DDR3 CKEx 10k

Tes [es [ xs [es | se [se [se | se | Se [ se gS | gS [ s$ [ eS | se | Se | Se | se [ se

87, sẽ |8", Br, Pes Pes Peg Peg P25 PES Pas Par Par Poe eg Peg Peg Peg Pel PSS Pes Pee Pee

SCHEMATIC,MB A7912

Trang 28

VRAM DDR3 chips (1GB) 64Mx16 DDR3 *8==>1GB

128Mx16 DDR3 *8==>2GB

+MEM,VREF2 VREFCA pato FE pa

<23,27> DQMAI7 0] <p OL CMDA9 na pate FEB D152

<23,27> OMDA[30.0] CUDAI0, 0 = oT ELH Ai DOL4 E2 DA

<23,27> DQSAd[? 0] ae SMAI 43 bats Fri DAS/

<23,27> MDA[63 0] <TD outa Be a7 pauo f-2 pas

EMDAS pa | 48 DQUI Fag DAGO

EMDAZD Ey 49 pau2 Foe BAEZ CMDAZT— Ly A10/AP paus F-2 GAGE CMDA2S N7 § Al! PSUs 22 DA56

= ae Ty Ata pau? Ft BASE

R1099 2S CLKATE & vp Lat

240_0402 1% _0402_ 2 i CMDA18 CKE/CKEO VDD Họ +1.8VSDGPU

S C EMDAIS—— DA30 J3 CSET | BAS VDDO vopa fF-ot G1

Mode D

CMDO CS0_ TL

CMD1 CMD2 ODT L

CMDAS Palas DÓLs [H8 DA43 CMD6 A9 A9

CMDA2D Ta n2 Pave Lae DA54

CMDR M2 Í sa voo PE CMD14 A15 A15

Gs

vss

— DGSAG a7 I Bas

DGSU ves Mt CHD28 A12 A12

SI Nice vsso F-Pt

>—L2# ÏNCzZGi vsso P5

vsso fF vsso FES vsso Frat vsso Ƒ=

5e thuš ff oS f oS 1S hSs 78s pes fre PSs

@F Oa Oa Oa Oa oF oF oF oF @S)

Trang 29

—NR A0 VDD CMDC26 BAL VDD

VDD VDD _GLKGO GLKC0 7 | ox VDD

—— €WDS3 — ko| CMDC3 CKE/CKE0 VDD +1.5VSDGPU

a Bea Kf opTiopTo VDDQ

CMDC3D Ja | SS VDDO CMDGI5 Ka § RAS VDDO

——“"-*>_—n+Ïsuu vss

vss basc#t poset gg J DasL VSS

Trang 30

R02 modify Swap MDC37 and MDC38

<23,29» DQSG[7 0J —= + MEM, VAEFe VREFCA poLo E3 po + MEM, VREF? VREFCA poLo E3 pes aT —

a A18 DQUs Rẻ Z4 EMBếT ——1^13 DQUs Sẻ aS

Doss DOSU VDDo +9 Dosce DOSU VDDo +9 CMD2T AS AS

GSGL@ ey DOMGS——D4 | DU vee [53 DOMCS— D4 Í DỤ vee [53

————————— >~—r| xcopr: vsso Fat Bros 7 “—UrÌNGcoDri vsso Fat CMD29 A10 A10

9

=—= — ———=— —= - Tổ mg Thế Thế TCOA TCOY CO CD amd

oT os Tos Tog, $7 $7, SỊ 5 $L §$ by TL oa Tbe Ton Les Leg Tee Teg Teg

Tiêu đề	Acer Aspire E1 V1 V3 531 571 Compal LA 7912p Rev 02
Trường học	Compal Electronics, Inc.
Chuyên ngành	Engineering
Thể loại	Schematic Document
Năm xuất bản	2011
Thành phố	Taipei

Định dạng
Số trang	60
Dung lượng	1,52 MB