acer 5738 scheme jv50 mv 1 0109 156

1 = TLS cipher suite with confidentiality default0 = Transport Layer Security TLS cipher suite with no confidentiality Cantiga chipset and ICH9M I/O controller Hub strapping configuratio

Trang 1

Mobile CPU

Cantiga

DDR3 800/1066 MHz DDR3

ICH9M

X4 DMI

C-Link0

ODD SATASATAHDD SATA

INT.

KB Touch Pad

BIOS (2MB)

DEBUG LPC LPC BUS

Mini 1 Card Wire LAN PCIe

BCM5764

LAN Giga LAN

TPS2231

MS/MS Pro/xD /MMC/SD

RJ11

AGTL+ CPU I/F DDR Memory I/F INTEGRATED GRAHPICS LVDS, CRT I/F

6 PCIe ports PCI/PCI BRIDGE ACPI 2.0

ETHERNET (10/100/1000MbE) High Definition Audio LPC I/F Serial Peripheral I/F Matrix Storage Technology(DO) Active Managemnet Technology(DO)

Penryn

3

4, 5

6,7,8,9,10,11 16,17

33 27

30 29

TOP GND S

GND BOTTOMPCB STACKUP

38

L1 L2 L3

L5 L6

31

LINE OUT

VGA_CORE 13A

VCC_GFXCORE (7A)

46

INPUTS

DCBATOUT

GFXCOREISL6263A

5V_S5(6A)

42

OUTPUTS

RT9026 DDR_VREF_S3 (1.2A)

RT9018 1D5V_S3 1D1V_S0(2A)

TPS51117 DCBATOUT FBVDD(4A)

44

47

41

VCC_CORE 38A OUTPUTSCPU DC/DC

INPUTS

DCBATOUT

CHARGEROUTPUTS INPUTS

BT+ DCBATOUT ISL88731A

ISL6266A

45

3D3V_AUX_S5 5V_AUX_S5

47

DCBATOUT INPUTSVGA_CORE

OUTPUTS RT8202A

64MbX16X4 512M VRAM

Trang 2

1 = TLS cipher suite with confidentiality (default)

0 = Transport Layer Security (TLS) cipher suite with no confidentiality

Cantiga chipset and ICH9M I/O controller Hub strapping configuration

page 218

Intel Management engine Crypto strapCFG6

1 = Dynamic ODT Enabled

0 = Dynamic ODT Disabled

1= LFP Card Present; PCIE disabledL_DDC_DATA

FSB Dynamic ODT

DMI Lane Reversal

NOTE:

PCIE config2 bit2,

Rising Edge of PWROK

ESI compatible mode is for server platforms only

This signal should not be pulled low for desttopand mobile

This signal has a weak internal pull-up

XOR Chain Entrance/

PCIE Port Config1 bit1,

1= Normal operation(Default):Lane Numbered in order

Allows entrance to XOR Chain testing when TP3pulled low.When TP3 not pulled low at rising edge

of PWROK,sets bit1 of RPC.PC(Config Registers:

offset 224h) This signal has weak internal pull-downPCIE config1 bit0,

GPIO20

Usage/When Sampled

ESI Strap (Server Only)

Comment

CFG[13:12]

0 = Only Digital Display Port

or PCIE is operational (Default)

1 =Digital display Port and PCIe are operting simulataneously via the PEG port

0 =No SDVO Card Present (Default)

1 = SDVO Card Present

DMI Termination Voltage,

The signal is required to be low for desktopapplications and required to be high formobile applications

Signal has weak internal pull-up Sets bit 27

of MPC.LR(Device 28:Function 0:Offset D8)

CFG[2:0]

CFG[4:3]

CFG8CFG[15:14]

CFG5

Pin Name

011 = FSB667FSB Frequency

Select

0 = DMI x2

others = ReservedReserved

(Default)

1 = DMI x4 Strap Description

DMI x2 SelectiTPM Host Interface

Configuration

Sets bit2 of RPC.PC2(Config Registers:Offset 0224h)This signal has a weak internal pull-down

GNT1#/

low and the TPM Disable bit is clear, theIntegrated TPM will be enable

Flash Descriptor

Security Override Strap

PCI Express Lane

Reversal Rising Edge

of PWROK

No Reboot

XOR Chain Entrance

This signal should not be pull low unless using XOR Chain testing

If sampled high, the system is strapped to the

"No Reboot" mode(ICH9 will disable the TCO Timersystem reboot feature) The status is readable via the NO REBOOT bit

ICH9M Functional Strap Definitions

Controllable via Boot BIOS Destination bitGNT0# is MSB, 01-SPI, 10-PCI, 11-LPC

ICH9 EDS 642879 Rev.1.5

ICH9M Integrated Pull-up and Pull-down Resistors

SIGNAL Resistor Type/Value

HDA_BIT_CLK

HDA_RST#

HDA_SDIN[3:0]

HDA_SDOUT HDA_SYNC

PULL-UP 20K PULL-UP 20K

PULL-UP 20K

PULL-UP 15K PULL-UP 20K PULL-UP 20K

PULL-UP 20K

PULL-DOWN 20K

PULL-DOWN 20K PULL-DOWN 20K PULL-DOWN 20K

PULL-DOWN 20K

PULL-DOWN 20K GPIO[49]

0= The iTPM Host Interface is enabled(Note2)

1=The iTPM Host Interface is disalbed(default)

PCIE Graphics Lane

XOR/ALL

1 = Reverse LanesDMI x4 mode[MCH -> ICH]:(3->0,2->1,1->2and0->3)DMI x2 mode[MCH -> ICH]:(3->0,2->1)

0 = Normal operation(Default):

Lane Numbered in Order

Digital Display Port(SDVO/DP/iHDMI)Concurrent with PCIe

1 All strap signals are sampled with respect to the leading edge ofthe (G)MCH Power OK (PWROK) signal

2 iTPM can be disabled by a 'Soft-Strap' option in theFlash-decriptor section of the Firmware This 'Soft-Strap' isactivated only after enabling iTPM via CFG6

Only one of the CFG10/CFG/12/CFG13 straps can be enabled at any time

10 = XOR mode Enabled

01 = ALLZ mode Enabled (Note 3)

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CPU_SEL2_R

GEN_XTAL_INGEN_XTAL_OUT

PCLKCLK5PCLKCLK1

CLK48_ICHPCLK_KBCPCLK_ICHPCLK_FW HCLK_ICH14

CLK48

PCLKCLK3

DREFCLK_1DREFCLK_1#

PCLKCLK0

PCLKCLK0PCLKCLK2

CPU_SEL2_R

CPU_SEL2_RCLK48

CR#_G

DREFSSCLK_1DREFSSCLK_1#

3D3V_S0

CLK_PCIE_SATA12CLK_PCIE_SATA# 12

PCLK_ICH

13

CPU_SEL14,7

PCLK_KBC

35

CLK_CPU_BCLK4CLK_CPU_BCLK# 4

SMBD_ICH15,16,17SMBC_ICH15,16,17

CLK_PW RGD13

CLK_MCH_BCLK6CLK_MCH_BCLK# 6

PM_STPCPU#

13PM_STPPCI#

13

CPU_SEL04,7

CLK_PCIE_NEW 32CLK_PCIE_NEW # 32

CLK_MCH_3GPLL7CLK_MCH_3GPLL# 7

CLK_PCIE_LAN 25CLK_PCIE_LAN# 25

CLK_PCIE_MINI2 33CLK_PCIE_MINI2# 33

CLK_PCIE_ICH 13CLK_PCIE_ICH# 13

PCLK_FW H36,51

CLK_MCH_OE#

7SATACLKREQ#

13

DREFSSCLK# 7DREFSSCLK7

VGA_XIN1 5252

CLK_PCIE_MINI1 33CLK_PCIE_MINI1# 33

CLK48_5158E31

0

667M 200M

1067M 266M

533M CL=20pF±0.2pF

Byte 6, bit 6

0 = SRC7 enabled (default) 1= CR#_F controls SRC8

Byte 6, bit 4

0 = SRC11 enabled (default) 1= CR#_H controls SRC10

Byte 6, bit 5

0 = SRC11# enabled (default) 1= CR#_G controls SRC9

SRCC7/CR#_E SRCT7/CR#_F

Byte 5, bit 7

0 = PCI0 enabled (default)

1= CR#_A enabled Byte 5, bit 6 controls whether CR#_A controls SRC0 or SRC2 pair

Byte 5, bit 6

0 = CR#_A controls SRC0 pair (default),

1= CR#_A controls SRC2 pair

Byte 5, bit 5

0 = PCI1 enabled (default)

1= CR#_B enabled Byte 5, bit 6 controls whether CR#_B controls SRC1 or SRC4 pair

Byte 5, bit 4

0 = CR#_B controls SRC1 pair (default)

1= CR#_B controls SRC4 pair

PCI1/CR#_B

0 = Overclocking of CPU and SRC Allowed

1 = Overclocking of CPU and SRC NOT allowed

PCI2/TME

0 = Pin17 as SRC-1, Pin18 as SRC-1#, Pin13 as DOT96, Pin14 as DOT96#

1 = Pin17 as 27MHz, Pin 18 as 27MHz_SS, Pin13 as SRC-0, Pin14 as SRC-0#

0 = CR#_D controls SRC1 pair (default) 1= CR#_D controls SRC4 pair

SRCC3/CR#_D

SRCC11/CR#_G SRCT11/CR#_H SRCT3/CR#_C

CPU NB

SB DMI NEWCARD

LAN

NB

NB CLK 3G

SB SATA GPU NB

GPU

WLANmodify by RF

DY

RN47SRN10KJ-6-GP

DY

R24910KR2J-3-GP

DY

12

RN44SRN0J-6-GP

UMA

RN44SRN0J-6-GP

UMA

13

DIS

RN42SRN33J-5-GP-U

DIS

13

R25410KR2J-3-GP

UMA

R25410KR2J-3-GP

SRN33J-7-GP

1

3

57

RN48

SRN10KJ-6-GPRN48

SRN10KJ-6-GP135

X5X-14D31818M-35GP

82.30005.891

X5X-14D31818M-35GP

SRCT9 37SRCC9 38

SRCC11/CR#_GSRCT11/CR#_H 3940

SRCC7/CR#_E 50SRCT7/CR#_F 51

CPUC0 60CPUT0 61

UMA

RN76SRN0J-6-GP

UMA

13

C452SC33P50V2JN-3GPC452SC33P50V2JN-3GP

DIS

R26010KR2J-3-GP

DIS

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H_A#23H_A#25H_A#27H_A#29H_A#31

H_A#3H_A#5H_A#7H_A#9H_A#10H_A#12H_A#14H_A#16

H_REQ#0H_REQ#2H_REQ#4

H_A#[35 3]

H_RS#1H_IERR#

H_D#32H_D#34H_D#36H_D#38

H_D#41H_D#43H_D#[63 0]

H_D#44H_D#46

H_D#0H_D#2H_D#4H_D#6H_D#8H_D#10H_D#12H_D#14

H_D#16H_D#18H_D#20H_D#22H_D#24H_D#26H_D#28H_D#30

H_D#48

H_D#51H_D#53H_D#55H_D#57H_D#59H_D#61H_D#63

COMP0COMP2

XDP_TDIXDP_TMS

XDP_TRST#

XDP_TCK

H_THERMDCH_THERMDA

CPU_GTLREF0CPU_PROCHOT#_1

TEST4

TEST1

TEST4

H_A#32H_A#34

H_INIT#

H_CPURST#

XDP_BPM#1XDP_BPM#3

XDP_TCKXDP_TDIXDP_TMSXDP_TRST#

1D05V_S0

3D3V_S0

H_ADS# 6H_BNR# 6

H_DRDY#6H_DBSY#6H_BREQ#06

H_HIT# 6H_HITM# 6H_LOCK#6

H_DSTBN#26H_DSTBP#26H_DINV#26H_D#[63 0] 6

H_DSTBN#36H_DSTBP#36H_DINV#36

H_DSTBN#16H_DSTBP#16H_DINV#16

H_BPRI# 6H_DEFER#6

H_INIT# 12

H_CPURST#6,51H_RS#[2 0] 6

H_TRDY#6

H_THERMDA34

CLK_CPU_BCLK3CLK_CPU_BCLK# 3

H_DPRSTP#7,12,41H_DPSLP#12H_DPW R#6

H_PW RGD12,39,51H_CPUSLP#6

H_FERR#

12

H_THERMDC34PM_THRMTRIP-A#7,12,39

CPU_SEL23,7CPU_SEL03,7CPU_SEL13,7

H_STPCLK#

12

H_PSI# 41CPU_PROCHOT#_R 41

Layout Note:

Comp0, 2 connect with Zo=27.4 ohm, makeComp1, 3 connect with Zo=55 ohm, maketrace length shorter than 0.5" trace length shorter than 0.5"

Layout Note:

"CPU_GTLREF0"

0.5" max length

should connect toPM_THRMTRIP#

without T-ingICH9 and MCH

All place within 2" to CPU

Net "TEST4" as short as possible, make sure "TEST4" routing is reference to GND and away other noisy signals

PH @ page48

Place these TP on button-side, easy to measure.

Close to NBmodify by RF

R8968R2-GPR8968R2-GP

DY

R970R2J-2-GP

D35# V26D36# V23D38# U25

D39# U23D40# Y25

D41# W22

D42# Y23D43# W24D44# W25

D45# AA23D46# AA24D47# AB25

DSTBP2# AA26DSTBN2# Y26

D48# AE24D49# AD24

D52# AB21

D54# AD20

D55# AE22D56# AF23

D57# AC25D58# AE21D59# AD21D61# AD23

DINV3# AC20

DSTBN3# AE25

D51# AB22D50# AA21

D62# AF22

COMP0 R26COMP1 U26

DPRSTP# E5

DPSLP# B5

DPWR# D24PWRGOOD D6SLP# D7

C525SCD1U10V2KX-4GP

DY

C525SCD1U10V2KX-4GP

R3121KR2F-3-GPR3121KR2F-3-GP

C116SC2200P50V2KX-2GP

DY

C116SC2200P50V2KX-2GP

DBSY# E1DRDY# F21

BR0# F1

IERR# D20INIT# B3

LOCK# H4

RS0# F3RS1# F4RS2# G3

TRDY# G2HIT# G6

HITM# E4

BPM0# AD4

BPM1# AD3

BPM2# AD1BPM3# AC4PRDY# AC2

PREQ# AC1TCK AC5TDI AA6

TDO AB3

TMS AB5TRST# AB6DBR# C20

PROCHOT# D21THRMDA A24

THERMTRIP# C7

BCLK0 A22BCLK1 A21

RSVD#D2

D2

RSVD#F6

F6 RSVD#D3D3 RSVD#D22D22

Trang 5

TP_AE26_CPUTP_A2_CPU

TP_A25_CPU

VCC_CORE

1D5V_S01D05V_S0

1D5V_VCCA_S01D05V_S0VCC_CORE

should be of equal length

VCCSENSE and VSSSENSE lines

Layout Note:

Provide a test point (with

no stub) to connect a differential probe between VCCSENSE andVSSSENSE at the locationwhere the two 54.9ohmresistors terminate the

55 ohm transmission line

layout note: "1D5V_VCCA_S0"

GAP-CLOSE-PW R

TP23TPAD14-GP TP23

4 OF 4CPU1D

BGA479-SKT6-GPU7

4 OF 4CPU1D

VSS R2

VSS R5VSS R22

VSS R25

VSS T1VSS T4VSS T23

VSS T26VSS U3VSS U6

VSS U21

VSS U24VSS V2VSS V5

VSS V22VSS V25VSS W1

VSS W4

VSS W23VSS W26

VSS Y3

VSS Y6VSS Y21VSS Y24

VSS AA2VSS AA5VSS AA8

VSS AA11

VSS AA14VSS AA16VSS AA19

VSS AA22VSS AA25VSS AB1

VSS AB4

VSS AB8VSS AB11

VSS AB13

VSS AB16

VSS AB19VSS AB23

VSS AB26VSS AC3VSS AC6VSS AC8

VSS AC11VSS AC14VSS AC16

VSS AC19

VSS AC21VSS AC24

VSS AD2

VSS AD5VSS AD8VSS AD11

VSS AD13

VSS AD16VSS AD19

VSS AD22

VSS AD25VSS AE1VSS AE4

VSS AE8VSS AE11VSS AE14

VSS AE16

VSS AE19VSS AE23

VSS AE26

VSS A2VSS AF6VSS AF8

VSS AF11

VSS AF13VSS AF16

VSS AF19

VSS AF21VSS A25VSS AF25

2nd = 68.00248.061

L18FCM1608KF-1-GP

VCC AC9

VCC AC12VCC AC13VCC AC15

VCC AC17VCC AC18VCC AD7

VCC AD9

VCC AD10VCC AD12VCC AD14

VCC AD15VCC AD17VCC AD18

VCC AE9

VCC AE10VCC AE12

VCC AE13

VCC AE15VCC AE17VCC AE18

VCC AE20VCC AF9VCC AF10

VCC AF12

VCC AF14VCC AF15VCC AF17

VCC AF18VCC AF20VCCP G21

VCCP J6

VCCP J21VCCP K6

VCCP K21

VCCP M6

VCCP M21VCCP N6VCCP N21

VCCP R6VCCP R21

VCCP T6

VCCP T21VCCP V6

VCCP V21

VCCP W21VCCA B26

VCCA C26VID0 AD6

VID6 AE2VID4 AE3

VID2 AE5

VID5 AF3VID3 AF4

Trang 6

H_A#29H_A#31

H_A#26H_A#28

H_A#23H_A#25

H_A#20H_A#22

H_A#17H_A#19

H_A#14H_A#16

H_A#11H_A#13

H_A#8H_A#10

H_A#5H_A#7H_A#3H_A#[35 3]

H_A#33

H_RS#1

H_REQ#1H_REQ#3H_REQ#0

H_REQ#4

H_DSTBN#[3 0]

H_DSTBN#3H_DSTBN#1

H_DSTBP#[3 0]

H_DSTBP#2H_DSTBP#0

H_DSTBP#3H_DSTBP#1

H_DINV#0H_DINV#2H_DINV#[3 0]

H_RCOMPH_SW ING

H_AVREF

H_SW INGH_RCOMP1D05V_S0

4

H_A#[35 3]4

H_BNR# 4H_BREQ#04

H_ADS# 4H_ADSTB#0 4

H_DBSY#4

H_DRDY#4H_HIT# 4H_HITM# 4

CLK_MCH_BCLK3CLK_MCH_BCLK# 3

H_LOCK#4

H_BPRI# 4H_DEFER# 4

Place them near to the chip ( < 0.5")

H_RCOMP routing Trace width and

Spacing use 10 / 20 mil

H_SWING routing Trace width and

Spacing use 10 / 20 mil

H_SWING Resistors and

CANTIGA-GM-GP-U-NF

71.CNTIG.00U

H_A#_10 P16H_A#_11 R16

H_A#_12 N17

H_A#_13 M13H_A#_14 E17

H_A#_15 P17

H_A#_16 F17H_A#_17 G20H_A#_18 B19

H_A#_19 J16H_A#_20 E20H_A#_21 H16

H_A#_22 J20

H_A#_23 L17H_A#_24 A17H_A#_25 B17

H_A#_26 L16H_A#_27 C21H_A#_28 J17

H_A#_29 H20

H_A#_3 A14

H_A#_30 B18H_A#_31 K17

H_A#_4 C15

H_A#_5 F16

H_A#_6 H13H_A#_7 C18H_A#_8 M16

H_A#_9 J13

H_ADS# H12H_ADSTB#_0 B16

H_ADSTB#_1 G17

H_BNR# A9H_BPRI# F11H_BREQ# G12

H_DINV#_3 Y1

H_DPWR# J11H_DRDY# F9

H_DSTBN#_0 L10

H_DSTBN#_1 M7

H_DSTBN#_2 AA5H_DSTBN#_3 AE6H_DSTBP#_0 L9

H_DSTBP#_1 M8H_DSTBP#_2 AA6

H_REQ#_4 B14

H_A#_32 B20

H_A#_33 F21H_A#_34 K21H_A#_35 L20

H_RS#_2 C8

R382100R2F-L1-GP-UR382100R2F-L1-GP-U

Trang 7

PEG_RXN2

PEG_RXN7PEG_RXN4PEG_RXN1

PEG_RXN6PEG_RXN3PEG_RXN0PEG_CMP

PEG_RXP5

PEG_RXP15

PEG_RXP4PEG_RXP1

L_LVBGLIBGLVDS_VREFGMCH_LCDVDD_ONCLK_DDC_EDIDLCTLB_DATALCTLA_CLK

DAT_DDC_EDID

GMCH_DDCDATAGMCH_DDCCLK

CRT_IREFGMCH_VSTV_DACB

CRT_IREFTV_DACA

LIBG

PEG_TXN3_L

PEG_TXN1_L

PEG_TXN2_LPEG_TXN0_L

MCH_TSATN#

PM_EXTTS#0

GFXVR_EN

LCTLB_DATALCTLA_CLK

GMCH_GREEN

GMCH_BL_ONGMCH_LCDVDD_ON

PEG_TXN0

PEG_TXP10PEG_TXP7

PEG_TXP15PEG_TXP12PEG_TXP1

PEG_TXP9PEG_TXP6

PEG_TXP14PEG_TXP3

PEG_TXP11PEG_TXP0

PEG_TXP8PEG_TXP5

PEG_TXP13

PEG_TXP2PEG_TXN14PEG_TXN3

PEG_TXN11PEG_TXN8PEG_TXN5

PEG_TXN13PEG_TXN2

PEG_TXN10PEG_TXN7

PEG_TXN15PEG_TXN4

PEG_TXN12PEG_TXN1

PEG_TXN9PEG_TXN6

PEG_TXP4

PEG_TXN0_L

PEG_TXN11_LPEG_TXN8_LPEG_TXN5_L

PEG_RXN12

PEG_RXP2

PEG_RXP13PEG_RXP10PEG_RXP6

PEG_RXP9PEG_RXP11PEG_RXP0

PEG_TXP0_L

PEG_TXP14_LPEG_TXP3_L

PEG_TXP11_LPEG_TXP8_LPEG_TXP5_L

PEG_TXP12_LPEG_TXP9_LPEG_TXP1_L

PEG_TXP6_L

ACZ_SYNC_RACZ_SDATAOUT_RACZ_BIT_CLKHDA_BCLK

HDA_SDO

HDA_BCLK

ACZ_SDIN3

GMCH_REDGMCH_BLUE

CFG16

1D05V_S03D3V_S0

GMCH_TXBOUT0+

18GMCH_TXBOUT1+

18GMCH_TXBOUT2+

18

18GMCH_TXBOUT1-18GMCH_TXBOUT2-18

GMCH_TXBOUT0-18GMCH_TXBCLK+

GMCH_TXBCLK-18

L_BKLTCTL18

GMCH_LCDVDD_ON18CLK_DDC_EDID18DAT_DDC_EDID18GMCH_BL_ON35

GMCH_TXAOUT0+

18GMCH_TXAOUT1+

18GMCH_TXAOUT2+

18

18GMCH_TXAOUT1-18GMCH_TXAOUT2-18

GMCH_TXAOUT0-18GMCH_TXACLK+

GMCH_TXACLK-18

GMCH_DDCCLK19GMCH_DDCDATA19GMCH_HSYNC19GMCH_VSYNC19

GMCH_GREEN19GMCH_BLUE19

GMCH_RED19

FOR Discrete change RN to 0 ohm (66.R0036.A8L)

FOR Discrete,change to 0 ohm (66.R0036.A8L)

for HDMI port C

DY

R178100KR2F-L1-GP

0R0402-PADR1890R0402-PAD

C759SC2D2U6D3V3MX-1-GPC759SC2D2U6D3V3MX-1-GP

R44280D6R2F-L-GPR442

8

R1830R0402-PADR183

2

R4413K01R2F-3-GPR4413K01R2F-3-GP

SRN0J-10-GP-U

UMA13

SRN10KJ-5-GP13

L_VDD_ENM29LVDS_IBGC44LVDS_VBGB43LVDS_VREFHE37LVDS_VREFLE38LVDSA_CLK#

C41LVDSA_CLKC40

LVDSA_DATA#_0H47LVDSA_DATA#_1E46LVDSA_DATA#_2G40

LVDSA_DATA_1D45LVDSA_DATA_2F40

LVDSB_CLK#

B37LVDSB_CLKA37

LVDSB_DATA#_0A41LVDSB_DATA#_1H38LVDSB_DATA#_2G37

LVDSB_DATA_1G38LVDSB_DATA_2F37

L_BKLT_ENG32

TVA_DACF25TVB_DACH25TVC_DACK25TV_RTNH24

CRT_BLUEE28

CRT_DDC_CLKH32CRT_DDC_DATAJ32

CRT_GREENG28

CRT_HSYNCJ29CRT_TVO_IREFE29

CRT_REDJ28CRT_IRTNG29

CRT_VSYNCL29

LVDSA_DATA_0H48

LVDSB_DATA_0B42

L_BKLT_CTRLL32

TV_DCONSEL_0C31TV_DCONSEL_1E32

LVDSA_DATA#_3A40

LVDSA_DATA_3B40

LVDSB_DATA#_3J37

LVDSB_DATA_3K37

UMA1 2

R44380D6R2F-L-GPR44380D6R2F-L-GP

R38756R2J-4-GPR38756R2J-4-GP

SRN0J-10-GP-U

UMA13

CFG_2P25CFG_0T25CFG_1R25

CFG_20T28

CFG_3P20CFG_4P24CFG_5C25CFG_6N24CFG_7M24CFG_8E21CFG_9C23CFG_10C24CFG_11N21CFG_12P21CFG_13T21CFG_14R20CFG_15M20CFG_16L21CFG_17H21

PM_SYNC#

R29PM_EXT_TS#_0N33PM_EXT_TS#_1P32

PW ROKAT40RSTIN#

AK34RESERVED#AM35AM35

RESERVED#BG23BG23RESERVED#BF23BF23RESERVED#BH18BH18RESERVED#BF18BF18

RESERVED#AH9AH9RESERVED#AH10AH10RESERVED#AH12AH12RESERVED#AH13AH13

RESERVED#M36M36RESERVED#N36N36RESERVED#R33R33RESERVED#T33T33

RESERVED#K12K12

NC#BG48BG48NC#BF48BF48NC#BD48BD48NC#BC48BC48NC#BH47BH47NC#BG47BG47NC#BE47BE47NC#BH46BH46NC#BF46BF46NC#BG45BG45NC#BH44BH44NC#BH43BH43NC#BH6BH6NC#BH5BH5NC#BG4BG4

RESERVED#T24T24

PEG_CLK#PEG_CLKE43F43

NC#BH3BH3

RESERVED#B31B31

NC#BF3BF3NC#BH2BH2NC#BG2BG2NC#BE2BE2NC#BG1BG1NC#BF1BF1NC#BD1BD1NC#BC1BC1NC#F1F1

RESERVED#M1M1

RN84SRN0J-10-GP-U

SRN0J-10-GP-U

UMA13

SRN0J-10-GP-U

UMA

13

DY

C324SC100P50V2JN-3GP

Trang 8

M_A_DQ40M_A_DQ37M_A_DQ35

M_A_DQ59M_A_DQ54

M_A_DQ51M_A_DQ48

M_A_DQ7M_A_DQ5

M_A_DQ12M_A_DQ10

M_A_DQ15

M_A_DQ30

M_A_DQ18M_A_DQ16

M_A_DQ28M_A_DQ17

M_A_DQ26

M_A_DQ31M_A_DQ29

M_A_DQ46M_A_DQ42M_A_DQ38M_A_DQ32

M_A_DQ45M_A_DQ33

M_A_DQ43M_A_DQ41

M_A_DQS#3M_A_DQS#0

M_A_DQS#6M_A_DQS#4M_A_DQS#1

M_A_DQS#5M_A_DQS#7M_A_A0

M_A_A6M_A_A3M_A_A5M_A_A7

M_A_A1

M_A_A4

M_A_A10M_A_A8

M_A_A13M_A_A11M_A_A9

M_A_DQS5M_A_DQS7

M_A_DQS2M_A_DQS4M_A_DQS0

M_A_DQS6

M_A_A14

M_B_DQ0M_B_DQ2M_B_DQ4M_B_DQ6M_B_DQ8M_B_DQ10

M_B_DQ15M_B_DQ13

M_B_DQ16M_B_DQ18

M_B_DQ23M_B_DQ21

M_B_DQ28M_B_DQ26

M_B_DQ29M_B_DQ25

M_B_DQ31

M_B_DQ24

M_B_DQ27

M_B_DQ30M_B_DQ32M_B_DQ34

M_B_DQ39M_B_DQ37

M_B_DQ44M_B_DQ42

M_B_DQ45M_B_DQ41

M_B_DQ47

M_B_DQ40

M_B_DQ43

M_B_DQ55M_B_DQ53

M_B_DQ60M_B_DQ58

M_B_DQ61M_B_DQ57

M_B_DQS[7 0]

M_B_DQS0M_B_DQS2M_B_DQS4M_B_DQS6

M_B_A12M_B_A9M_B_A11M_B_A13

M_B_A8M_B_A10

M_B_A[14 0]

M_B_A0M_B_A2M_B_A4M_B_A6

M_B_DM[7 0]

M_B_DM0M_B_DM2M_B_DM4M_B_DM6

M_B_A14

M_A_DQ[63 0]

16

M_A_BS#0 16M_A_BS#2 16

M_A_CAS# 16

M_A_DQS#[7 0]16M_A_DQS[7 0] 16

M_A_A[14 0]16

M_A_DM[7 0]16

M_A_RAS# 16M_A_W E# 16

M_B_DQ[63 0]

17

M_B_BS#0 17M_B_BS#2 17

M_B_CAS# 17M_B_W E# 17

M_B_DQS#[7 0] 17M_B_DQS[7 0] 17

M_B_A[14 0]17M_B_DM[7 0]17

SB_CAS# BG16

SB_DM_0 AM47SB_DM_1 AY47

SB_DM_2 BD40

SB_DM_3 BF35SB_DM_4 BG11SB_DM_5 BA3

SB_DM_6 AP1SB_DM_7 AK2SB_DQS_0 AL47

SB_DQS_1 AV48SB_DQS_2 BG41SB_DQS_3 BG37

SB_DQS_4 BH9SB_DQS_5 BB2SB_DQS_6 AU1

SB_DQS_7 AN6

SB_DQS#_0 AL46SB_DQS#_1 AV47

SB_DQS#_2 BH41

SB_DQS#_3 BH37SB_DQS#_4 BG9SB_DQS#_5 BC2

SB_DQS#_6 AT2SB_DQS#_7 AN5SB_MA_0 AV17

SB_MA_1 BA25

SB_MA_10 BB16

SB_MA_11 AW33

SB_MA_12 AY33SB_MA_13 BH15

SB_MA_2 BC25SB_MA_3 AU25

SB_MA_4 AW25SB_MA_5 BB28SB_MA_6 AU28

SB_MA_7 AW28

SB_MA_8 AT33SB_MA_9 BD33

SB_MA_14 AU33

SB_RAS# AU17SB_WE# BF14

SA_CAS# BD20

SA_DM_0 AM37

SA_DM_1 AT41SA_DM_2 AY41

SA_DM_3 AU39

SA_DM_4 BB12SA_DM_5 AY6SA_DM_6 AT7

SA_DQS_0 AJ44

SA_DQS_1 AT44

SA_DQS_2 BA43SA_DQS_3 BC37SA_DQS_4 AW12

SA_DQS_5 BC8SA_DQS_6 AU8SA_DQS_7 AM7

SA_DM_7 AJ5

SA_DQS#_0 AJ43

SA_DQS#_1 AT43SA_DQS#_2 BA44

SA_DQS#_3 BD37

SA_DQS#_4 AY12SA_DQS#_5 BD8SA_DQS#_6 AU9

SA_DQS#_7 AM8SA_MA_0 BA21

SA_MA_5 BA24SA_MA_6 BD24SA_MA_7 BG27

Trang 9

U60(ISL6263ACRZ-T-GP) place near Cantiga

place near Cantiga

VCC_SMBF31

VCC_SM

AW 29

VCC_SMBD32

VCC_SMBC32

VCC_SMBB32

VCC_SMBA32

VCC_SM

AW 32

VCC_SMAV32

VCC_SMAU32

VCC_SMAT32

VCC_SMAR32

VCC_SMAP32

VCC_SMAN32

VCC_SMBH31

VCC_SMBG31

VCC_SMAN33

VCC_SMBG30

VCC_SMBH29

VCC_SMBG29

VCC_SMBF29

VCC_SMBD29

VCC_SMBC29

VCC_SMBB29

VCC_SMBA29

VCC_SMAY29

VCC_SMBH32

VCC_SMAV29

VCC_SMAU29

VCC_SMAT29

VCC_SMAR29

VCC_SMBG32

VCC_SMBF32

VCC_SMAP33

VCC_AXGY26VCC_AXGAE25

VCC_AXGAB25

VCC_AXGAA25

VCC_AXGAE24

VCC_AXGAC24

VCC_AXGAA24

VCC_AXGY24VCC_AXGAE23

VCC_AXGAC23

VCC_AXGAB23

VCC_AXGAA23

VCC_AXGAJ21

VCC_AXGAG21

VCC_AXGAE21

VCC_AXGAC21

VCC_AXGAA21

VCC_AXGY21VCC_AXGAH20

VCC_AXGAF20

VCC_AXGAE20

VCC_AXGAC20

VCC_AXGAB20

VCC_AXGAA20

VCC_AXGT17VCC_AXGAM15

VCC_AXGAL15

VCC_AXGAJ15

VCC_AXGAH15

VCC_AXGAF15

VCC_AXGAB15

VCC_AXGAG15

VCC_AXGAA15

VCC_AXGY15VCC_AXGV15VCC_AXGU15VCC_AXGAN14

VCC_AXGAM14

VCC_AXGU14VCC_AXGT14

VCC_AXG_SENSEAJ14

VSS_AXG_SENSEAH14

VCC_SM/NCBB24

VCC_SM/NCBD16

VCC_SM/NCBB21

VCC_AXGAE15

W 33VCCV33VCCU33VCCAH28VCCAF28VCCAC28VCCAA28VCCAJ26VCCAG26VCCAE26VCCAC26VCCAH25VCCAG25VCCAF25VCCAG24VCCAJ23VCCAH23VCCAF23VCCT32

Trang 10

M_VCCA_DAC_BG3D3V_CRTDAC_S0

M_VCCA_HPLLM_VCCA_MPLL

M_VCCA_DPLLAM_VCCA_DPLLBM_VCCA_DPLLA

322mA

73mA

5mA

13.2mA 65mA

65mA

Imax = 300 mA

60.3mA 58.7mA

CANTIGA-GM-GP-U-NF

71.CNTIG.00U

VTT V3VTT U3VTT V2

VTT T8

VTT U7VTT T7

VCCD_HPLL

AF1

VTT U13

VTT T13VTT T12

VTT U11

VTT T11VTT U10VTT T10

VTT U9VTT T9VTT U8

VCC_HV A35

VCC_DMI AH47VCC_DMI AG47

R4480R0603-PADR4480R0603-PAD12

U12

G1117-18T63UF-GP

74.G1117.B3C UMA

VIN 3GND 1VOUT 2

DY

R3790R2J-2-GP

DY

R1670R2J-2-GP

DY

R3900R2J-2-GP

DY

R3900R2J-2-GP

21

C704SCD1U10V2KX-4GPC704SCD1U10V2KX-4GP

21

DY

R1680R2J-2-GP

DY

R4000R2J-2-GP

DY

R3980R2J-2-GP

R3780R0603-PADR3780R0603-PAD12

Trang 11

TP190 TPAD14-GP1

TP188 TPAD14-GP1

G9 VSSAD9 VSS

AM9 VSSAN9 VSSBC9

VSS B8VSS AY7VSS AU7

VSS AN7

VSS AJ7VSS AE7VSS AA7

VSS N7VSS J7VSS BG6

VSS BD6

VSS AV6VSS AT6

VSS

AC15

VSS AM6

VSS M6VSS C6VSS BA5

VSS AH5VSS AD5VSS Y5

VSS L5

VSS J5VSS H5VSS F5

VSS BE4VSS BC3

VSS_NCTF AM29

VSS_NCTF AF29VSS_NCTF AB29VSS_NCTF U26

VSS_NCTF U23

VSS_NCTF AL20VSS_NCTF V20

VSS_NCTF AC19

VSS_NCTF AL17VSS_NCTF AJ17VSS_NCTF AA17

VSS_NCTF U17

NCTF_VSS_SCB#BH48 BH48

NCTF_VSS_SCB#BH1 BH1NCTF_VSS_SCB#A48 A48

NCTF_VSS_SCB#C1 C1

NCTF_VSS_SCB#A3 A3NC#E1 E1

NC#D2 D2

NC#C3 C3NC#B4 B4

NC#A5 A5

NC#A6 A6NC#A43 A43NC#A44 A44

NC#B45 B45NC#C46 C46NC#D47 D47

NC#B47 B47

NC#A46 A46NC#F48 F48

NC#E48 E48

NC#C48 C48NC#B48 B48

VSS R3

VSS P3

VSS BA2

VSS AR2VSS AU2VSS AP2

VSS F3VSS AW2

VSS AE2

VSS AF2VSS AH2VSS AJ2

VSS AD2VSS AC2VSS Y2

VSS M2

VSS K2VSS AM1

VSS

L12

TP202 TPAD14-GP1

TP187 TPAD14-GP1

VSS

9 OF 10NB1I

CANTIGA-GM-GP-U-NF

71.CNTIG.00U

VSS

9 OF 10NB1I

VSS L36VSS J36VSS F36

VSS B36

VSS AH35VSS AA35VSS Y35

VSS U35VSS T35VSS BF34

VSS AM34

VSS AJ34VSS AF34

VSS AE34

VSS W34VSS B34VSS A34

VSS BG33VSS BC33VSS BA33

VSS AV33

VSS AR33VSS AL33VSS AH33

VSS AB33VSS P33VSS L33

VSS H33

VSS N32VSS K32

VSS F32

VSS C32VSS A31VSS AN29

VSS T29VSS N29VSS K29

VSS H29

VSS F29VSS A29VSS BG28

VSS BD28VSS BA28VSS AV28

VSS AT28

VSS AR28VSS AJ28

VSS AG28

VSS AE28

VSS AB28VSS Y28

VSS P28VSS K28VSS H28VSS F28

VSS C28VSS BF26VSS AH26

VSS AF26

VSS AB26VSS AA26

VSS C26

VSS B26VSS BH25VSS BD25

VSS BB25

VSS AV25VSS AR25

VSS AJ25

VSS AC25VSS Y25VSS N25

VSS L25VSS J25VSS G25

VSS AB24VSS L24

VSS

AY46

VSS G24

VSS E24VSS AG23

VSS B23

VSS AY24

VSS AJ24VSS AF24

VSS R24

VSS K24VSS J24VSS F24VSS BH23

VSS Y23VSS

AK15

VSS AD12

VSS AJ6

Trang 12

RTC_RST#

H_PW RGDH_DPRSTP#

HDA_DOCK_RST#

GLAN_COMPHDMI_EN

ACZ_RST#_R

ACZ_SDATAOUT_RACZ_BIT_CLK

ACZ_BIT_CLKACZ_RST#_RACZ_SDATAOUT_R

ACZ_SYNC_RACZ_SDATAOUT_RACZ_BIT_CLK

1D05V_S0 3D3V_S0

RTC_AUX_S53D3V_AUX_S5

SATA_TXN122SATA_TXP122SATA_RXN122SATA_RXP122

MEDIA_LED#

38

SATA_TXN021SATA_TXP021SATA_RXN021SATA_RXP021

KBRCIN#35

LPC_LFRAME#35,36,51

H_IGNNE#4H_INIT#4H_INTR4

H_STPCLK# 4H_NMI 4H_SMI# 4

KA20GATE 35

H_FERR#4

H_A20M# 4H_DPRSTP#4,7,41H_DPSLP#4

H_PW RGD4,39,51

PM_THRMTRIP-A#4,7,39

ACZ_SDIN252ACZ_SDATAIN027ACZ_SDATAIN130

ACZ_BTCLK_MDC30ACZ_SYNC_MDC30ACZ_RST#_MDC30ACZ_SDATAOUT_MDC30

ACZ_SYNC_AUDIO27ACZ_SDATAOUT_AUDIO27

ACZ_RST#_AUDIO27ACZ_BITCLK_AUDIO27

ACZ_BITCLK_GPU52ACZ_SYNC_GPU52ACZ_RST#_GPU52ACZ_SDATAOUT_GPU52

ACZ_RST#_R7ACZ_BIT_CLK7ACZ_SYNC_R7

ACZ_SDATAOUT_R7ACZ_SDIN37

LPC_LAD035,36,51LPC_LAD135,36,51LPC_LAD235,36,51LPC_LAD335,36,51

HDD ODD

Place within 500 mils ofICH9 ball

GLAN_COMP place within 500 mil of ICH9M

close to SB1

modify by RF

modify by RF modify by RF

SRN33J-4-GP

1357

BAS40CW -GP123

DY

R41356R2J-4-GP

TP204TPAD14-GP TP204

DY

RN70SRN10KJ-5-GP

DY

R42456R2J-4-GP

DY

TP116 TPAD14-GP1

R41156R2J-4-GPR41156R2J-4-GP

R2301MR2J-1-GPR2301MR2J-1-GP

C386

SC7P50V2DN-2GPC386

SRN56J-4-GP13

TP144 TPAD14-GP1

SATARBIAS AH7

FWH0/LAD0 K5

FWH1/LAD1 K4

FWH2/LAD2 L6FWH3/LAD3 K2

LDRQ0# J3

LDRQ1#/GPIO23 J1

FWH4/LFRAME# K3

A20GATE N7A20M# AJ27

DPRSTP# AJ25DPSLP# AE23

FERR# AJ26CPUPWRGD AD22

IGNNE# AF25INIT# AE22INTR AG25RCIN# L3

SMI# AF24NMI AF23

STPCLK# AH27THRMTRIP# AG26

SATA5TXN AE10SATA5TXP AF10

SRTCRST#

F20

Q14MMBT3904-4-GP

84.T3904.C11

DY

Q14MMBT3904-4-GP

82.30001.841

X4X-32D768KHZ-40GPU

DY

C381SC47P50V2JN-3GP

SC7P50V2DN-2GP

RN68

SRN33J-4-GPRN68

SRN33J-4-GP

1357

TP200 TPAD14-GP1

Trang 13

SATA0GPICH_GPIO36

SMB_LINK_ALERT#

SMB_ALERT#

RSMRST#_SB

SUSPWRACKICH_GPIO24AC_PRESENTICH_GPIO9FP_ID

TXP5

PM_SUS_STAT#

TXP1

AC_PRESENTSATACLKREQ#

PCI_REQ#2PCI_REQ#0

USBPP924USBPN924

RSMRST#_KBC35

CL_DATA07CL_CLK07CLK_PWRGD3

PM_SUS_CLK34

PM_PWRBTN#35,51PM_DPRSLPVR 7,41PM_SLP_S4#32,35,39,43,44

CLK_ICH143CLK48_ICH3

PM_SLP_S3#32,34,35,39,43,46

PWROK 7,34PM_STPPCI#

3

SMB_CLK15,25,32,33

PM_SYNC#

7

VGATE_PWRGD34,41

SMB_DATA15,25,32,33

PM_STPCPU#

3

INT_SERIRQ35THRM#

34PM_CLKRUN#

35PCIE_WAKE#

25,32

ECSCI#_135

CLK_PCIE_ICH# 3CLK_PCIE_ICH 3

DMI_RXN37DMI_RXP37

DMI_RXN27DMI_RXP27

DMI_RXN17DMI_RXP17

DMI_RXN07DMI_RXP07DMI_TXN07DMI_TXP07

DMI_TXN17DMI_TXP17

DMI_TXN27DMI_TXP27

DMI_TXN37DMI_TXP37

USBPN024USBPP024

USB_OC#0

24

USBPP1033USBPN1033

USBPN224,51USBPP224,51

EC_TMR35

USBPP1131USBPN1131

USBPN333USBPP333

USBPN418USBPP418

CCD Pair

4 USB

5

0 2 1 Device

MINIC2

6 7 8

9 USB1

New Card

0 1 1 1A16 swap override strap

BOOT BIOS Strap

PCI_GNT#0

PCI_GNT#3 low = A16 swap override enable high = default

LPC(Default) PCI

GPIO49 should be pulled down toGND only when using Teenah Whenusing Cantiga, this ball should

be left as No Connect

10 11 Finger Print MINI1

PCI_GNT#0 and SPI_CS1#

have weak internal Pull up

MINICARD2

SB 1202

R2160R0402-PADR2160R0402-PAD

PCI

Interrupt I/F

2 OF 6SB1B

TP153 TPAD14-GP1

DMI3TXP AC28

DMI_CLKN T26

DMI_CLKP T25

DMI_ZCOMP AF29DMI_IRCOMPAF28

SRN10KJ-5-GP

13

RP3

SRN8K2J-2-GP-URP3

SRN8K2J-2-GP-U

13

810

CL_DATA0 F22

CL_DATA1 C19

CL_VREF0C25

CL_VREF1A19CL_RST0# F21

GPIO10/SUS_PWR_ACK C18

GPIO9/WOL_ENC20

GPIO14/AC_PRESENT C11GPIO24/MEM_LED A16

SRN10KJ-6-GP1357

R224100KR2J-1-GPR224100KR2J-1-GP

TP148 TPAD14-GP1

RP4

SRN8K2J-2-GP-URP4

SRN8K2J-2-GP-U

13

810

12

RP2

SRN8K2J-2-GP-URP2

SRN8K2J-2-GP-U

13

810

TP206 TPAD14-GP1

D8BAS16-1-GP

83.00016.B11

D8BAS16-1-GP

83.00016.B11

1

23

R2220R2J-2-GP

DY

R2220R2J-2-GP

DY

RN40SRN10KJ-5-GPRN40SRN10KJ-5-GP

R2263K24R2F-GPR2263K24R2F-GP

TP207 TPAD14-GP1

SRN10KJ-6-GP

1357RP1

SRN10KJ-L3-GPRP1

SRN10KJ-L3-GP

146810

R227453R2F-1-GPR227453R2F-1-GP

Trang 14

VCCSUS1D5V_INT_ICHTP_VCCSUS1D05V_ICH_1

VCCCL1D05V_INT_ICH

VCCLAN_1D05V_INT_ICH

VCCCL1D5V_INT_ICHV5REF_S5

3D3V_S0

5V_S53D3V_S5

5V_S0

3D3V_S01D5V_S0

1D5V_S51D5V_S01D5V_S0

USBPLL=11mA 1.64A

Place near ICH9MLayout Note:

68.1R220.10D

L9IND-1D2UH-10-GP

L8IND-1D2UH-10-GP

68.1R220.10D

L8IND-1D2UH-10-GP

68.1R220.10D

C713SC4D7U6D3V3KX-GPC713SC4D7U6D3V3KX-GP

DY

C707SC4D7U6D3V3KX-GP

2

R2190R0603-PADR2190R0603-PAD

VCC1_05 F15VCC1_05 L11VCC1_05 L12

VCC1_05 L14

VCC1_05 L16VCC1_05 L17VCC1_05 L18

VCC1_05 M11VCC1_05 M18VCC1_05 P11

VCC1_05 P18

VCC1_05 T11VCC1_05 T18

V_CPU_IO AB23

V_CPU_IO AC23

VCC3_3 F9VCC3_3 G3

VCC3_3 G6

VCC3_3 J2VCC3_3 J7

VCCSUS3_3 T1VCCSUS3_3 T2VCCSUS3_3 T3

VCCSUS3_3 T4VCCSUS3_3 T5VCCSUS3_3 T6

VCCSUS3_3 U6

VCCSUS3_3 U7VCCSUS3_3 V6

VCCSUS3_3 V7

VCCSUS3_3 W6VCCSUS3_3 W7

VCC1_5_A

AG10

VCCSUS1_05 AC8VCCSUS1_05 F17

VCCDMI Y23VCCDMI W23

VCCCL1_05 G22

VCCCL3_3 B24VCCCL3_3 A24VCCCL1_5 G23

VCC1_5_A

AC9

VCC1_5_A

AJ10 VCC1_5_AAH10 VCC1_5_AAG11

Trang 15

TP_A29TP_A2

TP_AJ28TP_AH1TP_AJ1

3D3V_S03D3V_S5 3D3V_S0

SMBC_ICH3,16,17

SMBD_ICH3,16,17

SMB_CLK13,25,32,33

SMB_DATA13,25,32,33

TP121 TPAD14-GP1

TP152 TPAD14-GP1

TP118 TPAD14-GP1

TP149 TPAD14-GP1

TP130 TPAD14-GP1

56

VSS AC22VSS K28VSS K29

VSS L13

VSS L15VSS L2VSS L26

VSS L27VSS L5VSS L7

VSS M12

VSS M13VSS M14

VSS M15

VSS M16VSS M17VSS M23

VSS M28VSS M29VSS N11

VSS N12

VSS N13VSS N14VSS N15

VSS N16VSS N17VSS N18

VSS N26

VSS N27VSS P12

VSS P13

VSS P14VSS P15VSS P16

VSS P17VSS P2VSS P23

VSS P28

VSS P29VSS P4VSS P7

VSS R11VSS R12VSS R13

VSS R14

VSS R15VSS R16

VSS R17

VSS R18

VSS R28VSS T12

VSS T13VSS T14VSS T15VSS T16

VSS T17VSS T23VSS U12

VSS U13VSS U14

VSS U15

VSS U16VSS U17VSS AD23

VSS U26

VSS U27VSS U3

NCTF_VSS#A1 A1NCTF_VSS#A2 A2

NCTF_VSS#A28 A28NCTF_VSS#A29 A29

NCTF_VSS#AH1 AH1

NCTF_VSS#AH29 AH29

NCTF_VSS#AJ1 AJ1

NCTF_VSS#AJ2 AJ2NCTF_VSS#AJ28 AJ28

VSS V28

VSS

G21

VSS V29VSS V4

VSS V5

VSS W26VSS W27

VSS W3

VSS Y1VSS Y28VSS Y29

VSS Y4

VSS Y5VSS AG28

VSS AH6

VSS AF2VSS B26

VSS B25

TP120 TPAD14-GP1

TP129 TPAD14-GP1

TP150 TPAD14-GP1

TP119 TPAD14-GP1

TP147 TPAD14-GP1

Trang 16

M_A_A14M_A_A1

M_A_DQS#5M_A_DQ24

M_A_DQS5M_A_DQS#7

M_A_DQ51M_A_DQ40

M_A_DQ9M_A_DQ4M_A_A11

M_A_DQ62

M_A_DQ56M_A_DQ54M_A_DQ49M_A_DQ45M_A_DQ38

M_A_DQ21M_A_DQ16

M_A_A5M_A_A0

M_A_DQS#4M_A_DQ60

M_A_DQS7M_A_DQS4M_A_DQS#6M_A_DQS#1M_A_DQ39M_A_DQ3

M_A_DQ61

M_A_DQ28

M_A_DQ53M_A_DQ48M_A_DQ44M_A_DQ37

M_A_DQ22M_A_DQ14M_A_DQ8M_A_DQ1M_A_A8

M_A_DQS3M_A_DQS#3M_A_DQ59M_A_DQ33M_A_DQ0

M_A_DQS#0

M_A_DQ41

M_A_DQ26M_A_DQ20

M_A_DQ27

M_A_DQ47M_A_DQ36

M_A_DQS2M_A_DQS#2M_A_DQ58

M_A_DQ18

M_A_A13M_A_A10

M_A_DQ63

M_A_DQ31M_A_DQ25M_A_DQ19M_A_A3

M_A_DQS6M_A_DQS0M_A_DQ52

M_A_A12M_A_A9M_A_A2

M_A_DQ46M_A_DQ43M_A_DQ35M_A_DQ30M_A_DQ6M_A_A6

SMBC_ICHM_A_DM5M_A_DM3

M_A_DM7M_A_DM1

M_A_DM6M_A_DM0

M_A_DQ[63 0]

8

M_A_DM[7 0]8

PM_EXTTS#0 7,17SMBD_ICH3,15,17SMBC_ICH3,15,17

DDR3_DRAMRST#

7,17

M_ODT07M_ODT17

M_A_RAS# 8M_A_CAS# 8M_A_W E# 8

M_CS0# 7

M_CKE0 7

M_CLK_DDR17M_CLK_DDR#17

M_CLK_DDR07M_CLK_DDR#07

Layout Note ： Near Pin 126

CAS# 115CS0# 114

CS1# 121

CKE0 73

CKE1 74

CK0 101CK0# 103

CK1 102CK1# 104

DM0 11DM1 28DM2 46

DM3 63DM4 136DM5 153

DM6 170

DM7 187SDA 200

SCL 202

VDDSPD 199SA0 197

VDD5 87

VDD6 88VDD7 93

VDD8 94

VDD9 99VDD10 100

VDD13 111VDD14 112

VSS 14

VSS 19VSS 20VSS 25

VSS 26VSS 31VSS 32

VSS 37

VSS 38VSS 43

VSS 44

VSS 48VSS 49VSS 54

VSS 55

VSS 60VSS 61

VDD1 75

VSS 65

VSS 66VSS 71VSS 72

VSS 133VSS 138VSS 139

VSS 144

VSS 145

VSS 151

VSS 150VSS 155

VSS 172

VSS 179VSS 178

VSS 185VSS 184

VSS 189VSS 190

VSS 195

VSS 196RESET#

Trang 17

M_B_A11M_B_A6M_B_A3

M_B_A12M_B_A9

M_B_DQS6M_B_DQS3

M_B_DQ0

M_B_DQ8M_B_DQ3

M_B_DQ10M_B_DQ1

M_B_DQ9

M_B_DQ11M_B_DQ5

M_B_DQ19M_B_DQ14

M_B_DQ28M_B_DQ18

M_B_DQ27

M_B_DQ15

M_B_DQ23M_B_DQ17

M_B_DQ31

M_B_DQ13

M_B_DQ21M_B_DQ12

M_B_DQ20

M_B_DQ35

M_B_DQ46M_B_DQ44

M_B_DQ24

M_B_DQ38M_B_DQ32

M_B_DQ43M_B_DQ39

M_B_DQ47

M_B_DQ34M_B_DQ26

M_B_DQ33

M_B_DQ53

M_B_DQ25

M_B_DQ37M_B_DQ29

M_B_DQ36

M_B_DQ45

M_B_DQ52M_B_DQ40

M_B_DQ60M_B_DQ50

M_B_DQ59

M_B_DQ42

M_B_DQ55M_B_DQ49

M_B_DQS#4M_B_DQ7

M_B_DQS#2

M_B_DQS#7M_B_DQS#3

M_B_DQS#6M_B_DQS#0

M_B_DQS#5M_B_DQS#1

M_B_A15

M_B_DM0

M_B_DM7M_B_DM5M_B_DM3

DDR3_DRAMRST#

7,16

M_B_BS#28

M_B_RAS# 8M_B_W E# 8M_B_CAS# 8M_CS2# 7

M_CKE2 7

M_CLK_DDR37M_CLK_DDR27

M_CLK_DDR#37M_CLK_DDR#27

CAS# 115CS0# 114

CS1# 121

CKE0 73CKE1 74

CK0 101CK0# 103

CK1 102CK1# 104

DM0 11DM1 28DM2 46

DM3 63DM4 136DM5 153

DM6 170

DM7 187SDA 200

SCL 202

VDDSPD 199SA0 197

VDD3 81VDD4 82

VDD5 87

VDD6 88VDD7 93

VDD8 94

VDD9 99VDD10 100

VDD13 111VDD14 112

VSS 14

VSS 19VSS 20VSS 25

VSS 26

VSS 31VSS 32

VSS 37

VSS 38VSS 43VSS 44

VSS 48VSS 49VSS 54

VSS 55

VSS 60VSS 61

VDD1 75

VSS 65

VSS 66VSS 71VSS 72

VSS 133

VSS 145VSS 151VSS 150VSS 155

VSS 156VSS 161

VSS 162

VSS 167

VSS 168VSS 173

VSS 172

VSS 179VSS 178

VSS 185VSS 184

VSS 189VSS 190

VSS 195

VSS 196RESET#

30

EVENT# 198

VSS 205VSS 206

R24210KR2J-3-GPR24210KR2J-3-GP12

Trang 18

LCD_EDID_DATLCD_EDID_CLK

BRIGHTNESS_CNBLON_OUT_1

CCD_PW R

BLON_OUT_1BRIGHTNESS_CNDCBATOUT_LCD1

LCD_TXBCLK+

LCD_TXBOUT2+

LCD_TXBCLK-LCD_TXBOUT1+

LCD_TXBOUT2-LCD_TXBOUT0+

LCD_TXBOUT0-LCD_TXAOUT2-

LCD_TXBOUT1-

LCD_TXBCLK-LCD_TXACLK+

LCD_TXBCLK+

LCD_TXACLK-LCD_TXAOUT1+

LCD_TXAOUT0+

LCD_TXAOUT1-

LCD_TXAOUT0-LCD_TXACLK+

LCD_TXAOUT2+

LCD_TXBOUT0-

LCD_TXBOUT1-

LCD_TXAOUT2-LCD_TXAOUT1-

LCD_TXBCLK-LCD_TXBCLK+

LCD_TXBOUT2+

BRIGHTNESS35BLON_OUT 35L_BKLTCTL 7

CLK_DDC_EDID7DAT_DDC_EDID7

GMCH_TXBOUT0+ 7GMCH_TXBOUT1+ 7GMCH_TXBOUT0- 7GMCH_TXBOUT1- 7

GMCH_TXAOUT2+ 7GMCH_TXACLK- 7GMCH_TXACLK+ 7GMCH_TXAOUT2- 7

LCDVDD_ON56

GMCH_LCDVDD_ON7

LCD_CB_SEL35

INT_MIC1

27,51

GPU_TXACLK- 55GPU_TXACLK+ 55GPU_TXAOUT2- 55GPU_TXAOUT2+ 55

GPU_TXBOUT0- 55GPU_TXBOUT0+ 55GPU_TXBOUT1- 55GPU_TXBOUT1+ 55

GPU_TXAOUT1+ 55GPU_TXAOUT1- 55GPU_TXAOUT0+ 55GPU_TXAOUT0- 55

GMCH_TXAOUT1- 7GMCH_TXAOUT1+ 7GMCH_TXAOUT0- 7GMCH_TXAOUT0+ 7

GMCH_TXBCLK+ 7GMCH_TXBCLK- 7GMCH_TXBOUT2- 7GMCH_TXBOUT2+ 7

GPU_TXBCLK- 55GPU_TXBCLK+ 55GPU_TXBOUT2- 55GPU_TXBOUT2+ 55

DBC_EN35USBPN413USBPP413

F2

FUSE-1A6V-2-GP

2nd = 69.50007.981 69.50007.721

F2

FUSE-1A6V-2-GP

2nd = 69.50007.981 69.50007.721

R133R2J-2-GP

33R2J-2-GP

DIS

12

UMA R333R2J-2-GP

UMA

12

R510KR2J-3-GP

DIS

R510KR2J-3-GP

42

246810121416182022242628303234363840

Trang 19

VSYNC_1

CRT_HSYNC1

CRT_VSYNC1HSYNC_1

DAT_DDC1_5

CLK_DDC1_5DAT_DDC1_5_Q

CRT_IN#_RCLK_DDC1_5

CRT_VSYNC1DAT_DDC1_5CRT_HSYNC1

CRT_HSYNC1

CLK_DDC1_5DAT_DDC1_5

35

CRT_HSYNC54CRT_VSYNC54

CRT_DDCDATA54CRT_DDCCLK54

GMCH_VSYNC7GMCH_HSYNC7

GMCH_DDCDATA7GMCH_DDCCLK7

CRT I/F & CONNECTOR

Layout Note:

* Must be a ground return path between this ground and the ground on

the VGA connector.

Pi-filter & 150 Ohm pull-down resistors should be as close as to CRT

CONN RGB will hit 75 Ohm first, pi-filter, then CRT CONN.

Layout Note:

close to the CRT-out

connector

Place these resistors

Ferrite bead impedance: 10 ohm@100MHz

Hsync & Vsync level shift

DDC_CLK & DATA level shift

470R2J-2-GP12

L5FCB1608CF-GP

68.00230.021

L5FCB1608CF-GP

68.00230.021

C98SC100P50V2JN-3GP

U18BTSAHCT125PW -GPU18BTSAHCT125PW -GP

DIS

13

83.R5003.C8F

D4CH551H-30PT-GP

RN20SRN10KJ-6-GPRN20SRN10KJ-6-GP

1 3

U18CTSAHCT125PW -GPU18CTSAHCT125PW -GP

U18DTSAHCT125PW -GPU18DTSAHCT125PW -GP

1 1

RN62SRN0J-10-GP-U

UMA

RN62SRN0J-10-GP-U

UMA

13

5

6

78910

11

121314151716

68.00230.021

L3FCB1608CF-GP

69.50007.691

F3FUSE-1D1A6V-4GP-U

69.50007.691

RN66SRN2K2J-1-GPRN66SRN2K2J-1-GP

C107SCD1U16V2ZY-2GPC107SCD1U16V2ZY-2GP

RN53SRN0J-10-GP-U

UMA

RN53SRN0J-10-GP-U

UMA

13

1 3

L4FCB1608CF-GP

68.00230.021

L4FCB1608CF-GP

68.00230.021

RN57SRN0J-10-GP-U

DIS

RN57SRN0J-10-GP-U

DIS

13

Trang 20

HDMI_TXC-HDMI_TX0+

HDMI_TX0-HDMI_TX1-HDMI_TX1+

TDMS_A_DAT_R

HDMI_TX0+

HDMI_TX0-HDMI_TX1+

HDMI_TX1-HDMI_TXC+

HDMI_TXC-HDMI_TX2+

HDMI_TX0+

HDMI_TX0-HDMI_TX1-HDMI_TX1+

HDMI_TX2-HDMI_TXC+

HDMI_TXC-HDMI_TX2+R

HDMI_TX0-RHDMI_TX0+R

HDMI_TX2-RHDMI_TX1-RHDMI_TX1+R

HDMI_TXC-RHDMI_TXC+R

3D3V_S0

5V_S03D3V_S0

HDMI_DETECT#7

NV_HDMI_CLK54NV_HDMI_DAT54

UMA

Q102N7002-11-GP

DIS

R31318KR2J-GP

DIS

12

1

Q242N7002-11-GP

DIS

Q242N7002-11-GP

U11

TSCBTD3305CPW R-GP

73.03305.A0B DIS

UMA

R637K5R2F-1-GP

DIS

R13100KR2J-1-GP

OUT_D3+OUT_D3- 1617

OUT_D2+OUT_D2- 1920

OUT_D1+ 22OUT_D1- 23

UMA 66.15236.04L

RN14SRN1K5J-GP

UMA 66.15236.04L

DIS

RN86SRN2K2J-1-GP

DIS

R31447KR2J-2-GP

DIS

R31447KR2J-2-GP

DIS

R7220KR2J-L2-GP

DY

R7220KR2J-L2-GP

DY

R4581KR2J-1-GP

UMA

R944K7R2J-2-GP

UMA

R6420KR2J-L2-GP

UMA

R6420KR2J-L2-GP

UMA

R74499R2F-2-GP

UMA

R74499R2F-2-GP

CEC 13

GND 20

GND 21GND 22GND 23

D3

BAW 56-2-GPD3

BAW 56-2-GP123

DIS

R1234K7R2F-GP

UMA

R731KR2J-1-GP

UMA

12

Trang 21

SATA_RXN0_C SATA_TXP0_C

23

24

1 2 4 6 8 10 12 14 16 18 20 22

C254 SCD01U50V2KX-1GP C254 1 SCD01U50V2KX-1GP 2

Trang 22

SATA_RXP1_C

5V_S0

SATA_TXP1 12 SATA_TXN1 12 SATA_RXN1 12 SATA_RXP1 12

ODD Connector

SB 1204

C403 SCD01U50V2KX-1GP C403 1 2 SCD01U50V2KX-1GP C410 SCD01U50V2KX-1GP C410 1 2 SCD01U50V2KX-1GP

C258 SCD01U50V2KX-1GP C258 1 2 SCD01U50V2KX-1GP

R214 10KR2J-3-GP DY

P1 P3 P5 13

14 D9 S

Trang 23

BLUETOOTH_EN 35

USBPN7 13,51 USBPP7 13,51

BLUETOOTH MODULE

EC20 put near BLUE1 / all USB put one choke near connector by EMI request

C862 SC4D7U10V5ZY-3GP C862 SC4D7U10V5ZY-3GP

U65

G5240B1T1U-GP U65

EC59 SCD1U16V2ZY-2GP DY

Trang 24

5V_USB1_S05V_USB1_S0

USBPN913USBPP913

USBPN013USBPP013

USB_OC#113,51

USB_PW R_EN#

35,51

OUT#6OC# 65USB1

1617

Trang 25

LAN_AVDD

BIASVDD_GXTALVDD_G

LAN_AVDD

UART_MODEGPIO0GPIO2AVDDL_G

LAN_X0

RDAC

LAN_XO_RLAN_XI

PCIE_SDSVDDAVDDL_G

AVDDL_G

XTALVDD_G

SCLKBIASVDD_G

SOCS#

REGCTL12

PCIE_RXDNPCIE_RXDP

LOW _PW RVMAINPRSNTVAUX_PRESENTAVDDL_G

3D3V_LAN_S5_1

EE_W PSOSCLK

EE_W P

DC#68DC#38

3D3V_LAN_S53D3V_LAN_S5

MDI1- 26

MDI0- 26MDI0+ 26MDI1+ 26

MDI3- 26

MDI2- 26MDI2+ 26MDI3+ 26

3PLT_RST1#

LOW _PW R35

R349 change to Bead for Transmitter Distortion

Place PLLVDD/AVDDLCKT as close to chip aspossible

SRN4K7J-10-GP1357

C31SCD1U10V2KX-4GP

R19

FCM1608K-601T03GPR19

FCM1608K-601T03GP12

TP223 TPAD14-GP1

100R2J-2-GP12

WP 7

VCC 8C70

Q9

DCP69A-13-GP

84.DCP69.01B

CBE

Q9

DCP69A-13-GP

84.DCP69.01B

123

4

R65200R2J-L1-GPR65

2

R231K24R2F-GPR231K24R2F-GP

C78SC33P50V2JN-3GPC78SC33P50V2JN-3GP

2

R5210KR2J-3-GP

DYR5210KR2J-3-GP

2

R400R0603-PADR400R0603-PAD

R5110KR2J-3-GP

DYR5110KR2J-3-GP

DY

R7010KR2J-3-GPR7010KR2J-3-GP

R310R0603-PADR310R0603-PAD12

RN13SRN1K5J-GPRN13SRN1K5J-GP

13

R280R0603-PADR28

TP222 TPAD14-GP1

BCM5764MKMLG-GP

SPD100LED# 1LINKLED# 2

Trang 26

CONN_PW R2CONN_PW R

RJ45_7

RJ45_8MCT4

XRF_TDC1XRF_TDC2

XRF_TDC3

RJ45_5MCT3

CONN_PW R2RJ45_8RJ45_6RJ45_3

RJ45_7RJ45_5

3D3V_S5

25

MDI1-25

MDI3-25

JV50

LAN Connector

1.route on bottom as differential pairs.

2.Tx+/Tx- are pairs Rx+/Rx- are pairs.

3.No vias, No 90 degree bends.

4.pairs must be equal lengths.

5.6mil trace width,12mil separation.

6.36mil between pairs and any other trace.

7.Must not cross ground moat,except

RJ-45 moat.

LAN Connector

GIGA Lan Transformer

Yellow(B2), when LAN is transfering data

Green(A3), behavior is the same for 10/100/1000 bits

A2(+) A1(-)::GREEN

B1(+) B2(-):YELLOW LED COLOR

SB 1208

C502SC1KP50V2KX-1GP

DY

C502SC1KP50V2KX-1GP

DY

C8SC1KP50V2KX-1GP

DY

C8SC1KP50V2KX-1GP

3

4

6

78

9

10

12

2423

22

21

19

1817

10

RN50

SRN470J-4-GP-URN50

SRN470J-4-GP-U13

Trang 27

MIC1-R_PORT-BAUD_MIC_L

MIC2VINT_MIC1_R

3D3V_S0

5VA_S0

3D3V_S03D3V_S0

ACZ_SDATAIN012ACZ_SDATAOUT_AUDIO 12LINE_IN_L

29LINE_IN_R29

AUD_HP1_OUT_L28AUD_HP1_OUT_R28

AMP_SHUTDOW N#28,35

MAX9789A_SHDN#

28SPDIF_GPU 52

R5170R0402-PADR5170R0402-PAD

SC1U10V3KX-3GP

RN79

SRN2K2J-2-GPRN79

SRN2K2J-2-GP

1357

R5150R0402-PADR5150R0402-PAD

83.00056.E11 DY

D32BAW 56-3-GP

83.00056.E11 DY

SIDESURR_L 45SIDESURR_R 46

SURR_L 39SURR_R 41

FRONT_L35FRONT_R 36

C820

C843SC10U10V5ZY-1GPC843SC10U10V5ZY-1GP

R51239K2R2F-L-GPR51239K2R2F-L-GP

C844

SCD1U10V2KX-4GPC844

RN77

SRN75J-1-GPRN77

SRN75J-1-GP

1357

R5160R3-0-U-GP

DIS

R5160R3-0-U-GP

DIS

12

C858SCD1U50V3KX-GP

DY

C858SCD1U50V3KX-GP

DY

C855SC10U10V5ZY-1GPC855SC10U10V5ZY-1GP

R52420KR2F-L-GPR52420KR2F-L-GP

C826SC10U10V5ZY-1GP

DY

C826SC10U10V5ZY-1GP

DY

C835SCD1U50V3KX-GP

DY

R5141K91R2F-1-GPR5141K91R2F-1-GP

SRN47K-2-GP-U13

R51020KR2F-L-GPR51020KR2F-L-GP

Trang 28

SPKR_R-SPKR_L+

AUD_AMP_GAIN1

AUD_SPK_ENABLE#

AMP_C1PAMP_C1NAUD_BIASAMP_MUTE#_R

AUD_CPVSS

AUD_HP1_OUT_R2AUD_HP1_OUT_L2

SPKR_R+1SPKR_L+1

AMP_REGEN

AUD_AMP_GAIN2AUD_AMP_GAIN1

AUD_HP1_OUT_L1AUD_HP1_OUT_R1

AUD_LIN_R_1AUD_LIN_L_1

AMP_MUTE#_R

AUD_SPK_ENABLE#

+5V_SPK_AMP5VA_S0

+5V_SPK_AMP

5V_S0+5V_SPK_AMP+5V_SPK_AMP

29SPKR_L+129

MAX9789A_SHDN#27

AUD_LINE_OUT_R27AUD_LINE_OUT_L27

60ohm 100MHz

3000mA 0.05ohm DC

Close to Pin9 Close to U53.8 Close to U53.18

Signal inverter for speaker shutdown

R4962K2R2J-2-GPR4962K2R2J-2-GP

C805

SC1U10V3KX-3GPC805

SC1U10V3KX-3GP12

BIAS 24C1P 10C1N 12

SPKR_EN# 23

G113

GAP-CLOSEG113

100KR2J-1-GP12

GAP-CLOSE

G110

GAP-CLOSEG110

GAP-CLOSE

R47910KR2F-2-GPR47910KR2F-2-GP12

DY

R475100KR2J-1-GP

R4804K99R2F-L-GPR4804K99R2F-L-GP12

U55

2N7002A-7-GPU55

2N7002A-7-GPG

Trang 29

LOUT_L+1LOUT_R+15V_SPDIF_S0

LINE_IN_L_CONNLINEIN_JD#_RLINE_IN_R_CONN

LOUT_L+1LOUT_R+1

AUD_MICIN_RAUD_MICIN_L5V_S0

3D3V_S03D3V_S0

SPKR_L+

28,51SPKR_R-28,51SPKR_R+

28,51SPKR_L-28,51

MIC_JD#

27

AUD_MICIN_L27

AUD_MICIN_R27

LINEOUT_JD#

27

SPKR_R+128SPKR_L+128

AUD_SPDIF_OUT27

Internal Speaker

MIC IN LINE OUT

4

L34

MLVS0603M04-1-GPL34

L29

MLVS0603M04-1-GPL29

RN75

SRN75J-2-GP-URN75

SRN75J-2-GP-U13C773

SCD1U16V2ZY-2GP

DY

C773SCD1U16V2ZY-2GP

SRN75J-2-GP-U13

L30

MLVS0603M04-1-GPL30

MLVS0603M04-1-GP

G117GAP-CLOSEG117GAP-CLOSE

6NP1

L32

MLVS0603M04-1-GPL32

6NP1

L33

MLVS0603M04-1-GPL33

LOUT1

PHONE-JK332-GP

22.10133.G51

ACNP1

135

Trang 30

ACZ_BTCLK_MDC_A ACZ_SDATAOUT_A

ACZ_SDATAIN1_A ACZ_RST#_A

1D5V_S5_3D3V_S5_MDC

3D3V_S5

3D3V_S5 1D5V_S5

13 14 15

16 17 18

DY

C196 SC22U6D3V6KX-1GP

R274 39R2J-L-GP R274 39R2J-L-GP

Tiêu đề	Block diagram
Trường học	Wistron Corporation
Thể loại	Bản vẽ
Năm xuất bản	2009
Thành phố	Taipei Hsien

Định dạng
Số trang	61
Dung lượng	1,62 MB