Broadband Packet Switching Technologies: A Practical Guide to ATM Switches and IP RoutersH.. This book addresses the basics, theory, architectures, and technologies to implement ATM swit
Trang 1Broadband Packet Switching Technologies: A Practical Guide to ATM Switches and IP Routers
H Jonathan Chao, Cheuk H Lam, Eiji OkiCopyright䊚 2001 John Wiley & Sons, Inc
ISBNs: 0-471-00454-5 Hardback ; 0-471-22440-5 Electronic
BROADBAND PACKET
SWITCHING TECHNOLOGIES
Trang 2JOHN WILEY & SONS, INC.
New York r Chichester r Weinheim r Brisbane r Singapore r Toronto
Trang 3Designations used by companies to distinguish their products are often claimed as trademarks.
In all instances where John Wiley & Sons, Inc., is aware of a claim, the product namesappear in initial capital or ALL CAPITAL LETTERS Readers, however, should contact theappropriate companies for more complete information regarding trademarks and registration.Copyright䊚 2001 by John Wiley & Sons, Inc All rights reserved
No part of this publication may be reproduced, stored in a retrieval system or transmitted
in any form or by any means, electronic or mechanical, including uploading, downloading,printing, decompiling, recording or otherwise, except as permitted under Sections 107 or
108 of the 1976 United States Copyright Act, without the prior written permission of thePublisher Requests to the Publisher for permission should be addressed to the
Permissions Department, John Wiley & Sons, Inc., 605 Third Avenue, New York, NY
10158-0012, 212 850-6011, fax 212 850-6008, E-Mail: PERMREQ & WILEY.COM.This publication is designed to provide accurate and authoritative information in regard to thesubject matter covered It is sold with the understanding that the publisher is not engaged inrendering professional services If professional advice or other expert assistance is required, theservices of a competent professional person should be sought
ISBN 0-471-22440-5
This title is also available in print as ISBN 0-471-00454-5
For more information about Wiley products, visit our web site at www.Wiley.com
Trang 41.1 ATM Switch Systems r 3
1.1.1 Basics of ATM networks r 3
1.1.2 ATM switch structure r 5
2.1.1 Internal link blocking r 17
2.1.2 Output port contention r 18
2.1.3 Head-of-line blocking r 19
2.1.4 Multicasting r 19
2.1.5 Call splitting r 20
2.2 Switch Architecture Classification r 21
2.2.1 Time division switching r 22
v
Trang 53.1 A Simple Switch Model r 50
3.1.1 Head-of-line blocking phenomenon r 51
3.1.2 Traffic models and related throughput results r 52
3.2 Methods for Improving Performance r 53
3.2.1 Increasing internal capacity r 53
3.2.2 Increasing scheduling efficiency r 54
3.3 Scheduling Algorithms r 57
Ž 3.3.1 Parallel iterative matching PIM r 58
Ž 3.3.2 Iterative round-robin matching iRRM r 60
Ž 3.3.3 Iterative round-robin with SLIP iSLIP r 60
Ž 3.3.4 Dual round-robin matching DRRM r 62
3.3.5 Round-robin greedy scheduling r 65
3.3.6 Design of round-robin arbiters rselectors r 67
3.4 Output-Queuing Emulation r 72
Ž 3.4.1 Most-Urgent-Cell-First-Algorithm MUCFA r 72
3.4.2 Chuang et al.’s results r 73
Ž 3.5 Lowest-Output-Occupancy-Cell-First Algorithm LOOFA
r 78
References r 80
4.1 Linked-List Approach r 84
4.2 Content-Addressable Memory Approach r 91
4.3 Space ᎐Time᎐Space Approach r 93
4.4 Multistage Shared-Memory Switches r 94
4.4.1 Washington University gigabit switch r 95
4.4.2 Concentrator-based growable switch
architecture r 96 4.5 Multicast Shared-Memory Switches r 97
Trang 6CONTENTS vii
4.5.1 Shared-memory switch with a multicast logical
queue r 97 4.5.2 Shared-memory switch with cell copy r 98
4.5.3 Shared-memory switch with address copy r 99
5.5.1 Tandem banyan switch r 114
5.5.2 Shuffle-exchange network with deflection
routing r 117 5.5.3 Dual shuffle-exchange network with error-correcting
routing r 118 5.6 Multicast Copy Networks r 125
5.6.1 Broadcast banyan network r 127
5.6.2 Encoding process r 129
5.6.3 Concentration r 132
5.6.4 Decoding process r 133
5.6.5 Overflow and call splitting r 133
5.6.6 Overflow and input fairness r 134
References r 138
6.1 Single-Stage Knockout Switch r 142
6.1.1 Basic architecture r 142
6.1.2 Knockout concentration principle r 144
6.1.3 Construction of the concentrator r 146
6.2 Channel Grouping Principle r 150
6.2.1 Maximum throughput r 150
6.2.2 Generalized knockout principle r 152
6.3 A Two-Stage Multicast Output-Buffered ATM
Switch r 154
6.3.1 Two-stage configuration r 154
Trang 7viii
6.3.2 Multicast grouping network r 157
6.3.3 Translation tables r 160
6.3.4 Multicast knockout principle r 163
6.4 A Fault-Tolerant Multicast Output-Buffered ATM
Switch r 169
6.4.1 Fault model of switch element r 169
6.4.2 Fault detection r 172
6.4.3 Fault location and reconfiguration r 174
6.4.4 Performance analysis of reconfigured switch
module r 181 6.5 Appendix r 185
References r 187
7.1 Basic Architecture r 190
7.2 Multicast Contention Resolution Algorithm r 193
7.3 Implementation of Input Port Controller r 197
7.4 Performance r 198
7.4.1 Maximum throughput r 199
7.4.2 Average delay r 203
7.4.3 Cell loss probability r 206
7.5 ATM Routing and Concentration Chip r 208
7.6 Enhanced Abacus Switch r 211
7.6.1 Memoryless multistage concentration network r 212
7.6.2 Buffered multistage concentration network r 214
8.1 Overview of Crosspoint-Buffered Switches r 228
8.2 Scalable Distributed Arbitration Switch r 229
8.2.1 SDA structure r 229
8.2.2 Performance of SDA switch r 231
8.3 Multiple-QoS SDA Switch r 234
8.3.1 MSDA structure r 234
Trang 8CONTENTS ix
8.3.2 Performance of MSDA switch r 236
References r 238
9.1 Overview of Input ᎐Output᎐Buffered Switches r 239
10.1 Routing Properties and Scheduling Methods r 255
10.2 A Suboptimal Straight Matching Method for Dynamic
scheme r 265 10.4.3 Desynchronization effect of CRRD r 267
10.5 The Path Switch r 268
10.5.1 Homogeneous capacity and route
assignment r 272 10.5.2 Heterogeneous capacity assignment r 274
References r 277
11.1 All-Optical Packet Switches r 281
11.1.1 The staggering switch r 281
Trang 911.3.4 Cell synchronization unit r 297
11.4 Optical Interconnection Network for Terabit IP
Routers r 301
11.4.1 Introduction r 301
11.4.2 A terabit IP router architecture r 303
11.4.3 Router module and route controller r 306
11.4.4 Optical interconnection network r 309
11.4.5 Ping-pong arbitration unit r 315
11.4.6 OIN complexity r 324
11.4.7 Power budget analysis r 326
11.4.8 Crosstalk analysis r 328
References r 331
12.1 Wireless ATM Structure Overviews r 338
12.1.1 System considerations r 338
12.1.2 Wireless ATM protocol r 349
12.2 Wireless ATM Systems r 341
12.2.1 NEC’s WATMnet prototype system r 341
12.2.2 Olivetti’s radio ATM LAN r 342
12.2.3 Virtual connection tree r 342
12.2.4 BAHAMA wireless ATM LAN r 343
12.2.5 NTT’s wireless ATM Access r 343
12.2.6 Other European projects r 243
12.3 Radio Access Layers r 344
12.3.1 Radio physical layer r 344
12.3.2 Medium access control layer r 346
12.3.3 Data link control layer r 346
12.4 Handoff in Wireless ATM r 347
12.4.1 Connection rerouting r 348
12.4.2 Buffering r 340
Trang 10CONTENTS xi
12.4.3 Cell routing in a COS r 351
12.5 Mobility-Support ATM Switch r 352
12.5.1 Design of a mobility-support switch r 353
12.5.2 Performance r 358
References r 362
13.1 IP Router Design r 366
13.1.1 Architectures of generic routers r 366
13.1.2 IP route lookup design r 368
13.2 IP Route Lookup Based on Caching Technique
r 369
13.3 IP Route Lookup Based on Standard Trie
Structure r 369
13.4 Patricia Tree r 372
13.5 Small Forwarding Tables for Fast Route Lookups r 373
13.5.1 Level 1 of data structure r 374
13.5.2 Levels 2 and 3 of data structure r 376
13.7 IP Lookups Using Multiway Search r 381
13.7.1 Adapting binary search for best matching
prefix r 381 13.7.2 Precomputed 16-bit prefix table r 384
13.7.3 Multiway binary search: exploiting the cache
line r 385 13.7.4 Performance r 388
13.8 IP Route Lookups for Gigabit Switch Routers r 388
13.8.1 Lookup algorithms and data structure
construction r 388 13.8.2 Performance r 395
13.9 IP Route Lookups Using Two-Trie Structure r 396
13.9.1 IP route lookup algorithm r 397
13.9.2 Prefix update algorithms r 398
13.9.3 Performance r 403
References r 404
Trang 11xii
A.1 ATM Protocol Reference Model r 409
Ž A.2 Synchronous Optical Network SONET r 410
A.2.1 SONET sublayers r 410
A.2.2 STS-N signals r 412
A.2.3 SONET overhead bytes r 414
A.2.4 Scrambling and descrambling r 417
A.2.5 Frequency justification r 418
Ž A.2.6 Automatic protection switching APS r 419
A.2.7 STS-3 versus STS-3c r 421
A.2.8 OC-N multiplexer r 422
A.3 Sub-Layer Functions in Reference Model r 423
Ž A.4 Asynchronous Transfer Mode ATM r 425
A.4.1 Virtual path rvirtual channel identifier
Ž VPI rVCI r 426
Ž A.4.2 Payload type identifier PTI r 427
Ž A.4.3 Cell loss priority CLP r 428
A.4.4 Pre-defined header field values r 428
Ž A.5 ATM Adaptation Layer AAL r 429
Ž A.5.1 AAL type 1 AAL1 r 431
Ž A.5.2 AAL type 2 AAL2 r 433
Ž A.5.3 AAL types 3 r4 AAL3r4 r 434
Ž A.5.4 AAL type 5 AAL5 r 436
References r 438
Trang 12This book addresses the basics, theory, architectures, and technologies to implement ATM switches, IP routers, and optical switches The book is based on the material that Jonathan has been teaching to the industry and universities for the past decade He taught a graduate course ‘‘Broadband Packet Switching Systems’’ at Polytechnic University, New York, and used the draft of the book as the text The book has incorporated feedback from both industry people and college students.
The fundamental concepts and technologies of packet switching described
in the book are useful and practical when designing IP routers, packet switches, and optical switches The basic concepts can also stand by them- selves and are independent of the emerging network platform, for instance,
Ž
IP, ATM, MPLS, and IP over wavelength-division multiplexing WDM ATM switching technologies have been widely used to achieve high speed and high capacity This is because ATM uses fixed-length cells and the switching can be implemented at high speed with synchronous hardware
xiii
Trang 13ATM cells The switching technologies described in this book are common
to both ATM switches and IP routers We believe that the book will be a practical guide to understand ATM switches and IP routers.
AUDIENCE
This book can be used as a reference book for industry people whose job is related to ATM rIPrMPLS networks Engineers from network equipment and service providers can benefit from the book by understanding the key concepts of packet switching systems and key techniques of building a high-speed and high-capacity packet switch This book is also a good text for senior and graduate students in electrical engineering, computer engineering, and compute science Using it, students will understand the technology trend
in packet networks so that they can better position themselves when they graduate and look for jobs in the high-speed networking field.
ORGANIZATION OF THE BOOK
The book is organized as follows.
䢇 Chapter 1 introduces the basic structure of ATM switching systems and
IP routers It discusses the functions of both systems and their design criteria and performance requirements.
䢇 Chapter 2 classifies packet switching architectures into different gories and compares them in performance and implementation com- plexity It also covers terminologies, concepts, issues, solutions, and approaches of designing packet switches at a high level so that readers can grasp the basics before getting into the details in the following chapters.
cate-䢇 Chapter 3 discusses the fundamentals of input-buffered switches Switches with input and output buffering are also described in this chapter We show the problems of input-buffered switches, and present the techniques and algorithms that have been proposed to tackle the problems.
䢇 Chapter 4 discusses the shared-memory switches, which have been widely used in industry because of their high performance and small buffers We describe the operation principles of the shared-memory switches in detail.
Trang 14PREFACE xv
䢇 Chapter 5 discusses banyan-family switches, which have attracted many researchers for more than two decades as components of interconnec- tion networks We discuss the theory of the nonblocking property of Batcher ᎐banyan switches and describe several example architectures in detail.
䢇 Chapter 6 discusses several switches based on the knockout principle Their implementation architectures are described in detail.
䢇 Chapter 7 describes a scalable multicasting switch architecture and a fault-tolerant switch The latter is very important for a reliable network but has not been received much attention We discuss the architectures and algorithms for building such switches.
䢇 Chapter 8 discusses a scalable crosspoint-buffered switch architecture with a distributed-contention control scheme We also describe how to
Ž support multiple quality-of-service QoS classes in the switch.
䢇 Chapter 9 discusses an input ᎐output-buffered switch, called the tandem-crosspoint switch, that fully utilizes current CMOS technologies.
䢇 Chapter 10 discusses multi-stage Clos-network switches, which are tractive because of their scalability It presents the properties of Clos networks and introduces several routing algorithms in the Clos network.
at-䢇 Chapter 11 describes optical switch architectures in both all-optical and optoelectronic approaches Several design examples are described.
䢇 Chapter 12 introduces mobility-support ATM switches It also discusses wireless ATM protocols and surveys several proposed wireless ATM systems.
䢇 Chapter 13 discusses fast IP route lookup approaches, which have been proposed over the past few years Their performance and implementa- tion complexity are described.
ACKNOWLEDGMENTS
This book could not have been published without the help of many people.
We thank them for their efforts in improving the quality of the book We have done our best to accurately describe broadband packet switching technologies If any errors are found, please send an email to chao@poly.edu.
We will correct them in future editions.
The entire manuscript draft was reviewed by Dr Aleksandra Smiljanic
Ž AT & T Laboratories , Dr Li-Sheng Chen Alcatel , Dr Kurimoto Takashi Ž
Ž NTT , Dr Soung-Yue Liew, and Dr Zhigang Jing Polytechnic University Ž
We are immensely grateful for their critiques and suggestions.
Several chapters of the book are based on research work that was done at Polytechnic University, Chinese University of Hong Kong, and NTT We
Trang 15xvi
would like to thank several persons who contributed material to some
Ž chapters Especially, we thank Professor Tony Lee Chinese University of
Jonathan wants to thank his wife, Ammie, and his children, Jessica, Roger, and Joshua, for their love, support, encouragement, patience and persever- ance He also thanks his parents for their encouragement Cheuk would like
to thank his wife, Lili, and his parents for their love and support Eiji wishes
to thank his wife, Noako, and his daughter, Kanako, for their love.
H JONATHANCHAO
CHEUKH LAM
EIJIOKI
July 2001
Trang 16Broadband Packet Switching Technologies: A Practical Guide to ATM Switches and IP Routers
H Jonathan Chao, Cheuk H Lam, Eiji OkiCopyright䊚 2001 John Wiley & Sons, Inc
ISBNs: 0-471-00454-5 Hardback ; 0-471-22440-5 Electronic
BROADBAND PACKET
SWITCHING TECHNOLOGIES
Trang 17multicast contention resolution algorithm,
wireless ATM WATM switches, datalink control layer, 347
Adaptive homing algorithm, wireless ATM
ŽWATM switches, BAHAMA wireless.ATM LAN, 343
AddPrefix X, Y, Z algorithm, internet
Ž protocol IP route lookups, two-triestructure, 399᎐402
Ž Address broadcaster AB :abacus switch, architecture, 191᎐193fault-tolerant multicast output-buffered ATM switch, fault detection,173
multicast grouping networks MGNs ,
157᎐160Address copy, multicast shared-memoryswitch, 99᎐101
Ž Address filter AF :
ŽBBN , boolean interval spitting.algorithm, 128᎐129
439
Trang 18medium access control layer, 346
Olivetti’s radio ATM LAN, 342
radio physical layer, 346
Application-specific integrated circuit
ŽASIC :
abacus switch architecture, 208᎐211
wireless ATM WATM switches,
mobility-support ATM switch, 354᎐358
Arbiter device:
abacus switch, multicast contention
resolution algorithm, 194᎐197
Ž optical interconnection network OIN ,
Ž ping-pong arbitration unit PAU ,
315᎐324
Arbitrating cells, input-buffered switches,
output port contention, 49᎐50
Arbitration control CNTL :
multiple-QoS scalable
Ž distributed-arbitration switch SDA ,
round-robin arbitersrselectors, 67᎐72
Ž bidirectional arbiter NTT , 67᎐70
Ž ping-pong arbitration unit PAU ,
316᎐324
Arrayed-waveguide grating AWG router,
Ž optical interconnection network OIN ,
309᎐315crosstalk analysis, 329᎐331tunable filters, 312᎐315
Asynchronous transfer mode ATM switches
See also specific ATM switches, e.g.,
Wireless ATMapplications, 2architecture:
buffering strategies, 34᎐37classification, 21᎐37design and performance criteria, 13᎐17
Ž space-division switching SDS , 24᎐34multiple-path switches, 29᎐34single-path switches, 25᎐29
Ž time-division switching TDS , 22᎐24shared-medium switch, 22᎐23shared-memory switch, 23᎐24basic concepts, 15᎐17
call splitting, 20᎐24
head-of-line HOL blocking, 19internal link blocking, 17᎐18multicasting, 20᎐21network basics, 35optical ATMOS switch, 282᎐283output port contention, 16᎐18protocols:
background, 407᎐409cell loss priority, 428᎐429cell structure, 425᎐426payload type identifier, 427᎐428reference model, 409᎐410virtual path and channel identifiers,
426᎐427switch structure, 58Atlanta switch:
architecture, 261configuration, 259᎐261distributed and random and arbitration,
261᎐262multicasting, 262᎐263
Ž ATM adaptation layer AAL , asynchronous