Soc Encounter P1

Getting Started ont, Vv Data preparation cont — Design Netlist ¢ Add IO cells — Refer to IO cell library datasheet, type the following command at UNIX prompt acroread /RAID2/Manager

NCTU-EE ICLAB II — Dec 2005

Cell-based APR Design Flow

Cell-based Design Flow

Cell-based Design Tools

Traditional APR Flow

RC extraction Timing check

Logic design

Fast logic synthesis

Partition/floorplan

SI analysis

E Si

L ` soos Power plan & ; 5

Wiring Problem

wire resistance 2

to 15 ¬ Total Delays

— Signal Integrity closure _ ca

— Power closure (IR drop, .) Technology Generation

Physigal Synthesis tool Prevention Power Analysis tool

Physical

eT ee

SoC Encounter

Y SoC Encounter

— Itis a hierarchical physical implementation environment

— Comprised of the following tools

— sign-off quality SI analysis

¢ Physically Knowledgeable Synthesis (PKS)

— complex optimizations which require logic restructuring

SCM Physical (PKS Cadence) (Physical compiler—Synopsys)

ri pg 8 (61) System Integration & Silicon Implementation Group.

Getting Started (ont,

Vv Data preparation cont)

— Design Netlist

¢ Add IO cells

— Refer to IO cell library datasheet, type the following command at UNIX prompt

acroread /RAID2/Manager/lib.18/doc/umc18io3v5v.pdt &

— Add IO pads, core power pads, IO power pads, and corner pads to synthesized design netlist

Note: how to decide the number of power pads "¬

will be discussed in power planning "¬

Getti Ng Sta rted (cont.)

¢ Uniquify design netlist

— The Verilog design neilist must be unique for running Clock Tree Synthesis (CTS), Scan Reorder, and In-Placement Optimization(IPO)

— To ensure that the names of all instantiated cells are unique, type

uniquifyNetlist —top TopModuleName Uniquified_ Netlist Design_Netlist

at the UNIX prompt

Getti Ng Sta rted (cont.)

Vv Data preparation cont,

— |O pad location file

Getting Started (ont,

Vv Data preparation cont)

— An example of IO pad location file

Pad: po2 Pad: po3

Pad: po12 Pad: po13

Pad; PCUR NE PCORNER

Import Design

Vv Import design

— Import design files into Encounter environment

| Design | Edit FlipChip Partition Floorplan Place Glock Route Timing © SI_—- Power Verify Tools

— Technology Information/Physical Libraries:

| LEF Files: umc18_ 5lm.lef umc18_5lm_anteni EI r Physical libraries

Common Timing Libraries: EI Stamp Model Definitions: Bl

Buffer hlame/Footprint: buf T Buffer footprint Delay Name/Footprint: \dly1 dly2 dly3 dly4 + Delay footprint

| Inverter Name/F ootprint: inv i Inverter footprint _! Generate Footprint Based on Functional Equivalence

IO Information:

j lO Assignment File: |CHIP.io Bi lo assignment

Exclude Net File: | |

Default Delay Pin Limit: | 1000

Default Net Delay: | 1000.0ps

Default Net Load: 0.5pf Input Transition Delay: 0.0ps

— RC Extraction

Capacitance Table File: | DI

Default Cap Scale Factor: f 10 Detail Cap Scale Factor: [4.0 Coupling Cap Scale Factor: fF

Resistance Scale Factor: | 10

Shrink Factor: f 10

Relative C Threshold(0-0.) 0.01 Total C Threshold (fF)(0-20);; 50

Timing Constraint File: CHIP.sdc

Capacitive Load Unit (pf):

Time Unit: ^^ From Library ~- Ins ~ Ips , 10ps ~, 100ps

— You can save the settings to CH/P.conf by clicking

save bottom, then you can load it by using load bottom in the next time without typing those data again

Design Edit Flip Chip Partition Hoorplan Place Cock Route Timing sl Power Verify Tools Help

Z| HAYUQQ.A) C| GE 46) Z| s| | 8| 6| mị| Designis InMemoy |

504.870)

Floorplanning

Y Calculating core size, width and height

— When calculating core size of standard cells, the core utilization must

be decided first Usually the core utilization is higher than 85%

— Thecore size is calculated as follows

Core Size of Standard Cell = standard cell area

core utilization

— The recommended core shape is a square, i.e Core Aspect Ratio = 1

Hence the width and height can be calculated as

Width = Height = Core Size of Standard Cells

¢ Note: because stripes and macros will be added, width and height are

usually set larger than the value calculated above

— EX:

¢ Standard cell area = 2,000,000

¢ Core utilization demanded = 85%

¢ Note: the width needed for P/G ring will be discussed in power planning

Y Core limited design or Pad limited design

— Die size determination

Pad

¢ When pad width > (core width + core margin), wes

die size is decided by pads

And it is called pad limited design Y

¢ When pad width < (core width + core margin), die size is decided by core

And it is called core limited design

— Adding pad filler

¢ There should be no spacing between pads

Therefore adding pad filler is necessary for core limited design

Floorplanning (cont

Y Setup the floorplan

— Define core width, height and core margin

Design Edit HipCGhp Partition | Floorplan} Place ock Route Timing Sl Power Venfy Tools

^ Size by:

“ Core Size by: , Aspect Ratio: Ratio (H/W);: mwwr

¢ First, set Core Width and Height to a small 2 Gis Uiication: "Gaze7ee

value, such as 100 " a

¢ Set Core to |O Boundary to a suitable \ Die Size by: Wath an Hight DieHeight| 02

value, such as 100 (design dependent) a =

~ Core to Die Boundary

— For core limited design eC | eee ra

unit: micron

¢ Set Core to 10 Boundary to a suitable value | $2zs°zs< |

Double-back rows: F-| Bottom row orient’ [7] — |

Row height: |504.”

IO Specifications

9K | | Amy | Gmeal | - Hep |

v

Move macro blocks to proper position

Press this button to move macro block

i A

Design Edit Flip Chip Partition Floorplan Place Cock Route Timing Sl Power Verify Tools Help | Design Edit Flip Chip Partition Floorplan Place Cock Route Timing sl Power Verify Tools Help

D| AAI @) 2) o| BE A/4) als 5] ajo)o Desgis InMemoy j | D| YAU Ao] AA Ao) Gxt) a) ojo) Design is:_InMemory _|

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VCongest M ‹ | VCongest M ‹: HCongest M ‹:

Text =

HCongest ‹ Text

x Encounter - /misc/RATD2/COURSE/Iclab/iclabt05/iclab2004b/lab01/DEMO l/encounfer - Top _ TÌ XÌ

Design Eiit HipChip Partition Hoorplan Place Cock Route’ Timing Sl Power Verify Tools Help

Guide a N

Obstuct J F Region BF F screen of FF Instance ST ƒƑƑ Net ss

Power Planning

w« Power issue

— Metal migration (also known as electro-migration)

e Under high currents, electron collisions with metal grains cause the metal to

move The metal wire may be open circuit or short circuit

¢ Prevention: sizing power supply lines to ensure that the chip does not fail

¢ Experience: make current density of power ring < 1mA/ “mM

e IR drop can cause the chip to fail due to

— Performance (circuit running slower than specification)

— Functionality problem (setup or hold violations)

— Unreliable operation (less noise margin)

— Power consumption (leakage power)

Power Planning cont)

¢ 80% FF with dynamic gated clock

¢ Current needed = 0.2mA/MHz

— Note: the value should multiply with 1.8~2 for no gated design

¢ Current density < 1mA/ um

¢ The Width of P/G Ring > 22.86 wm

¢ In order to avoid the slot rule of wide metal, the largest width is 20 “~m (process dependent)

¢ Use two set P/G ring for this case

Power Planning cont)

¢ Core width = height = 1600

¢ Stripe set added = 15

Y Core/IO power pad selection

— Core power pad

¢ One set core power pad (PVDDC along with PVSSC) can provide 40~50mA

Power Planning cont,

Vv Create power ring

— | Design Edit HipGhp Partition | HAloorplan} Place lock Route Timing SI Power Verify Tools

* Core Ring(s) contouring:

_j Exclude selected objects

* Each block Width All 20 Click Update oe domain/fences/reefs

( or the demanded value)

wv Each selected block and/or group of core rows

~ Clusters of selected blocks and/or groups of core rows

4 With shared ring edges

Offset + Center in channel

+x User defined coordinates | Mouse dick |

Layer: met5 H —| metl5H — || met4¥ =| met4¥ —

Ok | — Variables | | Apply Cancel | Defaults | ˆ

CTU bg.25 (61) System Integration & Silicon Implementation Group

Power Planning cont,

Y Create power ring (ont)

¢ If you want to create more than one set of power ring, in Advanced tab

= set Custom Ring Sides and Extension Wire G roup + Use Wire group

Number of bits The demanded value

'— | — Note: you can choose the option “Interleaving”

to observe the difference in power ring

created

[es |

_{ Create rectangular ring{s) only Merge with pre-routed rings if within spacing threshold: (0.33 Minimum jog distance: (0.33 Snap wire center to routing grid: None |

-Wire Group )~ Use wire group

~Í Interleaving Fill in the set of power ring

Power Planning cont,

Y Create power stripes

| Design Edit HlipChp ~—— Partition =| Floorplan) Place lock Route Timing SI Power Verfy Tools

Complete the form and click Apply or OK =

Layer: met2 —

Direction: |“ Vertical [Vv Horizontal | Use met3 for Horizontal

|With lo — | Fill in suitable value

Spacing: 0.32 Update

—set Pattern

¬x Set-to-set distance: (100

Specify set-to-set distance

“~ Number of sets: 4 or number of sets

~, Bumps * Over v, Between

~y Over P/Gpins =) layer Top pin layer —|

^ Master name: | vy Selected blocks vw, All blocks

— Note: after click point vẽ E——

» Start (X): click the location of first stripe in design display area | “”asmmewsseesasa

» Stop (X): click the location of last stripe in design display area| F——

Power Planning cont,

Y Global Net Connection

— Setup global net connection settings

Design Edit HipChp Partition | Floorplan} Place Qock Route Timing SI Power Verify Tools

Ly Global Net Connections

— Complete the form and click Apply

¢ Add power nets connection list

Connect @ Pins: VDD To Global Net VDD Click Add to List Connect @ Nets: VDD To Global Net VDD Click Add to List

¢ Add ground nets connection list

Connect @ Pins: GND To Global Net GND Click Add to List Connect @ Nets: GND To Global Net GND Click Add to List Connect @ Tie Low To Global Net GND Click Add to List

Power Planning cont)

Y Global Net Connection con)

Create six global net connection list

Connect Pin-VDD to Global Net-VDD Connect Net-VDD to Global Net-VDD Connect Tie High to Global Net-VDD Connect Pin-GND to Global Net-GND Connect Net-GND to Global Net-GND Connect Tie Low to Global Net-GND

To Global Net} VDO

_j Override prior connection _J Verbose Output

Add to List Update | Delete |

Power Planning cont,

Y Connect core power

— Connect from ring pins to core power pads

— | Design Edit HipChp Partition Floorplan Place Giock | Route | Timing SI Power Verfy Tools

Là SRoute _

Block pins ro (off) (ask 7 Padpins 1 Padrings 1 Standard cellpins 1 Stripes (unconnected)

Pad pins @ (on)

Pad rings > (off) Lm ame cm a

Top layer; MS) — Bottom layer, M1 —

Stripes (unconnected) | <> (off) ter sane yer — ee

_ Area Draw

- Note: make sure that core power pads ° TT - F

Connect to target inside the area only

are connected to the power ring

And the connection should not be “Generate ogress messages [FS —

mixed with stripes ni