Nghiên cứu chế tạo dây nano silic đơn tinh thể trên cơ sở công nghệ vi cơ khối ướt

11 A schematic drawing of silicon oxide mask fabricated by SPL on SOI wafer a, A schematic drawing of profile of silicon nanowire after etching b, AFM images of surface topography and pr

MINISTRY OF EDUCATION AND TRAINING

HANOI UNIVERSITY OF TECHNOLOGY AND SCIENCE

INTERNATIONAL TRAINING INSTITUTE FOR MATERIALS SCIENCE

-

TRIEU QUANG TUAN

STUDY AND FABRICATION OF SINGLE CRYSTAL SILICON NANOWIRE BASED ON

WET BULK MICROMACHINING

MASTER THESIS OF MATERIALS SCIENCE

Batch ITIMS-2015

SUPERVISOR

Dr CHU MANH HOANG

Hanoi – 2017

Finally, thanks should also be given to my family and friends, who always supported me in my study

2 Nguyen Van Minh, Trieu Quang Tuan, Vu Ngoc Hung and Chu Manh Hoang

“ An Overview Of Emerging Methods For Fabricating Single-Crystal Silicon

Nannowires ” , 9th Vietnam National Conference Of Solid Physics And Materials

Science, pp 371-376, 2015, ISBN: 978-604-938-722-7

3 Trieu Quang Tuan, Le Van Tam, Nguyen Van Minh , Nguyen Huu Dung ,

Vu Ngoc Hung and Chu Manh Hoang ” Fabrication Of Single Crystal Silicon

Nanowires Based On Shadow Mask Technique “, 10th Vietnam National Conference

Of Solid Physics And Materials Science, Accepted

STATEMENT OF ORIGINAL AUTHORSHIP

I hereby declare that the results presented in the thesis are performed by the author The research contained in this thesis has not been previously submitted to meet requirements for an award at this or any higher education institution

Date: 30/09/2017

Signature:

Contents

CHAPTER 1: INTRODUCTION OF SINGLE CRYSTAL SILICON

NANOWIRES 8

1 Introduction of single crystal silicon nanowire 10

1.1 What is the nanowire? 10

1.2 Applications of silicon nanowires 10

2 Fabrication methods of single crystal silicon nanowire 18

2.1 Photolithography 18

2.2 E-beam and ion-beam lithography 20

2.3 Scanning probe lithography (SPL) 21

2.4 Nanofabrication by Replication 22

2.5 Novel methods based on conventional photolithography 23

Chapter 2: FABRICATION OF SINGLE CRYSTAL SILICON NANOWIRES 30

2 1 Proposed fabrication processes 30

2 2 Experiment 34

2 2 1 Cleaning wafer 34

2.2.2 Oxidation 34

2.2.3 Photolithography 35

2.2.4 Silicon dioxide isotropic wet etching in buffered hydrofluoric acid (BHF) solution 37

2.2.5 Anisotropic etching in Potassium Hydroxide 38

2.2.6 Sputtering 40

Chapter 3 Results and Discusion 42

3.1 Effect of exposure time on patterning by photolithography 42

3.2 The first isotropic wet etching of silicon dioxide in BHF solution and removing the photoresist mask lines 43

3.3 Varying the distance between silicon nanowires by controlling the width of SiO2 mask line 44

3.3 The first KOH wet etching 45

3.4 Sputtering platinum layer, the removing SiO2 mask and the second KOH etching 46

3.5 Removing platinum layer by wet etching in KOH solution 48

CONCLUSIONS 50

SUGGESTED FURTURE WORKS 51

REFERENCES 52

LIST OF FIGURES

Figure 1 1 Simplified schematics of the SiNW-based (a) resistor and (b) SiNW-based FET to illustrate the differences in the electrical configuration and the way the nanowires are orientated with respect to the electrodes (E) and the source (S) and drain (D) [1] 11Figure 1 2 FESEM images of the surface and tilted cross-section morphology for straight-aligned SiNW arrays with (a) 2, (b) 2.5, and (c) 3 h of metal-assisted electroless etching (MAEE) time (d) Length and top surface density of straight-aligned SiNW arrays with different (MAEE) time [7] 12Figure 1 3 Schematic illustrations of the working system and principle of the SiNW-FET A SiNW-FET is composed of a single SiNW (or a bunch of SiNWs), which is connected between a source (S) and drain (D) electrodes, laid on a Si wafer (a), receptor molecules, immobilized on the SiNW(s), are utilized to recognize specific targets with a SiNW-FET biosensor (b) [12] 13Figure 1 4 Scanning electron micrographs of pristine suspended [4] 15Figure 1 5 Experimental configuration (a), Frequency-modulated phase-locked loop (FM-PLL) scheme (b) [15] 15Figure 1 6 Sketch of α-Si nanowire waveguide (a) and the simulated intensity profile of the light(b) [13] 16Figure 1 7 Fibre butt coupling to Si nanowire waveguide (a), Schematic vertical coupler used to couple light from the fibre into the Si nanowire and vice versa (b) [13] 17Figure 1 8 Ordered silicon nanowire array fabrication scheme The fabrication consisted

of three major steps depicted above: dip coating an n-type silicon wafer in an aqueous suspension of silica beads to get a close-packed monolayer; deep reactive ion etching (DRIE) using the beads as an etch mask to form nanowires; bead removal in HF and boron diffusion to form the radial p-n junction Standard photolithography and metal

sputtering were used for the top finger grid while metal evaporation provided the back contact (not shown) [5] 18Figure 1 9 Horizontal silicon nanowires fabricated by top down fabrication Starting with SOI substrate and etching using anisotropic reactive ion etching (a) Starting with bulk substrate and etching with deep reactive ion etching and subsequent oxidation (b) [1] 19Figure 1 10 The images of overall pattern structure fabricated on the sample (a) and zoom in (b) of the fabricated 65nm nanowire under Al pad layer [3] 20Figure 1 11 A schematic drawing of silicon oxide mask fabricated by SPL on SOI wafer (a), A schematic drawing of profile of silicon nanowire after etching (b), AFM images

of surface topography and profile of silicon oxide mask and silicon nanowire after etching (c) [9] 22Figure 1 12 Cross section image of silicon nanowire on silicon wafer with substrate incline angle 600 (a) and 900 (b) [8] 23Figure 1 13 Fabrication process of single-crystal silicon nanowires by standard photolithography technique and anisotropic wet etching of the single-crystal silicon in KOH solution [10] 24Figure 1 14 Chromium mask three-line array is designed for investigating the fabrication process of single-crystal silicon nanowires (a) The fabrication process of single-crystal silicon nanowires is illustrated in Fig 1 14(b)–(g) Starting with oxidized, photo-lithography and developed (b) Wet undercut etching of SiO2 is carried out in BHF solution(c) The thin photoresist mask layers is bended and then adhered to silicon surface using the capillary force (d) The wet undercut etching of SiO2 is continued to form nanoscale SiO2 mask line patterns (e) Eching in KOH solution (f) Next, the buried oxide layer can be etched in BHF solution(g) [2] 25Figure 1 15 Illustration of progress in creating two nanoscale SiO2 mask lines from one microscale SiO2 mask line (a), schematic diagram for explaining mechanism of creating

two nanoscale SiO2 mask lines(b) - (e) and schematic drawing for explaining intermediate etching process to form two nanoscale SiO2 mask lines from one

microscale SiO2 mask line (f) [2] 26

Figure 1 16 Schematic shows the process steps for the fabrication of silicon nanowire (a)–(e) 3D images of silicon nanowires with a trapezoidal cross-section (top) (f); 3D images of silicon nanowires with a triangular cross-section (bottom) [11] 28

Figure 2 1 Structure of a SOI wafer 30

Figure 2 2 Fabrication process for micro-scale single crystal silicon structure by photolithography and anisotropic wet etching method 31

Figure 2 3 The first fabrication process for single crystal silicon nanowire by sputtering and anisotropic wet etching 32

Figure 2 4 The second fabrication process for single crystal silicon nanowire by sputtering and anisotropic wet etching 33

Figure 2 5 The dimensions of two silicon nanowires, the width of silicon microwires depending on the width of SiO2 mask line (a), The high of silicon nanowires depending on etching time (b) , The distance between two silicon nanowires depending on the width of silicon microwires 34

Figure 2 6 The thickness of silicon dioxide and single crystal silicon after wet oxidation step (b) 35

Figure 2 7 Illustration of geometric pattern on chrome mask (a) and alignment of chrome mask on the (100) wafer 36

Figure 2 8 Coating machine (a) and illustration of spin costing process (b) 36

Figure 2 9 Double-Sid Align system PEM – 800 37

Figure 2 10 Rectangular mask opening aligns in different orientations [3] 39

Figure 2 11 Schematic of KOH wet etching system 40

Figure 2 12 The sputtering system for depositing metal layer on the wafer 41

Figure 3 1 Optical image of patterned photoresist lines after Photolithography process different exposure times, 2.45 s (a) and 2.25 s (b) and image to show uniform photoresist mask lines on wafer-scale (c) 42Figure 3 2 The FESEM images of an array of the single crystal silicon wires transferred from an array of the SiO2 mask lines (a) and magnification image of three SiO2 mask lines (b) 43Figure 3 3 Schematic demonstrates creation of single crystal silicon nanowires with different gaps, D1 (a) and D2 (b) 44Figure 3 4 The FESEM images of silicon dioxide mask lines with different width: 400

nm (a), 350 nm (b) and 50 nm (c) 44Figure 3 5 The SEM images of sample after the first KOH wet etching, line array with different width (a), the lines with higher magnification (b), lines with different width (c), (d) 46Figure 3 6 Optical images of sample before sputtering Pt (a), after sputtering Pt (b), after remove SiO2 mask and etching KOH wet etching (c) 47Figure 3 7 FESEM images shows separation of one single crystal silicon microwires into two: (a) array of microwires and (b) magnification image of separated microwires 48Figure 3 8 FESEM images shows separation of one single crystal silicon microwire into two nanowires: (a) array of separated nanowires; (b), (c), and (d) magnification images

of separated nanowires 49

CHAPTER 1: INTRODUCTION OF SINGLE CRYSTAL

SILICON NANOWIRES

1 Introduction of single crystal silicon nanowire

1.1 What is the nanowire?

A nanowire is a one-dimensional structure with the diameter of less than 100nm The diameter of nanowire can be equal or below the characteristic length scale of many phenomenon: wavelength of light, mean free path of phonon, mean free path of air molecules, etc So, the properties of nanowire materials are significantly different than

in bulk materials For example, the band gap of material can increase and change from indirect band gap to direct band gap The large surface to volume ratio of nanowire is also an interesting property that can be used in sensor applications to enhance the sensitivity of sensor [1] Moreover, the two-dimensional confinement of nanowire can

be used in nanophotonic[14][16], nanoelectronics to conduct photon or electron

Silicon nanowire (SiNW) is one of the most popular and studied nanowire structure

At nanoscale, the band gap of silicon is strongly modified The bulk silicon has indirect band gap In SiNW, the band gap is widened and can become direct for sufficiently small diameter [6]

1.2 Applications of silicon nanowires

1.2.1 In nanosensors

Silicon nanowire is widely used in sensors Based on the electrical characterization, the SiNW based sensors can be classified into two types: SiNW based resistor and SiNW based field effect transistor (FET) [1], shown in Fig.1.1 In Fig.1.1a shows a configuration of the SiNW based resistor In this case, the SiNW acts as a resistor in the circuit When the analyte adsorbed onto the SiNW surface, that changes the surface state,

leads to change in the resistance By using a direction current circuit, the change in the resistance can be measured and the analyte can be detected The sensitivity of sensor can

be increased by used large surface to volume ratio characteristic and strong adsorption for gas of SiNW In Fig.1.1, SiNW array for hydrogen gas sensor was fabricated by top-down method SiNW arrays were formed with nanowire diameters ranging from 20 to

300 nm and lengths proportional to the electroless etching time [7]

Figure 1 1 Simplified schematics of the based (a) resistor and (b) based FET to illustrate the differences in the electrical configuration and the way the nanowires are orientated with respect to the electrodes (E) and the source (S)

SiNW-and drain (D) [1]

In the second case, the SiNW is used to make the conductive channel of FET Fig 1.1b shown a back gate electrode FET that uses highly doped SiNW to connect the source and drain By applying a voltage on the gate electrode, the conduction of SiNW can be changed For high sensitivity, the value of the applied voltage makes FET working in depletion mode and measuring in the sub-threshold regime When the analyte is occurred

in near SiNW surface that leads to change in the local electrical voltage on the SiNW and the extent of depletion also changes If the source-drain applied voltage is fixed, the change in drain current can be used to detect the analyte On other way of detecting the analyte is measuring the adaption of back gate voltage by fixing the source-drain voltage

and drain current In this case, the interactive between analyte and SiNW causes change

in the adaption of the back gate voltage

Figure 1 2 FESEM images of the surface and tilted cross-section morphology for straight-aligned SiNW arrays with (a) 2, (b) 2.5, and (c) 3 h of metal-assisted electroless etching (MAEE) time (d) Length and top surface density of straight -

aligned SiNW arrays with different (MAEE) time [7]

Figure.1.3 shows a schematic of working system and principle of SiNW-FET sensor [14] In Fig.1.3a, a SiNW-FET consists of a SiNW-FET device and a PDMA channel contacted with SiNW-FET to deliver sample The electrical signal wafer gate electrode

is recorded by connecting with a lock-in-amplifier Receptor molecules is fixed on SiNW

to recognize the specific target for SiNW-FET sensor There are two kinds of target: (i) positively charged target and (ii) negatively charged target In the case of SiNW is n-type, when a positively charged target is bound by a receptor molecule, number of holes

in SiNW is increased and the electrical conduction of SiNW is also increased For negatively charged target, it reduces the number of holes leading to an increasing in electrical conduction of SiNW For SiNW, the total surface area is very large that can

achieve very high sensitivity, so SiNW based sensor has potential for single molecule detection applications

Figure 1 3 Schematic illustrations of the working system a nd principle of the

which is connected between a source (S) and d rain (D) electrodes, laid on a Si

wafer (a), receptor molecules, immobilized on the SiNW(s), are

utilized to recognize specific targets with a SiNW -FET biosensor (b) [14]

1.2.2 In mechanical nanoresonators

In recent years, SiNW has been used for very high frequency (VHF) nanoelectromechanical system (NEMS) Nanowire and nanotube based resonator devices prove very high sensitive for mass detection applications [4] The mass resolution can achieve zeptogram (1 zg =10-21 g), resolution shown herein opens many

new possibilities among them is directly “weighing” the inertial mass of individual, electrically neutral macromolecules [19].

The operation of nanomechanical resonator is based on the frequency shift when a particle adsorbing to the resonator The relation between the adsorbed mass m and frequency shift f is   f f o/ 2m om where, fo is the resonant frequency and mo is the initial mass of beam From this equation, we can see, there are two ways to increase the resolution of mass sensor: (i) increasing the resonant frequency of beam, (ii) decreasing the initial mass of beam So, SiNW is suitable for nanomechanical resonator

A problem to very high frequency electrical resonator is excitation and detection For example, when we use capacitive detection for device with dimension of below 100nm, the capacitive of device can be smaller than 10-18 F So, the capacitive detection is hard

to apply for nanomechanical resonator In Fig.1.5, a metallized SiNW resonator with sensitivity about 10 zeptograms was demonstrated [4] The operating frequency is near

200 MHz with quality factor Q = 2000-2500 The SiNW is grown and suspended on two heavily doped supporting pads The cross section of the wire is hexagon and crystal direction along SiNW is <111> direction The wire is excited by Lorentz force An applied magnetic field is perpendicular to the wire When a RF current flows along the wire that causes the wire vibrating with same frequency as the RF current

Figure 1 4 Scanning electron micrographs of pristine suspended [4]

An experimental configuration for mass sensor is shown in Fig.1.5a [5] The experiment is performed at cryogenically cooled and ultrahigh vacuum with base pressure below 10-10 torr A gas nozzle provides a controllable atoms or molecules flux

A shutter is used as a gate to provide calibrated To control the mass flux, the gas flow rate is measured A schematic of frequency-modulated phase-locked (FM-PLL) loop is shown in Fig.1.5b The FM-PLL allows real time mass sensing

Figure 1 5 Experimental configuration (a), Frequency -modulated

phase-locked loop (FM-PLL) scheme (b) [19]

1.2.3 In nanophotonics

Photonic is a technology that uses photon for generating, transmitting, processing and detecting the signal Photonic has applications in a large number of areas, industrial manufacturing, military, entertainment, telecommunication, etc Similar to electronic, reducing dimension of devices is the main issue of photonic In fiber optic communication, the demand for capacity and quality exponentially increases To meet the demand, the wavelength division multiplexing (WDM) technique was developed to increasing the capacity tens or hundred times in optical transmission system[13] With WDM, a single optical fiber can carry multiple signals by using different wavelength of laser light Due to the compatibility of the fabrication technology with micro-electronics, silicon photonics has attracted a lot of interests A search for the high-index contrast waveguide led us to the Si-channel waveguides that consist of a Si core with an extremely small cross section and have a surrounding cladding of SiO2 materials or air

Figure 1 6 Sketch of α-Si nanowire waveguide (a) and the simulated intensity

profile of the light(b) [15]

A -SiNW waveguide is shown in Fig.1.6a The thickness of SiO2 buffer layer is 5 µm

to reduce leaky loss The SiNW is 220 nm thick, 500 nm wide, and lies in the single

mode region In Fig.1.6b, the simulation result of intensity distribution of the propagating electric field is shown for the channel wire waveguide

To couple efficiently the light from fiber cable to waveguide, we can use grating coupler, shown in Fig.1.7 The system is simple that don’t need lenses or focusing grating and the coupling efficiency can reach up to 38%

Figure 1 7 Fibre butt coupling to Si nanowire waveg uide (a), Schematic vertical coupler used to couple light from the fibre into the Si nanowire and vice

versa (b) [15]

Increasing the efficiency of solar cell is very crucial for solar cell applications The

n-p junction based silicon solar cell was develon-ped and has been commercially exn-ploited However, the efficiency is still low at about 20% that cause high cost for silicon solar cell The way to increase the efficiency is improving light scattering and trapping [5] The fabrication method consists of four steps illustrated in Fig.1.8: silica bead synthesis, dip coating to form a self-assembled monolayer of beads on the silicon surface, deep reactive ion etching to form the nanowire array, and diffusion to form the p-n junction

Figure 1 8 Ordered silicon nanowire array fabricati on scheme The fabrication consisted of three major steps depicted above: dip coating an n-type silicon wafer in an aqueous suspension of silica beads to get a close -packed monolayer; deep reactive ion etching (DRIE) using the beads as an etch mask to form nanowires; bead removal in HF and boron diffusion to form the radial p -n junction Standard photolithography and metal sputtering were used for the top finger grid while metal evaporation provi ded the back contact (not shown) [5]

2 Fabrication methods of single crystal silicon nanowire

In the top-down methods, there are two main techniques used for single crystal silicon nanowire fabrication: lithography and etching Lithography patterns mediate structures that are used as a mask for next etching process Lithography technique includes: photolithography, e-beam lithography, ion-beam lithography, scanning probe lithography, self-assembly of nanoparticles In next section, some of lithography techniques will be described

2.1 Photolithography

Photolithography is a convention technique, that is used widely in integrated circuits (ICs) manufacturing In this technique, light illuminates onto a mask and the light passing through the transparent patterns in the mask is focused onto the photoresist layer Feature on the mask will be transferred on the photoresist layer Accompany with physical and chemical processes, nanostructures can be fabricated The dimension of feature on photoresist layer is limited diffraction phenomenon, so many improvements

have been applied to reduce the feature dimension Reducing wavelength of illumination light is mainly used to improve the resolution of photolithography At the first time, the illumination source was mercury lamp with UV wavelength emission at 436nm (G-line) and 365nm (I-line) Later, excimer laser with wavelength at deep UV, 248 nm (KrF excimer laser), and 193 nm (ArF excimer laser) was employed for new illumination light The wavelength continually goes down vacuum UV at 157nm, extremely UV at 13nm, and X-ray at 1nm However, shorter wavelength requires expensive and complex equipment that may not conform to laboratory condition

To overcome the difficulty, photolithography is often combined with etching techniques to obtaining the horizontal single crystal silicon nanowire array The dimension of nanowire can be smaller than the resolution of photolithography Fig.1.9 shows a fabrication process using this combination

Figure 1 9 Horizontal silicon nanowires fabri cated by top down fabrication Starting with SOI substrate and etching using anisotropic reactive ion etching (a) Starting with bulk substrate and etching with deep reactive ion etch ing and

subsequent oxidation (b) [1]

2.2 E-beam and ion-beam lithography

E-beam and ion beam lithography are similar to photolithography, but uses charged particles In the e-beam lithography, the illumination light in photolithography is replaced by an electron-beam A fine electron beam illuminates on energy-sensitive polymer layer such as photoresist layer Structures on energy-sensitive polymer layer is formed by scanning electron-beam on the pattern area The wavelength of e-beam is dependent on energy of electron and it can be much shorter than wavelength of light source above So, it can reach higher resolution than photolithography These structures are used for etching mask in next step

Figure 1 10 The images of overall pattern structure fabricated on the sample (a) and zoom in (b) of the fabricated 65nm nanowire under Al pad layer [3]

In Fig.1.10, 65nm horizontal single crystal nanowire is fabricated on silicon wafer by beam lithography, with aluminum electrode for measuring characteristics of the nanowire The disadvantage of e-beam lithography is low throughput, because it uses only a beam for scanning on substrate So, it is often used in laboratory, or fabricating mask for photolithography

e-Ion-beam lithography, heavier charged particles with more momentum is used So, beam has a higher energy and smaller wavelength than e-beam It is almost no diffraction and reduces scattering on substrate and with residual gas The resolution of ion- beam

ion-lithography can be very high, nanostructures can be formed by removing material directly under effect of high energy ion-beam However, this technique requests very expensive, so

it is very limited in application and not detail mentioned here

2.3 Scanning probe lithography (SPL)

Scanning probe lithography is a technique that is developed from scanning probe microscope It uses interactions between tip and surface sample to change the physical

or chemical characteristics of surface sample Feature can be formed on surface sample

by many mechanisms such as: resist exposure (similar to e-beam lithography), local oxidation, dip-pen, mechanical scratching… In pattern process, diffraction phenomenon can be completely eliminated The most advantage (SPL) is simply and cheap but still reaches very high resolution However, similar to e-beam lithography, the throughput of SPL is very low, so it is almost used in laboratory for research

proposes In figure 1.11, silicon nanowire is fabricated by local oxidation The probe is used to oxidize silicon nearby the tip By scanning the probe, a silicon oxide line is formed that is used as an etching mask to fabricate silicon nanowires [9]

Figure 1 11 A schematic drawing of silicon oxide mask fabricated by SPL on SOI wafer (a), A schematic drawing of profile of silicon nanowire after etching (b), AFM images of surface topography and profile of silicon oxide mask and

silicon nanowire after etching (c) [9]

2.4 Nanofabrication by replication

Nanofabrication by replication is a technique that was recently proposed in 1995 [8]

It uses a mold with nanofeatures pressing into a thin layer of polymer Nanofeatures will

be transferred into the polymer layer After pressing, the polymer layer will be heating treatment or expose to form nanostructures Fabrication process is parallel, so it can reach high throughput The resolution of structure is equivalent with the resolution of mold that can reach sub-100nm by e-beam fabricated mold A nanowire array (figure 1.12 ) was fabricated on silicon wafer by nanoimprint [8] Metal nanodot array using for growing vertical silicon nanowire array was also fabricated by this technique [16]

Figure 1 12 Cross section image of silicon nanowire on silicon wafer with

substrate incline angle 60 0 (a) and 90 0 (b) [8]

2.5 Novel methods based on conventional photolithography

Due to the diffraction limit in photolithography, small size nano-structures are hardly fabricated However, a few novel methods have been developed to fabricate SiNWs using this technique Combining conventional photolithography with wet chemical etching in KOH solution, we can create high aspect ratio SiNWs, owing to its crystal direction dependence of bulk silicon Two simple and cost-effective methods will be described as flows [11]

Here, we report a top-down method for fabricating single-crystal silicon nanowires based on low cost, all-wet chemical etching technology The method employs the standard photolithography technique and anisotropic wet chemical etching of the single-crystal silicon in KOH solution The SiO2 mask lines are patterned by undercut etching using buffered hydrofluoric (BHF) solution The single-crystal silicon nanowires having

25 nm minimum width and 2 cm wafer-scale length, corresponding to an aspect ratio of

8 × 105, are successfully fabricated using the proposed fabrication technology [2] Fabrication process is shown in Fig 1.13 Here, dependence of etching rate on the direction of crystal faces of single-crystal silicon material in KOH anisotropic wet

etchant is used Fabrication process is started from SOI wafer having 340 nm device layer The starting SOI wafer is oxidized for thinning the device layer to a desired thickness We use the thermally formed SiO2 layer as a mask layer for fabricating single-crystal SiNWs The thickness of SiO2 layer can be controlled by repeated oxidization process or thinning process using BHF solution

Figure 1 13 Fabrication process of single -crystal silicon nanowires by standard photolithography technique and anisotropic wet etching of the single -

crystal silicon in KOH solution [10]

Using the conventional photolithography nanowires patterns are defined in shape as shown in Fig.1.13 (a) In order to use photoresist as a mask layer, the photoresist patterns are post-baked in a heating oven at 1200C for 30 min After that isotropic undercut wet-etching property of SiO2 is used to narrow further window mask patterns (Fig.1.13 (b)) After that the photoresist layer is removed The wafer with SiO2 mask patterns is then immerged in the 25% KOH solution at 800C Under the anisotropic etching property of single crystal silicon, nanowires are formed (Fig.1.13 (c)).The cross-section of single crystal SiNWs can be trapezium or triangular This depends on controlled etching time

Next, the buried oxide layer is can be etched in BHF solution to form the structure shown

in Fig.1.13 (d) or free standing single crystal SiNWs [10]

Figure 1 14 Chromium mask three-line array is designed for investigating the fabrication process of single-crystal silicon nanowires (a) The fabrication process of single-crystal silicon nanowires is illustrated in Fig 1 14(b) –(g) Starting with oxidized, photo -lithography and developed (b) Wet undercut etching of SiO 2 is carried out in BHF solution (c) The thin photoresist mask layers is bended and then adhered to sil icon surface using the capillary force (d) The wet undercut etching of SiO 2 is continued to form nanoscale SiO 2 mask line patterns (e) Eching in KOH solution (f) Next, the buried oxide layer can be

etched in BHF solution (g) [2]

Fabrication of Single-Crystal Silicon Nanowires Based on Surface Wet Adhesion In order to obtain high density of SiNWs, another fabrication method has been developed [18] This method uses surface wet adhesion to downscale SiO2 mask lines to widths from 45 nm to 200 nm and length up to 120 µm The interspace between nanoscale SiO

mask lines is 750 nm, which is narrower than the 1.2 µm feature resolution of obtainable photolithography process Then, single-crystal SiNWs are fabricated by transferring the nanoscale SiO2 mask line patterns into the top silicon layer of SOI wafer by KOH anisotropic wet-chemical etching The fabrication process of single-crystal silicon nanowires is schematically shown in Fig.1 14 (b)–(g) [2]

Figure 1 15 Illustration of progress in creating two nanoscale SiO 2 mask lines from one microscale SiO 2 mask line (a), schematic diagram for explaining mechanism of creating two nanoscale SiO 2 mask lines(b) - (e) and schematic drawing for explaining intermediate etching pr ocess to form two nanoscale SiO 2

mask lines from one microscale SiO 2 mask line (f) [2]

In order to explain for the creation of two nanoscale SiO2 mask lines from one microscale SiO2 mask line (Fig.1 15) States 1, 2, and 3 show the microscale SiO2 mask line before separation, partially separated, and completely separated into two SiO2 mask lines, respectively When the undercut etching process achieves a state as shown in Fig.1

15 (b), under the capillary force, the thin photoresist film is bent and then adheres to the