algorithms for vlsi physical design automation (3rd ed ) sherwani 1998 11 30 Cấu trúc dữ liệu và giải thuật

VLSI Design Cycle New Trends in VLSI Design Cycle Physical Design Cycle New Trends in Physical Design Cycle Comparison of Different Design Styles 1.6 System Packaging Styles 1.6.1 Die Pa

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Naveed A Sherwani

Intel Corporation.

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VLSI Design Cycle

New Trends in VLSI Design Cycle

Physical Design Cycle

New Trends in Physical Design Cycle

Comparison of Different Design Styles

1.6 System Packaging Styles

1.6.1 Die Packaging and Attachment Styles

1.6.1.11.6.1.2

Die Package StylesPackage and Die Attachment Styles1.6.2

39

40434345

2 Design and Fabrication of VLSI Devices

Static Random Access Memory (SRAM)Dynamic Random Access Memory (DRAM)

Status of Fabrication Process

3.2.1 Comparison of Fabrication Processes

3.3 Issues related to the Fabrication Process

Yield and Fabrication Costs

3.4 Future of Fabrication Process

3.4.1

3.4.2

3.4.3

SIA RoadmapAdvances in LithographyInnovations in Interconnect3.4.3.1

3.4.3.23.4.3.33.4.3.4

More Layers of MetalLocal InterconnectCopper InterconnectUnlanded Vias3.4.4

3.4.5

3.4.6

Innovations/Issues in DevicesAggressive Projections for the ProcessOther Process Innovations

3.4.6.13.4.6.2

Silicon On InsulatorSilicon Germaniun

3.5

3.6

3.7

3.8

Solutions for Interconnect Issues

Tools for Process Development

Summary

Exercises

4648515353586262646667697171

75

76777779798081828282838585868787878788888990909091939494

Graph Search AlgorithmsSpanning Tree AlgorithmsShortest Path AlgorithmsMatching AlgorithmsMin-Cut and Max-Cut AlgorithmsSteiner Tree Algorithms

4.3.2 Computational Geometry Algorithms

4.3.2.14.3.2.2

Line Sweep MethodExtended Line Sweep Method

4.4 Basic Data Structures

4.5 Graph Algorithms for Physical design

4.5.1 Classes of Graphs in Physical Design

4.5.1.14.5.1.2

Graphs Related to a Set of LinesGraphs Related to Set of Rectangles4.5.2

4.5.3

4.5.4

Relationship Between Graph ClassesGraph Problems in Physical DesignAlgorithms for Interval Graphs4.5.4.1

4.5.4.2

Maximum Independent SetMaximum Clique and Minimum Coloring4.5.5 Algorithms for Permutation Graphs

4.5.5.14.5.5.2

Maximum Independent Set

Maximum -Independent Set

4.5.6 Algorithms for Circle Graphs

4.5.6.14.5.6.24.5.6.3

Maximum Independent Set

Maximum -Independent Set

Classification of Partitioning Algorithms

Group Migration Algorithms

5.3.1

5.3.2

Kernighan-Lin AlgorithmExtensions of Kernighan-Lin Algorithm5.3.2.1

5.3.2.25.3.2.35.3.2.4

Fiduccia-Mattheyses AlgorithmGoldberg and Burstein AlgorithmComponent Replication

5.5 Other Partitioning Algorithms

5.5.1 Metric Allocation Method

6 Floorplanning and Pin Assignment 191

7.3.5 Comparison of Simulation Based Algorithms

7.4 Partitioning Based Placement Algorithms

7.4.1

7.4.2

Breuer’s AlgorithmTerminal Propagation Algorithm

7.5 Other Placement Algorithms

8 Global Routing 247

8.1 Problem Formulation

8.1.1 Design Style Specific Global Routing Problems

2532578.2 Classification of Global Routing

8.4

8.5

8.6

Line-Probe Algorithms

Shortest Path Based Algorithms

Steiner Tree based Algorithms

8.7 Integer Programming Based Approach

9.3

Classification of Routing Algorithms

Single-Layer Routing Algorithms

9.3.1 General River Routing Problem

9.3.1.1 General River Routing Algorithm9.3.2 Single Row Routing Problem

9.3.2.19.3.2.29.3.2.39.3.2.4

Origin of Single Row Routing

A Graph Theoretic ApproachAlgorithm for Street Congestion MinimizationAlgorithm for Minimizing Doglegs

9.4 Two-Layer Channel Routing Algorithms

Basic Left-Edge AlgorithmDogleg Router

Symbolic Channel Router: YACR29.4.3 Constraint Graph based Routing Algorithms

9.4.3.19.4.3.2

Net Merge Channel RouterGlitter: A Gridless Channel Router9.4.4

9.4.5

9.4.6

Greedy Channel RouterHierarchical Channel RouterComparison of Two-Layer Channel Routers

9.5 Three-Layer Channel Routing Algorithms

9.6

9.7

Multi-Layer Channel Routing Algorithms

Switchbox Routing Algorithms

9.8

9.9

Summary

Exercises

417

418419422423426427427428429430432433436439439440444444

10.1.5 Performance Driven Over-the-cell Routing

10.2 Via Minimization

10.2.1 Constrained Via Minimization Problem

10.2.1.1 Graph Representation of Two-Layer CVM

Prob-lem

10.2.2 Unconstrained Via Minimization

10.2.2.110.2.2.210.2.2.3

Optimal Algorithm for Crossing-Channel TVMProblem

Approximation Result for General k-TVM

11.1.3.1 Design Style Specific Problems11.1.4 Clock Routing Algorithms

11.1.4.111.1.4.211.1.4.311.1.4.411.1.4.511.1.4.6

H-tree Based AlgorithmThe MMM AlgorithmGeometric Matching based AlgorithmWeighted Center Algorithm

Exact Zero Skew AlgorithmDME Algorithm

480485485489490492493494496497

501

502505507510512512513514

12.1.1 Design Style Specific Compaction Problem

Constraint Graph GenerationCritical Path AnalysisWire Jogging

Wire Length Minimization12.3.2 Virtual Grid Based Compaction

12.3.2.112.3.2.212.3.2.3

Basic Virtual Grid AlgorithmSplit Grid CompactionMost Recent Layer Algorithm12.4

12.5

CompactionTwo-Dimensional Compaction

12.5.1 Simulated Annealing based Algorithm

12.6 Hierarchical Compaction

12.6.1 Constraint-Graph Based Hierarchical Compaction

12.7 Recent trends in compaction

12.7.1

12.7.2

Performance-driven compactionCompaction techniques for yield enhancement12.8

13.4.2.2

Basic AlgorithmRouting Algorithm for Staggered Model13.5

14.5.1 Classification of MCM Routing Algorithms

Bibliography 525

Author Index 563 Subject Index 567

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performance and low per-unit cost leads to the very pervasive introduction ofintegrated circuit chips to many aspects of modern engineering and scientificendeavors including computations, telecommunications, aeronautics, genetics,bioengineering, manufacturing, factory automation, and so on It is clear thatthe integrated circuit chip will play the role of a key building block in the

information society of the twenty-first century.

The manufacture of integrated circuit chips is similar to the manufacture

of other highly sophisticated engineering products in many ways The three

major steps are designing the product, fabricating the product, and testing the

fabricated product In the design step, a large number of components are to

be designed or selected, specifications on how these components should be sembled are to be made, and verification steps are to be carried out to assurethe correctness of the design In the manufacturing step, a great deal of man-power, and a large collection of expensive equipment, together with painstakingcare are needed to assemble the product according to the design specification.Finally, the fabricated product must be tested to check its physical function-ality As in all engineering problems, there are conflicting requirements in allthese steps In the design step, we want to obtain an optimal product design,and yet we also want the design cycle to be short In the fabrication step, wewant the product yield to be high, and yet we also need to be able to produce

as-a las-arge volume of the product as-and get them to mas-arket in time In the testingstep, we want the product to be tested thoroughly and yet we also want to beable to do so quickly

The title of this book reveals how the issue of enormous design complexity

is to be handled so that high quality designs can be obtained in a

reason-able amount of design time: We use muscles (automation) and we use brain

(algorithms) Professor Sherwani has written an excellent book to introduce

students in computer science and electrical engineering as well as CAD neers to the subject of physical design of VLSI circuits Physical design is akey step in the design process Research and development efforts in the lasttwenty years have led us to some very good understanding on many of theimportant problems in physical design Professor Sherwani’s book provides atimely, up-to-date integration of the results in the field and will be most usefulboth as a graduate level textbook and as a reference for professionals in thefield All aspects of the physical design process are covered in a meticulousand comprehensive manner The treatment is enlightening and enticing Fur-thermore, topics related to some of the latest technology developments such asField Programmable Gate Arrays (FPGA) and Multi-Chip Modules (MCM)are also included A strong emphasis is placed on the algorithmic aspect ofthe design process Algorithms are presented in an intuitive manner withoutthe obscurity of unnecessary formalism Both theoretical and practical aspects

engi-of algorithmic design are stressed Neither the elegance engi-of optimal algorithmsnor the usefulness of heuristic algorithms are overlooked ¿From a pedagogicalpoint of view, the chapters on electronic devices and on data structures and ba-sic algorithms provide useful background material for students from computerscience, computer engineering, and electrical engineering The many exercisesincluded in the book are also most helpful teaching aids

This is a book on physical design algorithms Yet, this is a book thatgoes beyond physical design algorithms There are other important designsteps of which our understanding is still quite limited Furthermore, develop-ment of new materials, devices, and technologies will unquestionably create newproblems and new avenues of research and development in the design process

An algorithmic outlook on design problem and the algorithmic techniques forsolving complex design problems, which a reader learns through the examplesdrawn from physical design in this book, will transcend the confine of physicaldesign and will undoubtedly prepare the reader for many of the activities inthe field of computer-aided design of VLSI circuits I expect to hear from manystudents and CAD professionals in the years to come that they have learned agreat deal about physical design, computer-aided design, and scientific researchfrom Professor Sherwani’s book I also expect to hear from many of them thatProfessor Sherwani’s book is a source of information as well as a source of in-spiration

Urbana-Champaign, September 1992 C L Liu

development of Physical Design (PD) Automation tools In the last two decades,the research in physical design automation has been very intense, and literallythousands of research articles covering all phases of physical design automationhave been published The development of VLSI physical design automation alsodepends on availability of trained manpower We have two types of studentsstudying VLSI physical design: students preparing for a research career andstudents preparing for a career in industry Both types of students need tobuild a solid background However, currently we lack courses and text bookswhich give students a comprehensive background It is common to find stu-dents doing research in placement, but are unaware of the latest developments

in compaction Those students seeking careers in industry will find that theVLSI physical design industry is very fast paced They are expected to be con-versant with existing tools and algorithms for all the stages of the design cycle

of a VLSI chip In industry, it is usual to find CAD engineers who work on oneaspect of physical design and lack knowledge of other aspects For example,

a CAD engineer working in the development of detailed routers may not beknowledgeable about partitioning algorithms This is again due to the lack

of comprehensive textbooks which cover background material in all aspects ofVLSI physical design

Providing a comprehensive background in one textbook in VLSI physicaldesign is indeed difficult This is due to the fact that physical design automa-tion requires a mix of backgrounds Some electrical engineering and a solidundergraduate computer science background is necessary to grasp the funda-mentals In addition, some background in graph theory and combinatorics isalso needed, since many of the algorithms are graph theoretic or use othercombinatorial optimization techniques This mix of backgrounds has perhaps

restricted the development of courses and textbooks in this very area

This book is an attempt to provide a comprehensive background in theprinciples and algorithms of VLSI physical design The goal of this book is toserve as a basis for the development of introductory level graduate courses inVLSI physical design automation It is hoped that the book provides self con-tained material for teaching and learning algorithms of physical design Allalgorithms which are considered basic have been included The algorithms arepresented in an intuitive manner, so that the reader can concentrate on thebasic idea of the algorithms Yet, at the same time, enough detail is provided

so that readers can actually implement the algorithms given in the text anduse them

This book grew out of a graduate level class in VLSI physical design tomation at Western Michigan University Initially written as a set of classnotes, the book took form as it was refined over a period of three years

au-Overview of the Book

This book covers all aspects of physical design The first three chaptersprovide the background material, while the focus of each chapter of the rest

of the book is on each phase of the physical design cycle In addition, newertopics like physical design automation of FPGAs and MCMs have also beenincluded

In Chapter 1, we give an overview of the VLSI physical design automationfield Topics include the VLSI design cycle, physical design cycle, design stylesand packaging styles The chapter concludes with a brief historical review ofthe field

Chapter 2 discusses the fabrication process for VLSI devices It is important

to understand the fabrication technology in order to correctly formulate theproblems In addition, it is important for one to understand, what is doableand what is not! Chapter 2 presents fundamentals of MOS and TTL transistors

It then describes simple NAND and NOR gates in nMOS and CMOS

Chapter 3 presents the status of fabrication process, as well as, processinnovations on the horizons and studies its impact on physical design We alsodiscuss several other factors such as design rules, yield, delay, and fabricationcosts involved in the VLSI process

Basic material on data structures and algorithms involved in the physicaldesign is presented in Chapter 4 Several different data structures for layouthave been discussed Graphs which are used to model several different problems

in VLSI design are defined and basic algorithms for these graphs are presented.Chapter 5 deals with partitioning algorithms An attempt has been made

to explain all the possible factors that must be considered in partitioning theVLSI circuits Group migration, simulated annealing and simulated evolutionalgorithms have been presented in detail The issue of performance drivenpartitioning is also discussed

In Chapter 6, we discuss basic algorithms for floorplanning and pin ment Several different techniques for placement such as, simulated annealing,

Chapter 10 discusses two ways of improving layouts after detailed routing,namely, via minimization and over-the-cell routing Basic algorithms for viaminimization are presented Over-the-cell routing is a relatively new techniquefor reducing routing areas We present the two latest algorithms for over-the-cell routing

The problems of routing clock and power/ground nets are discussed inChapter 11 These topics play a key role in determining the layout of highperformance systems Circuit compaction is discussed in Chapter 12 One di-mensional compaction, as well as two dimensional compaction algorithms arepresented

Field Programmable Gate Arrays (FPGAs) are rapidly gaining ground inmany applications, such as system prototyping In Chapter 13, we discussphysical design automation problems and algorithms for FPGAs In particular,

we discuss the partitioning and routing problems in FPGAs Both of theseproblems are significantly different from problems in VLSI Many aspects ofphysical design of FPGAs remain a topic of current research

Multi-Chip Modules (MCMs) are replacing conventional printed circuitboards in many applications MCMs promise high performance systems at

a lower cost In Chapter 14, we explore the physical design issues in MCMs Inparticular, the routing problem of MCMs is a true three dimensional problem.MCMs are currently a topic of intense research

At the end of each chapter, a list of exercises is provided, which range incomplexity from simple to research level Unmarked problems and algorithmsare the simplest The exercises marked with (†) are harder and algorithms inthese exercises may take a significant effort to implement The exercises andalgorithms marked with (‡) are the hardest In fact, some of these problemsare research problems

Bibliographic notes can be found at the end of each chapter In these notes,

we give pointers to the readers for advanced topics An extensive bibliography

is presented at the end of the text This bibliography is complete, to the best

of our knowledge, up to the September of 1998 An attempt has been made toinclude all papers which are appropriate for the targeted readers of this text.The readers may also find the author and the subject index at the back of thetext

Overview of the Second Edition

In 1992, when this book was originally published, the largest microprocessorhad one million transistors and fabrication process had three metal layers Wehave now moved into a six metal layer process and 15 million transistor micro-processors are already in advanced stages of design The designs are movingtowards a 500 to 700 Mhz frequency goal This challenging frequency goal, aswell as, the additional metal layers have significantly altered the VLSI field.Many issues such as three dimensional routing, Over-the-Cell routing, earlyfloorplanning have now taken a central place in the microprocessor physicaldesign flow This changes in the VLSI design prompted us to reflect these inthe book That gave birth to the idea of the second edition

The basic purpose of the second edition is to introduce a more realistic

picture to the reader exposing the concerns facing the VLSI industry whilemaintaining the theoretical flavor of the book New material has been added

to all the chapters Several new sections have been added to many chapters.Few chapters have been completely rewritten New figures have been added tosupplement the new material and clarify the existing material

In summary, I have made an attempt to capture the physical design flowused in the industry and present it in the second addition I hope that readerswill find that information both useful and interesting

Overview of the Third Edition

In 1995, when we prepared the 2nd edition of this book, a six metal layerprocess and 15 million transistor microprocessors were in advanced stages ofdesign In 1998, six metal process and 20 million transistor designs are in pro-duction Several manufacturers have moved to 0.18 micron process and copperinterconnect One company has announced plans for 0.10 micron process andplans to integrate 200 to 400 million transistors on a chip Operating frequencyhas moved from 266 Mhz (in 1995) to 650 Mhz and several Ghz experimentalchips have been demonstrated Interconnect delay has far exceeded device de-lay and has become a dominant theme in physical design Process innovations

such as copper, low k dielectrics, multiple threshold devices, local interconnect

are once again poised to change physical design once again

The basic purpose of the third edition is to investigate the new challengespresented by interconnect and process innovations In particular, we wanted toidentify key problems and research areas that physical design community needs

to invest in order to meet the challenges We took a task of presenting thoseideas while maintaining the flavor of the book As a result, we have added twonew chapters and new material has been added to most of the chapters A newchapter on process innovation and its impact on physical design has been added.Another focus of the book has been to promote use of Internet as a resource,

so wherever possible URLs has been provided for further investigation.Chapters 1 and 2 have been updated Chapter 3 is a new chapter on thefabrication process and its impact Chapter 4 (algorithms) and Chapter 5

sively and many new items have been added.

In summary, I have made an attempt to capture the impact of interconnectand process innovations on physical design flow I have attempted to balancematerial on new innovations with the classical content of the 2nd edition Ihope that readers will find that information both useful and interesting

To the Teacher

This book has been written for introductory level graduate students Itpresents concepts and algorithms in an intuitive manner Each chapter contains

3 to 4 algorithms that have been discussed in detail This has been done so as

to assist students in implementing the algorithms Other algorithms have beenpresented in a somewhat shorter format References to advanced algorithmshave been presented at the end of each chapter Effort has been made to makethe book self contained

This book has been developed for a one-semester or a two-semester course

in VLSI physical design automation In a one-semester course, it is mended that chapters 8, 9, 11, and 12 be omitted A half-semester algorithmdevelopment project is highly recommended Implementation of algorithms is

recom-an importrecom-ant tool in making students understrecom-and algorithms In physical sign, the majority of the algorithms are heuristic in nature and testing of thesealgorithms on benchmarks should be stressed In addition, the development ofpractical algorithms must be stressed, that is, students must be very aware ofthe complexity of the algorithms An optimal algorithm may be imprac-tical for an input of size 10 million Several (†) marked problems at the end ofeach chapter may serve as mini-projects

de-In a two-semester class, it is recommended that all the chapters be included.Reading state-of-art papers must be an integral part of this class In particular,students may be assigned papers from proceedings of DAC and ICCAD orfrom IEEE Transactions on CAD Papers from Transactions typically require

a little more mathematical maturity than the papers in DAC and ICCAD Animportant part of this class should be a two-semester project, which may bethe development of a new algorithm for some problem in physical design Atypical first part of the project may involve modifying an existing algorithmfor a special application Some (‡) problems may serve as projects

In both the courses, a good background in hand layout is critical It is

expected that students will have access to a layout editor, such as MAGIC orLEDIT It is very important that students actually layout a few small circuits.For examples see exercises at the end of Chapter 2

For faculty members, a teaching aid package, consisting of a set of 400 heads (foils) is available from the author These are quite helpful in teachingthe class, as all the important points have been summarized on section by sec-tion basis In order to obtain these foils, please send an email (or a mail) tothe author, at the address below

over-To the Student

First and foremost, I hope that you will enjoy reading this book Everyeffort has been made to make this book easy to read The algorithms havebeen explained in an intuitive manner The idea is to get you to develop newalgorithms at the end of the semester The book has been balanced to give

a practical as well as a theoretical background In that sense, you will find

it useful, if you are thinking about a career in industry or if you are thinkingabout physical design as a possible graduate research topic

What do you need to start reading this book? Some maturity in generalalgorithm techniques and data structures is assumed Some electrical engi-neering background and mathematics background will be helpful, although notnecessary The book is self-contained to a great extent and does not need anysupporting text or reference text

If you are considering a career in this field, I have one important piece ofadvise for you Research in this field moves very fast As a result, no textbookcan replace state-of-the-art papers It is recommended that you read papers

to keep you abreast of latest developments A list of conference proceedingsand journals appears in the bibliographic notes of Chapter 1 I also recom-mend attending DAC and ICCAD conferences every year and a membership inACM/SIGDA, IEEE/DATC and IEEE/TC-VLSI

To the CAD Professional

This book provides a detailed description of all aspects of physical designand I hope you have picked up this book to review your basics of physical de-sign While it concentrates on basic algorithms, pointers are given to advancedalgorithms as well The text has been written with a balance of theory andpractice in mind You will also find the extensive bibliography useful for findingadvanced material on a topic

Errors and Omissions

No book is free of errors and omissions Despite our best attempt, thistext may contain some errors If you find any errors or have any constructivesuggestions, I would appreciate receiving your comments and suggestions Inparticular, new exercises would certainly be very helpful You can mail your

feel free to remind me.

This book was typeset in Latex Figures were made using ‘xfig’ and serted directly into the text as ps files using ‘transfig’ The bibliography wasgenerated using Bibtex and the index was generated with a program written

in-by Siddharth Bhingarde

Portland, March, 1998 Naveed A Sherwani

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member of nitegroup, Timothy Strunk, who made (almost) all the figures inthe text and brought enthusiasm to the team Thanks are also due to AnandPanyam, Konduru Nagesh and Aizaz Manzar for helping in the final stages ofthis project Many students in my class CS520 (Introduction to VLSI designautomation) suffered through earlier version of this book, and I would like tothank them for their constructive suggestions.

Several colleagues and friends contributed significantly by reviewing severalchapters and using parts of the book in their courses In this regard, I wouldlike to thank Jeff Banker, Ajay Gupta, Mark Kerstetter, Sartaj Sahni, andJason Cong I would also like to especially thank Dinesh Mehta and Si-QingZheng I wish to express my sincere thanks to Malgorzata Marek-Sadowska,who made very critical remarks and contributions to the improvement in thequality of the text

Thanks are due to two special people, who have contributed very generously

in my career and helped in many ways I would like to thank Vishwani Agrawaland C L Liu for their constant encouragement and sound words of advise

I would like to thank several different organizations who have contributeddirectly to this project First, I would like to thank Ken Wan, and the rest

of the CTS group at Advanced Micro Devices for helping with many technicaldetails I would also like to thank ACM SIGDA for supporting our researchduring the last four years Thanks are also due to Western Michigan University,and in particular Donald Nelson and Douglas Ferraro, who, despite all costs,made the necessary facilities available to complete this book The NationalScience Foundation deserves thanks for supporting the VLSI laboratory andour research at Western Michigan University I would also like to thank RezaRashidi and the staff of FRC laboratory for their help in printing the text and

Finally, I wish to thank my parents and my family for supporting methroughout my life and for being there when I needed them They suffered

as I neglected many social responsibilities to complete this book

Kalamazoo, September, 1992 Naveed A Sherwani

The second edition project would not have been possible without the help ofSiddharth Bhingarde, Aman Sureka, Rameshwar Donakanti and Anand Pa-nyam In particular, Siddharth worked with me for many many nights on thisproject I am very grateful to these individuals for their help.

Several of my colleagues at Intel helped as reviewers of the chapters Inthis regard, I would like to thank Marc Rose, John Hansen, Dave Ackley, MikeFarabee, and Niraj Bindal

Several friends and family members helped by being copy editors SabahatNaveed, Shazia Asif and Akram Sherwani helped by editing many revisions.Internet played a key role, as many of these revisions were done in Pakistanand then emailed to me

I would like to thank Intel Corporation for helping me with this project Inparticular, I would like to thank Atiq Bajwa for making the time available for

me to complete the project

Portland, March, 1995 Naveed A Sherwani

Acknowledgments for the Third Edition

The third edition would not have been possible without the help of FaranRafiq, Srinivasa Danda, Siddharth Bhingarde, Niraj Bindal, Prashant Saxena,Peichen Pan and Anand Panyam I am very grateful to these individuals fortheir help In particular, I am indebted to Faran Rafiq, who worked tirelesswith me and this project would not have been possible without his dedicationand hard work

I would like to thank Intel Corporation for helping me with the third edition

In particular, I would like to thank Manpreet Khaira for the Research andDevelopment environment, which has helped mature many ideas

I must thank my copy editor Tawni Schlieski, who very carefully read thenew chapters and turned them around in a very short time I am very thankful

to Carl Harris, editor at Kluwer Academic Publishers for encouraging me towrite the third edition

Finally, I am very thankful to my wife Sabahat and my daughter Aysel fortheir encouragement and support

Portland, September, 1998 Naveed A Sherwani

perspective of work, life at home and provided new tools for entertainment Theinternet has emerged as a medium to distribute information, communication,event planning, and conducting E-commerce The revolution is based on com-puting technology and communication technology, both of which are driven by

a revolution in Integrated Circuit (IC) technology ICs are used in computersfor microprocessor, memory, and interface chips ICs are also used in computernetworking, switching systems, communication systems, cars, airplanes, evenmicrowave ovens ICs are now even used in toys, hearing aids and implantsfor human body MEMs technology promises to develop mechanical devices

on ICs thereby enabling integration of mechanical and electronic devices on aminiature scale Many sensors, such as acceleration sensors for auto air bags,along with conversion circuitry are built on a chip This revolutionary devel-opment and widespread use of ICs has been one of the greatest achievements

of humankind

IC technology has evolved in the 1960s from the integration of a few

transis-tors (referred to as Small Scale Integration (SSI))o the integration of millions

of transistors in Very Large Scale Integration (VLSI) chips currently in use.

Early ICs were simple and only had a couple of gates or a flip-flop Some ICswere simply a single transistor, along with a resistor network, performing alogic function In a period of four decades there have been four generations

of ICs with the number of transistors on a single chip growing from a few toover 20 million It is clear that in the next decade, we will be able to buildchips with billions of transistors running at several Ghz We will also be able

to build MEM chips with millions of electrical and mechanical devices Suchchips will enable a new era of devices which will make such exotic applications,such as tele-presence, augumented reality and implantable and wearable com-puters, possible Cost effective world wide point-to-point communication will

be common and available to all

2 Chapter 1 VLSI Physical Design Automation

This rapid growth in integration technology has been (and continues to be)made possible by the automation of various steps involved in the design andfabrication of VLSI chips Integrated circuits consist of a number of electroniccomponents, built by layering several different materials in a well-defined fash-

ion on a silicon base called a wafer The designer of an IC transforms a circuit description into a geometric description, called the layout A layout consists

of a set of planar geometric shapes in several layers The layout is checked

to ensure that it meets all the design requirements The result is a set of sign files that describes the layout An optical pattern generator is used toconvert the design files into pattern generator files These files are used to

de-produce patterns called masks During fabrication, these masks are used to

pattern a silicon wafer using a sequence of photo-lithographic steps The ponent formation requires very exacting details about geometric patterns andthe separation between them The process of converting the specification of

com-an electrical circuit into a layout is called the physical design process Due to

the tight tolerance requirements and the extremely small size of the individualcomponents, physical design is an extremely tedious and error prone process.Currently, the smallest geometric feature of a component can be as small as0.25 micron (one micron, written as is equal to ) For the sake

of comparison, a human hair is in diameter It is expected that thefeature size can be reduced below 0.1 micron within five years This small fea-ture size allows fabrication of as many as 200 million transistors on a 25 mm ×

25 mm chip Due to the large number of components, and the exacting detailsrequired by the fabrication process, physical design is not practical without thehelp of computers As a result, almost all phases of physical design extensivelyuse Computer Aided Design (CAD) tools, and many phases have already beenpartially or fully automated

VLSI Physical Design Automation is essentially the research, developmentand productization of algorithms and data structures related to the physicaldesign process The objective is to investigate optimal arrangements of devices

on a plane (or in three dimensions) and efficient interconnection schemes tween these devices to obtain the desired functionality and performance Sincespace on a wafer is very expensive real estate, algorithms must use the spacevery efficiently to lower costs and improve yield In addition, the arrangement

be-of devices plays a key role in determining the performance be-of a chip rithms for physical design must also ensure that the layout generated abides

Algo-by all the rules required Algo-by the fabrication process Fabrication rules establishthe tolerance limits of the fabrication process Finally, algorithms must be effi-cient and should be able to handle very large designs Efficient algorithms notonly lead to fast turn-around time, but also permit designers to make iterativeimprovements to the layouts The VLSI physical design process manipulatesvery simple geometric objects, such as polygons and lines As a result, physi-cal design algorithms tend to be very intuitive in nature, and have significantoverlap with graph algorithms and combinatorial optimization algorithms Inview of this observation, many consider physical design automation the study

of graph theoretic and combinatorial algorithms for manipulation of geometric

In this chapter, we present an overview of the fundamental concepts ofVLSI physical design automation Section 1.1 discusses the design cycle of aVLSI circuit New trends in the VLSI design cycle are discussed in Section 1.2.

In Section 1.3, different steps of the physical design cycle are discussed Newtrends in the physical design cycle are discussed in Section 1.4 Different designstyles are discussed in Section 1.5 and Section 1.6 presents different packagingstyles Section 1.7 presents a brief history of physical design automation andSection 1.8 lists some existing design tools

1.1 VLSI Design Cycle

The VLSI design cycle starts with a formal specification of a VLSI chip,follows a series of steps, and eventually produces a packaged chip A typicaldesign cycle may be represented by the flow chart shown in Figure 1.1 Ouremphasis is on the physical design step of the VLSI design cycle However, togain a global perspective, we briefly outline all the steps of the VLSI designcycle

1.

2.

System Specification: The first step of any design process is to lay down

the specifications of the system System specification is a high level resentation of the system The factors to be considered in this processinclude: performance, functionality, and physical dimensions (size of thedie (chip)) The fabrication technology and design techniques are alsoconsidered The specification of a system is a compromise between mar-ket requirements, technology and economical viability The end resultsare specifications for the size, speed, power, and functionality of the VLSIsystem

rep-Architectural Design: The basic architecture of the system is designed

in this step This includes, such decisions as RISC (Reduced InstructionSet Computer) versus CISC (Complex Instruction Set Computer), num-ber of ALUs, Floating Point units, number and structure of pipelines,and size of caches among others The outcome of architectural design

is a Micro-Architectural Specification (MAS) While MAS is a textual(English like) description, architects can accurately predict the perfor-mance, power and die size of the design based on such a description

4 Chapter 1 VLSI Physical Design Automation

Such estimates are based on the scaling of existing design or components

of existing designs Since many designs (especially microprocessors) arebased on modifications or extensions to existing designs, such a methodcan provide fairly accurate early estimates These early estimates arecritical to determine the viability of a product for a market segment Forexample, for mobile computing (such as lap top computer), low powerconsumption is a critical factor, due to limited battery life Early esti-mates based on architecture can be used to determine if the design islikely to meet its power spec

3.

4.

5.

Behavioral or Functional Design: In this step, main functional units

of the system are identified This also identifies the interconnect quirements between the units The area, power, and other parameters

re-of each unit are estimated The behavioral aspects re-of the system areconsidered without implementation specific information For example, itmay specify that a multiplication is required, but exactly in which modesuch multiplication may be executed is not specified We may use a va-riety of multiplication hardware depending on the speed and word sizerequirements The key idea is to specify behavior, in terms of input,output and timing of each unit, without specifying its internal structure.The outcome of functional design is usually a timing diagram or otherrelationships between units This information leads to improvement ofthe overall design process and reduction of the complexity of subsequentphases Functional or behavioral design provides quick emulation of thesystem and allows fast debugging of the full system Behavioral design islargely a manual step with little or no automation help available

Logic Design: In this step the control flow, word widths, register

allo-cation, arithmetic operations, and logic operations of the design thatrepresent the functional design are derived and tested This description

is called Register Transfer Level (RTL) description RTL is expressed

in a Hardware Description Language (HDL), such as VHDL or Verilog.This description can be used in simulation and verification This de-scription consists of Boolean expressions and timing information TheBoolean expressions are minimized to achieve the smallest logic designwhich conforms to the functional design This logic design of the system

is simulated and tested to verify its correctness In some special cases,

logic design can be automated using high level synthesis tools These tools

produce a RTL description from a behavioral description of the design

Circuit Design: The purpose of circuit design is to develop a circuit

rep-resentation based on the logic design The Boolean expressions are verted into a circuit representation by taking into consideration the speed

con-and power requirements of the original design Circuit Simulation is used

to verify the correctness and timing of each component The circuit design

is usually expressed in a detailed circuit diagram This diagram showsthe circuit elements (cells, macros, gates, transistors) and interconnec-

6 Chapter 1 VLSI Physical Design Automation

tion between these elements This representation is also called a netlist Tools used to manually enter such description are called schematic cap-

ture tools In many cases, a netlist can be created automatically from

logic (RTL) description by using logic synthesis tools.

6.

7.

Physical Design: In this step the circuit representation (or netlist) is

converted into a geometric representation As stated earlier, this

geo-metric representation of a circuit is called a layout Layout is created by

converting each logic component (cells, macros, gates, transistors) into ageometric representation (specific shapes in multiple layers), which per-form the intended logic function of the corresponding component Con-nections between different components are also expressed as geometricpatterns typically lines in multiple layers The exact details of the layoutalso depend on design rules, which are guidelines based on the limitations

of the fabrication process and the electrical properties of the fabricationmaterials Physical design is a very complex process and therefore it isusually broken down into various sub-steps Various verification and val-idation checks are performed on the layout during physical design Inmany cases, physical design can be completely or partially automated

and layout can be generated directly from netlist by Layout Synthesis

tools Most of the layout of a high performance design (such as a processor) may be done using manual design, while many low to mediumperformance design or designs which need faster time-to-market may bedone automatically Layout synthesis tools, while fast, do have an areaand performance penalty, which limit their use to some designs Man-ual layout, while slow and manually intensive, does have better area andperformance as compared to synthesized layout However this advan-tage may dissipate as larger and larger designs may undermine humancapability to comprehend and obtain globally optimized solutions

micro-Fabrication: After layout and verification, the design is ready for

fabri-cation Since layout data is typically sent to fabrication on a tape, the

event of release of data is called Tape Out Layout data is converted (or

fractured) into photo-lithographic masks, one for each layer Masks tify spaces on the wafer, where certain materials need to be deposited,diffused or even removed Silicon crystals are grown and sliced to pro-duce wafers Extremely small dimensions of VLSI devices require that thewafers be polished to near perfection The fabrication process consists ofseveral steps involving deposition, and diffusion of various materials onthe wafer During each step one mask is used Several dozen masks may

iden-be used to complete the fabrication process A large wafer is 20 cm (8inch) in diameter and can be used to produce hundreds of chips, depend-ing of the size of the chip Before the chip is mass produced, a prototype

is made and tested Industry is rapidly moving towards a 30 cm (12 inch)wafer allowing even more chips per wafer leading to lower cost per chip

human power management project as well Several hundred engineers maywork on a large design project for two to three years This includes architecturedesigners, circuit designers, physical design specialists, and design automationengineers As a result, design is usually partitioned along functionality, anddifferent units are designed by different teams At any given time, each unitmay not be at the same level of design While one unit may be in logic designphase, another unit may be completing its physical design phase This imposes

a serious problem for chip level design tools, since these tools must work withpartial data at the chip level

The VLSI design cycle involves iterations, both within a step and betweendifferent steps The entire design cycle may be viewed as transformations ofrepresentations in various steps In each step, a new representation of thesystem is created and analyzed The representation is iteratively improved tomeet system specifications For example, a layout is iteratively improved sothat it meets the timing specifications of the system Another example may bedetection of design rule violations during design verification If such violationsare detected, the physical design step needs to be repeated to correct the error.The objectives of VLSI CAD tools are to minimize the time for each iterationand the total number of iterations, thus reducing time-to-market

1.2 New Trends in VLSI Design Cycle

The design flow described in the previous section is conceptually simple andillustrates the basic ideas of the VLSI design cycle However, there are manynew trends in the industry, which seek to significantly alter this flow Themajor contributing factors are:

1 Increasing interconnect delay: As the fabrication process improves,

the interconnect is not scaling at the same rate as the devices Devices arebecoming smaller and faster, and interconnect has not kept up with thatpace As a result, almost 60% of a path delay may be due to interconnect.One solution to interconnect delay and signal integrity issue is insertion

of repeaters in long wires In fact, repeaters are now necessary for mostchip level nets This techniques requires advanced planning since area forrepeaters must be allocated upfront

8 Chapter 1 VLSI Physical Design Automation

2

3

4

5

Increasing interconnect area: It has been estimated that a

micropro-cessor die has only 60%-70% of its area covered with active devices Therest of the area is needed to accommodate the interconnect This areaalso leads to performance degradation In early ICs, a few hundred tran-sistors were interconnected using one layer of metal As the number oftransistors grew, the interconnect area increased However, with the in-troduction of a second metal layer, the interconnect area decreased Thishas been the trend between design complexity and the number of metallayers In current designs, with approximately ten million transistors andfour to six layers of metal, one finds about 40% of the chips real estatededicated to its interconnect While more metal layers help in reducingthe die size, it should be noted that more metal layers (after a certainnumber of layers) do not necessarily mean less interconnect area This isdue to the space taken up by the vias on the lower layers

Increasing number of metal layers: To meet the increasing needs

of interconnect, the number of metal layers available for interconnect isincreasing Currently, a three layer process is commonly used for mostdesigns, while four layer and five layer processes are used mainly formicroprocessors As a result, a three dimensional view of the interconnect

is necessary

Increasing planning requirements: The most important implication

of increasing interconnect delay, area of the die dedicated to interconnect,and a large number of metal layers is that the relative location of devices isvery important Physical design considerations have to enter into design

at a much earlier phase In fact, functional design should include chip

planning This includes two new key steps; block planning and signal

planning Block planning assigns shapes and locations to main functionalblocks Signal planning refers to assignment of the three dimensionalregions through which major busses and signals will be routed Timingshould be estimated to verify the validity of the chip plan This planshould be used to create timing constraints for later stages of design

Synthesis: The time required to design any block can be reduced if

layout can be directly generated or synthesized from a higher level

de-scription This not only reduces design time, it also eliminates humanerrors The biggest disadvantage is the area used by synthesized blocks.Such blocks take larger areas than hand crafted blocks Depending uponthe level of design on which synthesis is introduced, we have two types ofsynthesis

Logic Synthesis: This process converts an HDL description of a

block into schematics (circuit description) and then produces its layout.Logic synthesis is an established technology for blocks in a chip design,and for complete Application Specific Integrated Circuits (ASICs) Logicsynthesis is not applicable for large regular blocks, such as RAMs, ROMs,PLAs and Datapaths, and complete microprocessor chips for two reasons;

pilers An even more restricted type of synthesis tools are called Module Generators, which work on smaller size problems The basic idea is to

simplify the synthesis task, either by restricting the architecture or stricting the size of the problem Silicon compilers sometimes use theoutput of module generators High level synthesis is an area of currentresearch and is not used in actual chip development [GDWL92] In sum-mary, high level synthesis systems provide very good implementations forspecialized classes of systems, and they will continue to gain acceptance

re-as they become more generalized

In order to accommodate the factors discussed above, the VLSI design cycle

is changing In Figure 1.2, we show a VLSI design flow which is closer to reality.

Due to increasing interconnect delay, the physical design starts very early inthe design cycle to get improved estimates of the performance of the chip, Theearly floor physical design activities lead to increasingly improved chip layout

as each block is refined This also allows better utilization of the chip area

to distribute the interconnect in three dimensions This distribution helps inreducing the die size, improving yield and reducing cost Essentially, the VLSIdesign cycle produces increasingly better defined descriptions of the given chip.Each description is verified and, if it fails to meet the specification, the step isrepeated

The input to the physical design cycle is a circuit diagram and the output

is the layout of the circuit This is accomplished in several stages such aspartitioning, floorplanning, placement, routing, and compaction The differentstages of physical design cycle are shown in Figure 1.3 Each of these stages will

be discussed in detail in various chapters; however, to give a global perspective,

we present a brief description of all the stages here

1 Partitioning: A chip may contain several million transistors Due to the

limitations of memory space and computation power available it maynot be possible to layout the entire chip (or generically speaking anylarge circuit) in the same step Therefore, the chip (circuit) is normallypartitioned into sub-chips (sub-circuits) These sub-partitions are called