Solution manual for fundamentals of digital and computer design with VHDL by sandige

1.16 See Figure P1.16.Logic Symbols OR operation AND operation NOT or Complement operation Distinctive Shape Figure P1.16 1.17 See Figure P1.17... 1.22 See Figure P1.22.Figure P1.22 1.23

1.16 See Figure P1.16.

Logic Symbols

OR operation AND operation

NOT or Complement

operation

Distinctive Shape

Figure P1.16

1.17 See Figure P1.17.

Figure P1.17

1.18 (a) 1F    , (b) 2A B C F  , (c) 3B F     , (d) 4A B C D F C

(e) F5   , (f) 6S W Y F  P T

1.19 binary digits or bits 1.20 See Figure P1.20.

Figure P1.20

1.21 bits or identity elements

1.22 See Figure P1.22.

Figure P1.22

1.23 Variable Dominant Rule, Commutative Rule, Distributive Rule, and Complement Rule.

1.24 When writing Boolean algebra expressions, the NOT operator has the highest precedence

followed by the AND operator followed by the OR operator.

1.25 A 1 A (variable dominant rule), A B B A   (commutative rule),

A B C(  )   A B A C(distributive rule), and A A  (complement rule).0

1.26 The dual of a Boolean relationship or a Boolean expression is obtained by interchanging the

identity elements (1 and 0) and the binary operators (• and +) while maintaining the order of precedence of the operators using parentheses if required

(X Y Z W   A) (X(Y Z W  )A) (X Y Z W A(   ) )

1.27 (A B C  )D   A B C

(X Y  Z) ((X Y ) Z) (X Y Z )

1.28 Theorems are useful equalities that are helpful in designing logic circuits.

1.29 See Figure P1.29 The theorem is the Absorption Theorem T1a: X X Y(  )X

Figure P1.29

1.30 See Figure P1.30 The theorem is the Simplification Theorem T10b: X  X Y X Y

Figure P1.30

1.31 See Figure P1.31 The theorem is the Consensus Theorem T4a:

A B  A C  B C  A B  A C

Figure P1.31

1.32 See Table P1.32.

Figure P1.32

1.33 See Table P1.33.

Figure P1.33

1.34 See Table P1.34.

X•(X + Y) X•X + X•Y

X + X•Y X•1 + X•Y X•(1 + Y) X•1 X Note that EOL = EOR

Absorption Theorem T1a: X•(X + Y) = X

Proof by Perfect Induction Method Proof by Mathematical Manipulation Method

(proving that EOL = EOR)

X Y X+Y X•(X+Y)

0 0

0 1

1 0

1 1

Figure P1.34

Section 1.3 Deriving Boolean Functions from Truth Tables

1.35 (a) F X Y1( , ) m(3)m3   (b)X Y F Y2( ) m(0)=m0Y

(c) F A B3( , ) m(1, 2,3)m1m2m3  A B  A B  A B

1.36 For minterms place an overbar just over the 0s.

1.37 See Figure P1.37.

Figure P1.37

1.38 (a) F X Y1( , ) m(2)m2   (b)X Y F Y2( ) m(1)=m1Y

(c) F A B3( , ) m(0,1, 2)m0m1m2  A B  A B  A B

1.39 See Figure P1.39.

Figure P1.39

1.40 For maxterms place an overbar just over the 1s

1.41 (a) F X Y1( , ) M(0,1, 2)M M M0 1 2 (X Y ) ( X Y ) ( X Y ) (b) F Y2( ) M(0)M0 Y (c) F A B3( , ) M(1, 2) ( A B ) ( A B )

1.42 See Figure P1.42.

Figure P1.42

1.43 (a) F X Y1( , ) M(0,1,3)M M M0 1 3(X Y ) ( X Y ) ( X Y ) (b) F Y2( ) M(1)M1Y (c) F A B3( , ) M(1,3)M M1 3(A B ) ( A B )

1.44 See Figure P1.44.

Figure P1.44

Section 1.4 Writing VHDL Designs for Simple Gate functions

1.45 CPLD (Complex Programmable Logic Device) and FPGA (Field Programmable Gate

Array)

1.46 the entity and the architecture

1.47 The entity contains the description of the inputs and the outputs, and the architecture

contains the description of the actual circuit in terms of a Boolean function or functions

1.48 A VHDL design consists of 3 parts The names of the three parts are the Library Part, Entity

Declaration, and Architecture Declaration

1.49 Keywords are reserved words that cannot be used for signal names or labels in VHDL.

1.50 The keywords are library, use, all, entity, is, port, in, out, end, architecture, of, is begin, and, and end.

1.51 There are three inputs and their names are X, Y, and Z.

1.52 See Figure P1.52.

Figure P1.52

1.53 See Figure P1.53.

Figure P1.53

1.54 See Figure P1.54.

Figure P1.54

1.55 See Figure P1.55.

Figure P1.55

1.56 See Listing P1.56.

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity CSOP1 is port (

a, b, c : in std_logic;

f : out std_logic

);

end CSOP1;

architecture B_function of CSOP1 is begin

f <= (not a and b and not c) or (not a and b and c) or (a and b and not c) or (a and b and c);

end B_function;

Listing P56

1.57 See Waveform P1.57 Notice that F is 1 for minterms 2, 3, 6, and 7 and F is 0 for all other

minterms This shows that the design is correct

Waveform P1.57

1.58 See Listing P1.58.

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity CSOP2 is port (

a, b, c : in std_logic;

f : out std_logic

);

end CSOP2;

architecture B_function of CSOP2 is begin

f <= not ((not a and not b and c) or

(a and not b and c) or (a and b and c));

end B_function;

Listing P58

1.59 See Waveform P1.59 Notice that F is 0 for minterms 1, 5, and 7 and F is 0 for all other

minterms This shows that the design is correct

Waveform P1.59

m0 m1 m2 m3 m4 m5 m6 m7 m0

1.60 See Listing P1.60.

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity CPOS1 is port (

w, x, y, z : in std_logic;

f : out std_logic

);

end CPOS1;

architecture B_function of CPOS1 is begin

f <= (w or x or y or z) and (w or x or y or not z) and (w or x or not y or z) and (not w or not x or not y or z);

end B_function;

Listing P60

1.61 See Waveform P1.61 Notice that F is 0 for maxterms 0, 1, 2, and 14 and F is 1 for all other

maxterms This shows that the design is correct

Waveform P1.61

1.62 See Listing P1.62.

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity CPOS2 is port (

x, y, z : in std_logic;

f : out std_logic

);

end CPOS2;

architecture B_function of CPOS2 is begin

f <= not ((x or y or z) and

(x or not y or not z) and (not x or not y or z));

end B_function;

Listing P62

M0 M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 M11 M12 M13 M14 M15 M0 m0

1.63 See Waveform P1.63 Notice that F is 1 for maxterms 0, 3, and 6 and F is 0 for all other

maxterms This shows that the design is correct

Waveform P1.63

Section 1.5 More about Logic Gates

1.64 See Figure P1.64.

Figure P1.64

1.65 See Figure P1.65.

Figure P1.65

1.66 See Figure P1.66.

Figure P1.66

1.67 See Figure P1.67.

Figure P1.67

1.68 See Figure P1.68 The names of the functionally complete gates are the NAND gate and the

NOR gate

Figure P1.68

1.69 See Figure P1.69.

Figure P1.69

1.70 See Figure P1.70.

Figure P1.70

1.71 See Figure P1.71.

Figure P1.71

1.72 See Figure P1.72.

Figure P1.72

1.73 See Figure P1.73s.

Figure P1.73s

1.74 See Figure P1.74s.

Figure P1.74s

1.75 See Figure P1.75s.

Figure P1.75s

1.76 See Figure P1.76.

Figure P1.76

1.77 See Figure P1.77.

Figure P1.77

1.78 See Figure P1.78.

Figure P1.78

1.79 See Figure P1.79.

Figure P1.79

1.80 A gate with a bubble input is an active low input An active low input required a 0 or a low

voltage input for the input to be active or asserted

1.81 A gate with a bubble output is an active low output An active low output provided a 0 or

low voltage output for the output to be active or asserted

1.82 A gate that does not contain a bubble input is an active high input An active high input

required a 1 or a high voltage input for the input to be active or asserted

1.83 A gate that does not contain a bubble output is an active high output An active high output

provides a 1 or high voltage output for the output to be active or asserted

1.84 (a) 3-input NAND gate, (b) 2-input XOR gate, and (c) BUFFER 1.85 (a) 3-input NOR gate, (b) NOT gate, and (c) 2-input XNOR gate

1.86 (a) A B C   , (b) A B C   , and (c) A B

1.87 (a) A B  , (b) A , and (c) A B C 