Điện tử công suât mạch MMC Control and experiment of pulse width modulated modular multilevel converters

Luận văn, Điện tử công suất, đề tài tốt nghiệp, đồ án, thực tập tốt nghiệp, đề tài

Control and Experiment of Pulse-Width-Modulated

Modular Multilevel Converters

Makoto Hagiwara, Member, IEEE, and Hirofumi Akagi, Fellow, IEEE

Department of Electrical and Electronic Engineering Tokyo Institute of Technology, Tokyo, Japan E-mail: mhagi@akg.ee.titech.ac.jp, and akagi@ee.titech.ac.jp

Abstract— A modular multilevel converter (MMC) is one of

the next-generation multilevel converters intended for high- or

medium-voltage power conversion without transformers The

MMC is based on cascade connection of multiple bidirectional

chopper-cells per leg, thus requiring voltage-balancing control

of the multiple floating dc capacitors However, no paper has

made an explicit discussion on voltage-balancing control with

theoretical and experimental verifications This paper deals with

two types of pulse-width-modulated modular multilevel

convert-ers (PWM-MMCs) with focus on their circuit configurations

and voltage-balancing control Combination of averaging and

balancing controls enables the PWM-MMCs to achieve voltage

balancing without any external circuit The viability of the

PWM-MMCs, as well as the effectiveness of the voltage-balancing

control, is confirmed by simulation and experiment.

Keywords— Medium-voltage power conversion, multilevel

con-verters, voltage-balancing control.

I I

High-power converters for utility applications require

line-frequency transformers for the purpose of enhancing their

volt-age or current rating [1]-[4] The 80-MVA STATCOM (STATic

synchronous COMpensator) commissioned in 2004 consists

of 18 NPC (Neutral-Point-Clamped) converter-legs [4], where

each of the ac sides is connected in series by the corresponding

transformer The use of line-frequency transformers, however,

not only makes the converter heavy and bulky, but also induces

the so-called dc magnetic-flux deviation when a

single-line-to-ground fault occurs [5]

Recently, many scientists and engineers of power systems

and power electronics have been involved in multilevel

con-verters intended for achieving medium-voltage power

conver-sion without transformers [6]-[8] Two of the representatives

are:

1) the diode-clamped multilevel converter (DCMC) [6][7],

2) the flying-capacitor multilevel converter (FCMC) [8]

The three-level DCMC, or a neutral-point-clamped (NPC)

converter [9] has been put into practical use [10] If a

voltage-level number is more than three in the DCMC, inherent

voltage imbalance occurs in the series-connected dc capacitors,

thus resulting in requiring an external balancing circuit (such

as a buck-boost chopper) for a pair of dc capacitors [11]

Furthermore, a significant increase in the clamping diodes

required renders assembling and building of each leg more

complex and difficult Thus, a reasonable voltage-level number

would be up to five from a practical point of view As for

the FCMC, the four-level PWM inverter is currently produced

by one manufacture of industrial medium-voltage drives [12] However, the high expense of flying capacitors at low carrier frequencies (say, lower than 1 kHz) is the major disadvantage

of the FCMC [13]

A modular multilevel converter (MMC) has been proposed

in [14]-[20], intended for high-power applications Fig 1 shows a basic circuit configuration of a three-phase modular multilevel inverter Each leg consists of two stacks of multi-ple bidirectional cascaded chopper-cells and two non-coumulti-pled buffer inductors The MMC is suitable for high- or medium-voltage power conversion due to easy construction/assembling and flexibility in converter design Siemens has a plan of putting it into practical use with the trade name of “HVDC-plus.” It is reported in [19] that a system configuration of the HVDC-plus has a power rating of 400 MVA, a dc-link voltage of ±200 kV, and 200 cascaded chopper-cells per leg The authors of [14]-[20], however, have made no detailed description of staircase modulation, especially about a crucial issue of how to achieve voltage balancing of 200 floating dc capacitors per leg Moreover, no experimental result has been reported yet

This paper focuses on voltage-balancing control and oper-ating performance of a pulse-width-modulated modular multi-level converter (PWM-MMC) equipped with either two non-coupled buffer inductors or a single non-coupled buffer inductor per leg The final aim of this paper is to apply the PWM-MMC

to medium-voltage power converters in a power rating of 1 to

10 MVA, a dc-link voltage of 10 to 30 kV, and a switching frequency of 200 to 2000 Hz Combining averaging control with balancing control enables to achieve voltage balancing

of multiple floating dc capacitors without any external circuit

In addition, this paper proposes the dual MMC for low-voltage large-current power conversion Each dc side of positive and negative chopper-cells possesses a common dc capacitor, whereas its ac side is connected in parallel via multiple buffer inductors The similarity between the two MMCs exists in terms of circuit configuration and control method The validity

of the two MMCs is confirmed not only by simulated results, but also by experimental results

II T  M M C

A Classification from the Topologies

Fig 2 shows a classification of modular multilevel convert-ers based on single-phase half-bridge or full-bridge

converter-i d

i Pu

i Nu

i Zu

i u

i v

i w

v1u

v8u

v C1u

v C4u

v C5u

v C8u

v ju

l

l

E

v C ju

C ( j : 1 ∼ 8)

u-phase v-phase w-phase

cell 1

cell 4

cell 5

cell 8

w

(a)

(b)

Fig 1 Circuit configuration of a chopper-cell-type modular multilevel

inverter: (a) The power circuit, and (b) The bidirectional PWM chopper-cell

with a floating dc capacitor.

cells From their topologies, modular multilevel converters can

be classified into

1) double-star-configured MMCs,

2) a star-configured MMC (Fig 3(a)),

3) a delta-configured MMC (Fig 3(b)), and

4) the dual MMC (Fig 14)

Moreover, the double-star-configured MMCs can be classified

into

1) a chopper-cell-type MMC (Fig 1), and

2) a bridge-cell-type MMC

B Comparisons in Function and Application

The double-star-configured MMC topology possesses the

common dc-link terminals as shown in Fig 1(a), which

enable dc-to-ac and ac-to-dc power conversion However, the

star/delta-configured MMC topology has no common dc-link

terminals as shown in Fig 3 As a result, it has no capability

of achieving dc-to-ac and ac-to-dc power conversion although

it can control active power back and force between the

three-phase ac terminals and the floating dc capacitors This means

that the star/delta-configured MMC topology is not applicable

to industrial motor drives, but it is suitable for STATCOMs and

energy storage systems [21]-[23] This consideration is one of

the most significant differences in function and application

between the double-star-configured MMC topology in Fig 1

and the star/delta-configured MMC topology in Fig 3

The bridge-cell-type MMC replaces the chopper-cell in

Fig 1(b) with single-phase full-bridge converter-cells Hence,

Modular Multilevel Converters (MMCs) Double-star-configured MMCs

Star-configured MMC (Fig 3(a)) Delta-configured MMC (Fig 3(b)) The dual MMC (Fig 14)

using half-bridge converter-cells (chopper-cell-type MMC (Fig 1)) using single-phase full-bridge converter-cells (bridge-cell-type MMC)

Fig 2 A classification of modular multilevel converters.

cell 2

cell n

cell 2

cell n

Fig 3 Circuit configuration of MMCs: (a) Star-configured MMC, and (b) Delta-configured MMC.

the dc-voltage source E can be replaced with a single-phase

ac-voltage source [16] The detail of the dual MMC is discussed

in section V In this paper, the chopper-cell-type MMC is referred to simply as “the MMC” because attention is paid

to it exclusively

C Definition of DC Loop Currents

Fig 1 shows a three-phase inverter based on the MMC Each leg of the circuit consists of two stacks of four bidirectional chopper-cells and two non-coupled buffer inductors Each chopper-cell consists of a floating dc capacitor and two IGBTs

that form a bidirectional chopper Attention is paid to the

u-phase chopper-cells because the operating principle is identical among the three legs

The following circuit equation exists in Fig 1(a)1:

E =

8 X

j=1

v ju + l d

Here, E is a supply dc voltage, v ju is an output voltage of the u-phase chopper-cell numbered j, l is a buffer inductance, and i Pu and i Nu are positive- and negative-arm currents, respectively The KVL (Kirchhoff’s voltage law) loop given by (1) is referred to as the “dc loop,” which is independent of the load

1The subscript symbol j means numbering of each chopper-cell.

— 2

v∗C

¯v Cu

i∗Zu

i Pu

i Nu

i Zu

v C ju

v∗Au

current minor loop

( j : 1 ∼ 8)

+1 : i Pu , i Nu> 0

−1 : i Pu , i Nu< 0

K1+ —

s

K2

K3+ —

s K4

(a)

(b)

Fig 4 Block diagram of dc-capacitor voltage control: (a) Averaging control,

and (b) Balancing control.

The circulating current along the u-phase dc loop, i Zucan be

defined as

i Zu = i Pu−i u

2 = i Nu+i u

2

2(i Pu + i Nu) (2)

Note that i Pu , i Nu , i u and i d are branch currents whereas i Zu is

a loop current that is impossible to measure directly

III C M   MMC

The voltage-balancing control of eight floating dc capacitors

per leg in Fig 1 can be divided into

1) averaging control, and

2) balancing control

A Averaging Control

Fig 4(a) shows a block diagram of the averaging control It

forces the u-phase average voltage ¯v Cuto follow its command

v C∗, where ¯v Cuis given by

¯v Cu= 1 8

8 X

j=1

Let a dc-loop current command of i Zu be i∗Zu, as shown in

Fig 4(a) It is given by

i∗Zu = K1(v∗C − ¯v Cu ) + K2

Z

(v C∗ − ¯v Cu )dt. (4) The voltage command obtained from the averaging control,

v∗Auis given by

v∗Au = K3(i Zu − i∗Zu ) + K4

Z

(i Zu − i∗Zu )dt. (5)

When v∗C ≥ ¯v Cu , i∗Zu increases The function of the current

minor loop in Fig 4(a) forces the actual dc-loop current i Zu

to follow its command i∗Zu As a result, this feedback control

of i Zu enables ¯v Cu to follow its command v∗C without being

affected by the load current i

v∗Au

v∗Au

v∗B ju

v∗B ju

v∗u/4

v∗u/4

E/8

E/8

v∗ju

v∗ju ( j : 1 ∼ 4)

( j : 5 ∼ 8)

(a)

(b) Fig 5 Voltage command of each arm: (a) Positive arm, and (b) Negative arm.

B Balancing Control

The use of the balancing control described in [21] forces

the individual dc voltage to follow its command v C∗ Fig 4(b)

shows a block diagram of the u-phase balancing control, where

v∗B ju is the voltage command obtained from the balancing

control Since the balancing control is based on either i Pu or

i Nu , the polarity of v∗B ju should be changed according to that

of i Pu or i Nu When v C∗ ≥ v C ju ( j : 1 − 4) in the positive arm

of Fig 1(a), a positive active power should be taken from

the dc power supply into the four chopper-cells When i Pu is

positive, the product of v B ju (= v∗B ju ) and i Puforms the positive

active power When i Pu is negative, the polarity of v B jushould

get inverse to take the positive active power Finally, v∗B ju for

j = 1 − 4 is represented as:

v∗B ju=

(

K5(v C∗ − v C ju) (i Pu> 0)

−K5(v∗C − v C ju) (i Pu< 0), (6)

while v∗B ju for j = 5 − 8 is represented as:

v∗B ju=

(

K5(v∗C − v C ju) (i Nu> 0)

−K5(v∗C − v C ju) (i Nu< 0) (7)

Fig 5 shows a voltage command of each chopper-cell v∗ju The positive-arm and negative-arm commands are obtained as:

v∗ju = v∗

Au + v∗

B ju−v

∗

u

4 +E

8 ( j : 1 − 4) (8)

v∗ju = v∗Au + v∗B ju+v

∗

u

4 +E

8 ( j : 5 − 8), (9)

where v∗u is an ac-voltage command for the u-phase load.

Note that Fig 5 includes the feedforward control of the dc

supply voltage E The voltage command v∗ju is normalized

by each dc-capacitor voltage v C ju, followed by comparison with a triangular waveform having a maximal value of unity

and a minimal value of zero with a carrier frequency of f C

The actual switching frequency of each chopper-cell, f S is

equal to f C The eight chopper-cells have the eight triangular waveforms with the same frequency but a phase difference of

45◦(= 360◦/8) each other for achieving harmonic cancellation and enhancing current controllability As a result, the neutral voltage is a nine-level voltage waveform, and a line-to-line voltage is a 17-level voltage waveform with an equivalent

switching frequency of 8 f

0

-10

[kV]

200

0

-200

[A]

[A] 200

0

-200

[kV] 2.5

2.0

[MW]1.5

1.0

0.5

40

0

40

0

0

-40

0

-40

1

0

40 ms

v uv

v vw

v wu

v uv

i u

i v

i w

i u

i u

i Pu

i Nu

i u

v C1u

v C5u

v C1u

v C5u

p d

i∗Zu

i Zu

v∗B1u

v∗Au

v∗1u

v∗5u

v∗1u

v∗5u

Fig 6. Simulated waveforms obtained from Fig 1 where f = 50 Hz, v∗C=

2.25 kV, and E = 9 kV.

C Simulated Results

Fig 6 shows simulated waveforms from Fig 1 Tables I

and II summarize circuit parameters and control gains used for

simulation using a software package of the “PSCAD/EMTDC”

[24] The dc supply voltage E and the rated active power

P are set as E = 9 kV and P = 1 MW, and therefore the

nominal rated line-to-line rms voltage of the MMC is 5.5 kV

An intrinsic one-sampling delay occurs due to digital control

The dc-capacitor voltage command of each chopper-cell is

v∗ = 2.25 kV (= 9 kV/4), while three-phase load voltage

TABLE I C P U  S.

DC capacitor voltage V C 2.25 kV (= 9 kV/4)

Equivalent switching frequency 8 f C 16 kHz

Values in () are on a three-phase 5.5-kV, 1-MW, and 50-Hz base

TABLE II C G U  S.

Proportional gain of averaging control K1 0.5 A/V Integral gain of averaging control K2 150 A/(V·s) Proportional gain of current control K3 1.5 V/A Integral gain of current control K4 150 V/(A·s) Proportional gain of balancing control K5 0.35

commands of each phase are given as:

v∗u = 0.5E sin 2π f t

v∗v = 0.5E sin



2π f t −2

3π



v∗w = 0.5E sin



2π f t −4

3π



E = 9 kV

Note that v∗u , v∗v , and v∗w are the three-phase line-to-neutral voltages In Fig 6, each chopper-cell is operated at unity modulation index

In Table I, a unit capacitance constant H is defined as:

H = 3 × 8 ×

1

2CV2

C

P

= 12 × 1.9 × 10

−3× 2.252× 106

where V C is the rated dc voltage of each chopper-cell Note

that H is defined as a ratio of all electrostatic energy stored

in dc capacitors with respect to rated active power [25]

Therefore, H has a unit of second2

Fig 6 indicates that v uv is a 17-level line-to-line voltage, achieving voltage balancing of all the dc capacitors The dc

input power, p d is represented as:

where i d is a dc input current The waveform of p dincludes the following two frequency components: One is a 6th-frequency (300 Hz) component stemming from a three-phase full-bridge

2H can be defined in the traditional 2-level converters as well An optimization of H is left for the future work.

i P

i N

i0

v0

v1

v2

v3

v4

v C1

v C2

v C3

v C4

l l E/2

E/2

C d

C d

(70 V)

(70 V)

v S

C d = 20 mF

L ac= 1.1 mH

E = 140 V

L ac

E

C d

C d

250 VA MMC

cell 1

cell 2

cell 3

cell 4

(a)

(b)

Fig 7 Experimental circuit: (a) Half-bridge circuit, and (b) System

configuration.

v C1

v C4

clock(10 MHz)

sampling signal

8 bit gate Controller

AD

AD AD AD AD

i P

i N

E

cell 1

cell 4

v∗1

v∗4

Fig 8 Digital control system used for experiment.

converter, and the other is a fundamental-frequency (50 Hz)

component stemming from an output frequency of 50 Hz The

detailed analysis of each waveform will be carried out in the

next section

IV E R

A System Configuration Used for Experiment

Fig 7(a) shows a half-bridge circuit based on the MMC,

where the stack number of chopper-cells was selected as

four per leg to confirm the basic operating principle,

al-though the stack number of chopper-cells was eight in Fig 1

Fig 7(b) shows a system configuration used for experiment

The midpoint of the two dc input series-connected capacitors

is connected back to the neutral point of the star-winding of

the transformer, thus making the midpoint voltage stable The

dc supply voltage E is regulated at 140 V, and the capacitance

value of C is chosen as 20 mF

TABLE III C P U  E.

Equivalent switching frequency 4 f C 32 kHz

Values in () are on a single-phase 50-V, 5-A, and 50-Hz base

TABLE IV C G U  E.

Proportional gain of averaging control K1 0.5 A/V Integral gain of averaging control K2 80 A/(V·s) Proportional gain of current control K3 1 V/A Integral gain of current control K4 640 V/(A·s) Proportional gain of balancing control K5 0.5

Fig 8 shows the digital control system used for

experi-ment The system detects each dc-capacitor voltage v C j, both

positive- and negative-arm currents i P and i N, and a dc supply

voltage E as input signals to the A/D unit The A/D unit

consisting of seven A/D converters takes in the analogue signals, and then it converts them into seven 12-bits digital signals A DSP unit using a 16-bit DSP (ADSP-2105) takes

in the digital signals, and produces the voltage commands v∗j

after completing the digital processing shown in Figs 4 and

5 An FPGA unit has the following multi-functions:

1) generating carrier signals with appropriate phase differ-ences,

2) comparing v∗j with the corresponding triangular carrier signal, and

3) producing gate signals with a dead time of 2 µs The FPGA unit produces 8-bit (= 2 × 4) gate signals in total, because each chopper-cell possesses two semiconductor switches Furthermore, the FPGA unit sends back sampling signals to the DSP unit for realizing the so-called “syn-chronous sampling.”

Attention is paid to a one-sampling delay occurring in the DSP unit The experiment selected the carrier frequency

as f C = 8 kHz, while each triangular carrier had a phase difference of 90◦ (= 360◦/4) If a conventional synchronous sampling was adopted, the DSP unit would yield a time

delay of 63 µs (= 1/(2 f C)) because its sampling and com-mand renewal would be conducted at the peak value of each carrier waveform The sampling delay can be reduced with the following sampling method for improving controllability

of output voltages: As for chopper-cell 1, for instance, the sampling is conducted at the peak value of carrier signal 4,

and then v∗j is changed at the peak value of carrier signal 1

As a consequence, the time delay is minimized to be 31 µs

(= 1/(4 f C)) A three-phase MMC can reduce the time delay

further by phase-shifting of each leg by 120◦

B Operating Performance under a Steady-State Condition

Tables III and IV summarize the circuit parameters and

control gains used for experiment3 An R-L load with a power

factor of 0.9 at 50 Hz was utilized The experiment was carried

out under a condition of P = 250 W.

Fig 9 shows the experimental waveforms when the

dc-voltage command of each chopper-cell was set as v∗C = 70

V The ac voltage command for the load was given by:

v∗0 = √2V0sin 2π f t

V0= 50 V

Fig 7(a) yields the following equation:

v0 =1 2

X4

j=3

v j− 2 X

j=1

v j



− l 2

d

v0 =



R + L d dt



The waveform of v0is slightly different from that in a DCMC

and an FCMC, due to the existence of the second term of the

right hand in (14) Note that both DCMC and FCMC have

a complete staircase waveform with a constant (not curved)

voltage level Substituting (14) into (15) yields:

1

2

X4

j=3

v j−

2 X

j=1

v j



= Ri0+



L + l

2

d

Hence, harmonic voltages included in the left hand in (16)

appear across both L and l/2 If l/2 is dominant over L (L 

l/2), most of the harmonic voltages appear across l/2, bringing

less harmonic voltages to v0 If L is dominant over l/2 (L 

l/2), most of the harmonic voltages appear across L to the

contrary

Although the load current i0is sinusoidal with a

fundamen-tal component of 50 Hz, the arm currents i P and i N contain

non-negligible low-order harmonic currents This interesting

phenomenon occurs due to the effect of the balancing control

Fig 9 indicates that the voltage command from the balancing

control, v∗B1is a discontinuous sawtooth waveform as expected

from (6) and (7) As a result, v∗B1 brings a discontinuous

cir-culating current to the dc loop, producing low-order harmonic

currents in i P and i N It is obvious that the fluctuations in

i P and i N are accompanied by those in v∗B1 The switching

ripple currents contained in i P and i N are determined by the

inductance value of the buffer inductors and the harmonic

voltages resulting from the four chopper-cells Note that

switching-frequency components of 16 kHz are dominant in

i P and i N In other words, the ripple currents can be reduced

by increasing the carrier frequency and the buffer inductance

value Carefully looking into v∗B1 and i Pin Fig 9 reveals that a

subtle difference exists at the times of polarity change between

3The experimental conditions are the same in H and l(per unit) as those in

Fig 6.

80 0 -80 [V]

[A]10 0 -10 [V]100 70 40 [V]100 70 40 [A]

5 0 [V] 4 0 -4 [V] 4 0 -4 [V]70 35

v0

i0

i P

i N

i0

¯v C

v C1

v C3

v C1

v C3

i Z

i∗Z

i∗Z

i Z

v∗B1

v∗A

v∗1

Fig 9. Experimental waveforms obtained from Fig 7, where f = 50 Hz,

v C∗ = 70 V, and E = 140 V.

the waveforms of v∗B1 and i P The reason is that the 16-kHz

switching ripple component contained in i P is not taken into the control circuit precisely, because the sampling frequency

of DSP is set as 16 kHz This phenomenon produces no effect

on the balancing control because the harmonic current makes

no contribution to forming any active power

Applying the averaging control forces the average voltage

¯v C to follow its command v∗C (= 70 V) The calculation of

(3) has a function of reducing ac components in ¯v C From

Fig 9, v C1 and v C3 contain 50-Hz components caused by i0 This ac component is inverse proportional to the fundamental

frequency of i0 This is similar to flying capacitors in the FCMC

The dc voltage of each chopper-cell is kept balanced by the balancing control Making reference to (8) simplifies the

voltage commands of chopper-cells 1 and 2, v∗1 and v∗2 as follows:

v∗1= v∗

2' −v

∗

0

2 +E

where a reasonable approximation of v∗B1 = v∗

B2 = v∗

A' 0 was made Equation (17) implies that chopper-cells 1 and 2 were

0

-80

[V]

[A] 10

0

-10

[V] 100

70

40

Voltage command was changed

v0

i0

v C1

v C3

Fig 10 Experimental waveforms when the voltage command was changed

from 50 V to 25 V.

100

70

40

[V]

[V] 80

0

-80

[A] 10

0

-10

Only the balancing control was disabled

v0

i0

v C1

v C2

v C3

v C4

Fig 11 Experimental waveforms when only the balancing control was

disabled.

operated under the same modulation index As a result, v C1

was equal to v C2in Fig 9 because the chopper-cells 1 and 2

utilize a common arm current i P, and (17) leads to a relation

of v∗1 = v∗

2 In a similar way, v C3 was equal to v C4 in Fig 9

Experimental waveforms of i Z and i∗Zshow that no steady-state

error, even in a small control gain, existed between i Z and i∗Z

in terms of their dc components because of an extremely low

resistance along the dc loop

C Operating Performance under a Transient-State Condition

Fig 10 shows experimental waveforms of the MMC when

the voltage command was reduced to half, but the circuit

parameters and the control gains were not changed The

transient voltage fluctuations in v C1 and v C3 were suppressed

to less than 5% with respect to its rated voltage of 70 V

Fig 11 shows experimental waveforms before and after the

balancing control was disabled intentionally but the averaging

control was enabled The voltage imbalance was gradually

expanding with the passage of time Hence, the balancing

control is indispensable for stable operation

i P

i N

i0

a

b

c

l ac= 1.0 mH (3.2%)

l bc= 1.0 mH (3.2%)

l ab= 4.0 mH (12.8%)

Fig 12 Coupled inductor used for experiment.

80 0 -80 [V]

[A]10 0 -10 [V]100 70 40 [V]100 70 40 [A] 5 0

[V] 6 0 [V] 4 0 -4 [V]70 35

v0

i0

i P

i N

i0

¯v C

v C1

v C3

v C1

v C3

i Z

i∗Z

i∗Z

i Z

v∗B1

v∗A

v∗1

Fig 13 Experimental waveforms when a coupled buffer inductor was used.

D Operating Performance Using a Coupled Buffer Inductor

The two non-coupled buffer inductors in Fig 7 can be replaced with a single coupled buffer inductor intended for

a size reduction in the magnetic components Fig 12 shows specifications of the inductor used for experiment The

termi-nals “a” and “b” are connected to the positive- and negative-arms respectively, while the terminal “c,” or the midpoint is directly connected to the load The relation of l ab = 4l ac = 4l bc

exists in Fig 12 It should be noted that the inductor presents

no inductance to i0 because the magnetic fluxes produced by

the fundamental frequency components in i P and i N are can-celed out each other As a consequence, the inductor presents

the inductance of l ab only to the circulating current i Z The use of the coupled inductor results in bringing considerable

i P

i0

v0

i N

v1

v2

v3

v4

v C1

v C2

R L

i P1

i P2

i N1

i N2

l

l

l

l

E/2

E/2

C d

C d

(35 V)

(35 V)

cell 1

cell 2

cell 3

cell 4

Fig 14 Half-bridge circuit using the dual modular multilevel converter.

reductions in size, weight, and cost to the magnetic core4

Fig 13 shows experimental waveforms when the coupled

inductor was utilized In Fig 13, each chopper-cell was

oper-ated at a modulation index of 0.83, while the balancing control

using the load current was utilized (see the appendix.) Since

the inductor produces no effect on i0, (14) can be rewritten as

follows:

v0= 1 2

X4

j=3

v j− 2 X

j=1

v j



Hence, v0 is a staircase waveform with a constant voltage

level as shown in Fig 13 In other words, the MMC operates

as a multilevel voltage source that is independent of i0

Comparison between Figs 9 and 13 reveals that both have

similar waveforms except for v0

V T D MMC Fig 14 shows a half-bridge circuit of the other MMC with

a dual relation to Fig 7 Each dc side of positive and negative

chopper-cells possesses a common dc capacitor, whereas its

ac side is connected in parallel via two buffer inductors5

A Control Method

The control method of the dual MMC is basically the same

as that of Fig 1 except for the following: Although Fig 1 has

a common dc loop to cascaded chopper-cells per leg, the dual

MMC has multiple dc loops because the multiple

chopper-cells forming an arm are connected in parallel This means that

the multiple current minor loops should be provided for the

averaging control The chopper-cell 1 in Fig 14, for instance,

should control a circulating current i Z1 included in i P1 Here,

i Z1 is obtained as

i Z1 = i P1−i0

4 An optimization of the inductor is left for the future work.

5 The dc capacitor of each chopper-cell can be floated like Fig 7.

40 0 -40 [V]

[A]20 0 -20 [A] 10 0 -10 [V]100 70 40 [A]

5 0 [V] 4 0 -4 [V] 4 0 -4 [V]70 35

v0

i0

i P

i N

i0

i P1

i N1

i P1

i N1

v C2

v C1

v C1

v C2

i Z1

i∗Z

i∗Z

i Z1

v∗B1

v∗A1

v∗1

Fig 15. Experimental waveforms obtained from Fig 14, where f = 50 Hz,

v C∗ = 70 V, and E = 70 V.

B Operating Performance under a Steady-State Condition

Fig 15 shows experimental waveforms obtained from

Fig 14 Here, the dc supply voltage was E = 70 V, and the

dc voltage command of each chopper-cell was v C∗ = 70 V The

ac voltage command of the load was given by:

v∗0= √2V0sin 2π f t

V0 = 25 V

The circuit parameters and control gains were the same as those in Fig 9 It should be noted that the experiment was carried out using four non-coupled buffer inductors

Figs 9 and 15 show that both MMCs have similar wave-forms However, comparison reveals that the two waveforms

of v0 are different in harmonic voltage The reason is that the buffer inductance in the dual MMC is smaller than that in Fig 7 due to parallel connection of the two buffer inductors

Fig 15 shows that i P1 and i N1 are halves of i P and i N, respectively Therefore, the dual MMC is suitable for low-voltage large-current power conversion

VI C

This paper has dealt with two types of

pulse-width-modulated modular multilevel converters (PWM-MMCs),

proposing their control method and verifying their operating

principle Computer simulation using the “PSCAD/EMTDC”

software package has confirmed the proper operation of

the three-phase PWM-MMC Experiments using a laboratory

system has verified the viability and effectiveness of the

single-phase PWM-MMC The MMC is showing considerable

promise as a power converter for medium-voltage

motor-drives, high-voltage direct current (HVDC) systems,

STAT-COMs, and back-to-back (BTB) systems

R

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Sep./Oct 1981.

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2008.

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A

A Another Averaging Control Method

This subsection describes another averaging control method different from Fig 4(a), which is characterized by controlling independent average voltages of positive and negative

chopper-cells, ¯v Cup and ¯v Cun, which are given as follows:

¯v Cup=1 4

4 X

j=1

¯v Cun=1 4

8 X

j=5

The current command of the positive chopper-cells, i∗Zup is represented as:

i∗Zup = K1(v C∗ − ¯v Cup ) + K2

Z

(v∗C − ¯v Cup )dt, (23)

while that of the negative chopper-cells, i∗Zunis represented as:

i∗Zun = K1(v∗C − ¯v Cun ) + K2

Z

(v∗C − ¯v Cun )dt. (24)

Here, the voltage command of the positive chopper-cells, v∗Aup

is given by:

v∗Aup = K3(i Zu − i∗Zup ) + K4

Z

(i Zu − i∗Zup )dt, (25)

while that of the negative chopper-cells, v∗Aun is given by:

v∗Aun = K3(i Zu − i∗Zun ) + K4

Z

(i Zu − i∗Zun )dt. (26)

B Other Balancing Control Methods

The balancing control forms an active power between the

output voltage of each chopper-cell, v B juand the corresponding arm current The following describes two other balancing control methods different from Fig 4(b)

1) The method using the arm currents i Pu and i Nu :

For the positive chopper-cells numbered 1 to 4, v∗B ju is given

by:

v∗B ju = K5(v∗C − v C ju )i Pu (27)

For the negative chopper-cells numbered 5 to 8, v∗B ju is given

by:

v∗B ju = K5(v∗C − v C ju )i Nu (28)

Equations (27) and (28) indicate that v B ju (= v∗B ju) contains the

same frequency components as i Pu or i Nu, if the ac components

included in v C ju can be eliminated Hence, v B jucontains dc and

50-Hz components The dc component of v B juforms an active

power with that of i Pu or i Nu, and the 50-Hz component of

v B ju with that of i Pu or i Nu To avoid an undesirable effect on

the control system, ac components included in v C ju should be

eliminated fully by a low-pass filter

2) The method using the load current i u :

For the positive chopper-cells numbered 1 to 4, v∗B ju is given

by:

v∗B ju = K5(v∗C − v C ju )i u (29)

For the negative chopper-cells numbered 5 to 8, v∗B ju is given

by:

v∗B ju = −K5(v∗C − v C ju )i u (30)

Equations (29) and (30) indicate that v B ju (= v∗B ju) contains

the same frequency components as i u or −i u Note that i uis in

phase with i Pu , whereas −i u is in phase with i Nu The 50-Hz

component included in v B ju forms an active power with that

of i Pu or i Nu

Makoto Hagiwara (M’06) was born in Tokyo,

Japan, in 1979 He received his B.S and M.S.

and Ph.D degrees in electrical engineering from the Tokyo Institute of Technology in 2001, 2003, and 2006 respectively Since April 2006, he has been an Assistant Professor in the department of electrical and electronic engineering at the Tokyo Institute of Technology His research interests are self-commutated converters for utility applications.

Hirofumi Akagi (M’87-SM’94-F’96) was born in

Okayama, Japan, in 1951 He received the B.S degree from the Nagoya Institute of Technology, Nagoya, Japan, in 1974, and the M S and Ph D degrees from the Tokyo Institute of Technology, Tokyo, Japan, in 1976 and 1979, respectively, all

in electrical engineering.

In 1979, he was with the Nagaoka University

of Technology, Nagaoka, Japan, as an Assistant and then Associate Professor in the department of electrical engineering In 1987, he was a Visiting Scientist at the Massachusetts Institute of Technology for ten months From

1991 to 1999, he was a Professor in the department of electrical engineering

at Okayama University, Okayama, Japan From March to August of 1996, he was a Visiting Professor at the University of Wisconsin, Madison and then the Massachusetts Institute of Technology Since January 2000, he has been

a Professor in the department of electrical and electronic engineering at the Tokyo Institute of Technology, Tokyo, Japan.

His research interests include power conversion systems, ac motor drives, active and passive EMI filters, high-frequency resonant-inverters for induction heating and corona discharge treatment processes, and utility applications

of power electronics such as active filters for power conditioning, self-commutated BTB systems, and FACTS devices He has authored or coau-thored more than 80 IEEE Transactions papers, and two invited papers in

Proceedings of the IEEE According to Google Scholar, the total citation

index for all his papers is more than 7,000 He has made presentations many times as a keynote or invited speaker internationally.

He was elected as a Distinguished Lecturer of the IEEE Industry Ap-plications Society (IAS) and PELS for 1998-1999 He received two IEEE IAS Transactions Prize Paper Awards in 1991 and 2004, and two IEEE PELS Transactions Prize Paper Awards in 1999 and in 2003, nine IEEE IAS Committee Prize Paper Awards, the 2001 IEEE William E Newell Power Electronics Award, the 2004 IEEE IAS Outstanding Achievement Award, and the 2008 IEEE Richard H Kaufmann Technical Field Award He served as the President of the IEEE PELS for 2007-2008.