Tài liệu tiếng anh Điện tử công suất mạch MERS Series connected power flow control using magnetic energy recovery switch

Luận văn, Điện tử công suất, đề tài tốt nghiệp, đồ án, thực tập tốt nghiệp, đề tài

Series Connected Power Flow Control using Magnetic Energy Recovery Switch (MERS)

Jan A Wiik*, F Danang Widjaya*, Takanori Isobe*, Tadayuki Kitahara*, and Ryuichi Shimada*

*Solution Research Organization, Tokyo Institute of Technology 2-12-1 O-okayama, Meguro, Tokyo 152-8550, Japan

Abstract—A new series connected power flow controller,

called the Magnetic Energy Recovery Switch, has been inves-

tigated It is characterized by four active switches and a dc-

capacitor in each phase The device is capable of injecting up

to rated voltage within the current rating It behaves similar

to a controllable voltage source and a variable capacitor

connected in series A control algorithm has been developed

in order to facilitate power flow control with these combined

characteristics Experimental results suggest the MERS to be

a promising new power flow controller

Index Terms— Flexible ac transmission systems, power elec-

tronics, power flow control, series compensation

I INTRODUCTION Interconnections in power systems are getting more and

more common Large interconnected power systems have

the advantage of being able to reduce the total needed

generation capacity, while maintaining a secure operation

of the power system At the same time, interconnections

allow power flows over long distances such that natural

resources far away from load centers can be utilized With

the growing installation of renewable energy resources and

the de-regulation of energy markets, transmission flows are

more and more often being pushed towards the transmission

capacity limits

Another growing challenge in this scenario is loop flows

With parallel lines going from supply area to demand area,

the power flow will entirely be according to the impedances

in the grid A lower impedance line is in such a scenario

likely to become overloaded [1] Additionally, in grids with

multiple owners, owners that are not beneficiaries of the

transaction may be injured by loss of use of part or all of

their transmission capacity [2]

Series compensation has been used in transmission sys-

tems for many years, both for increasing transmission

capacity and for controlling power flows The initial uses

were with fixed passive capacitors giving a constant capac-

itive reactance However, fixed series compensation is well

known to potentially give problems with sub-synchronous

resonance (SSR) This was clearly demonstrated at the Mo-

have power station with two turbine-generator shaft failures

in 1970 and 1971 [3] Additionally, fixed passive capacitors

do not give the opportunity to actively improve damping

after transients in the power system or to actively control

the power flow However, they are the most cost effective solution for reducing the equivalent line impedance Research in the area of Flexible AC Transmission Sys- tems (FACTS) led to the development of the Thyristor Controlled Series Capacitor (TCSC) and the first large scale prototype installed in the beginning of the nineties [4] The TCSC consists of a series capacitor with a Thyristor Controlled Reactor (TCR) in parallel By controlling the switching instance of the thyristors, the apparent reactance

of the device can be controlled The TCSC has been shown to be SSR neutral when being controlled in vernier mode [4] The TCSC can control the equivalent reactance, however the operating range is limited

The GTO thyristor-controlled series capacitor or gate commutated series capacitor (GCSC) was introduced in

1992 [5] It consists of two anti-parallel GTOs in parallel with a series capacitor By controlling the timing of the switches, the equivalent reactance can be decreased con- tinuously to zero, Meaning an increase in operating range compared to the TCSC Compared to the TCSC, a smaller capacitor is needed [6]

The Static Synchronous Series Compensator (SSSC) was introduced in the late nineties [7] It consists of a voltage source inverter and a coupling transformer injecting the series voltage into the grid It can provide controllable com- pensating voltage over an identical capacitive and inductive range, independently of the magnitude of the line current Compared to the GCSC, the operating range is significant larger However, due to probable cost reasons, this com- ponent is not widely used today Also a transformerless variation of the SSSC has been suggested, eliminating the bulky transformer used in the SSSC application [8] This paper introduces a new series FACTS device First,

an overview of the device and its characteristics is given Secondly, experimental results are presented with a follow- ing conclusion

Il MAGNETIC ENERGY RECOVERY SWITCH

A Configuration The configuration investigated in this paper is called

use of this switch for power factor correction has been

Seeeescecedeoosesecas®

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Fig 1 Configuration of Magnetic Energy Recovery Switch

demonstrated for various loads [10], [11] In this paper

it is suggested to use the same configuration for series

compensation in power systems, however, with a different

control

The circuit configuration of the MERS is shown in Fig

1 It consists of 4 forced commutated switches (such as

GTOs), 4 diodes and a dc-capacitor For a three phase

circuit there will be one MERS per phase In principle,

the MERS configuration is the same as a single-phase full

bridge inverter, but the application and operation principle

differs Compared to a conventional single phase full bridge,

the capacitance of the dc-capacitor is several times smaller

and line frequency switching is used

B Operation Principle

The operation principle can be explained with illustra-

tions as shown in Fig 2 Fig 2(a) shows the case when

both switch S1 and S3 are on In this case the current will

flow as indicated by the main dotted line, as long as there is

a voltage across the capacitor The current will flow through

the diodes when the capacitor is charged and through the

active switches when being discharged For the case when

the dce-capacitor voltage becomes zero, the current will flow

in two parallel paths The same explanation applies for

Fig 2(b) Fig 2(c) shows the by-pass mode In this case

the injected series voltage can be zero even with voltage

remaining on the dc-capacitor

By using the described switching patterns, it is possible to

control the minimum dc-capacitor voltage and to control the

size of the zero voltage area The control is illustrated in Fig

3 The control of the minimum capacitor voltage, Vc min 18

achieved by entering the by-pass mode when the capacitor

voltage goes below Vo min In the by-pass mode, the series

injected voltage will be zero while the dc-capacitor voltage

will keep its value at Vomin The length of the by-pass

mode is adjusted with the phase lag control variable, +,

which has a zero reference when the current is 90 degrees

When the current phase passes the + set-point, a new pair

switching mode is entered (S1-S3 or S2-S4), and the dc-

capacitor voltage will again increase

Fig 2 Switching combination for the control of MERS

A special case can be achieved by controlling the Vo min

to zero For this case, the voltage across the capacitor will

be zero for parts of the period The control of the by-pass area will then directly result in the same operation as for the GCSC

C Series Voltage Characteristics and Harmonics The rms value of the injected series voltage, V, is given

by (1) All values are given in per unit and a sinusoidal current is assumed The voltage consists of a distortion component, Vpisr, and a first harmonic component, Vj

It can be found that the expressions have been divided by

the square of the current, /* By doing this, the expressions

on the right are simplified and only depends on two vari- ables, the minimum capacitor voltage related to the current, Vo.min/I, and the phase lag, y (Capacitor reactance, Xo,

is constant)

The equation of the MERS reactance, X,\erg, is given

12

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time (s) Fig 3 Ilustration of minimum de-capacitor voltage and phase lag control

by (2) Again, the expressions on the right depends on the

same two variables, Vo min/{ and +

V” Verse , Ve 1 f** 4

T2 = T2 T2 = mp Umers (z)dz

Da sin 2+ + 4X⁄2cos +XcB]

(2)

AVo min Cosy

X mers(Pu)

Fig 4 Optimal combination of minimum capacitor voltage reference and phase lag for relative voltage injection sizes

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oO NA

= 10F iat 7

BE 0 1

Current (pu) Fig 5 The harmonic distortion for various currents with rated series voltage applied

From (2) it can be found that + directly translates to an equivalent reactance, X.,, and that Vomin translates to a series voltage Vsprips(with a dependency also on y) Due

to this, the MERS can be said to have similar characteristics

to a voltage source and a capacitor connected in series For a given MERS reactance, Xyyers, various combina- tions of Vo min/J and y will be solutions to (2) The optimal combination, seen from a voltage distortion point of view, can be found by using both (1) and (2), and minimizing the Viftsr/12 Due to the relative complexity of the equations, a numerical approach was used to find the optimal parameter combinations The benefit of dividing the expression in (1) with the square of the current is now a more simple optimization with two variables instead of three The results, with Xc equal one, are shown in Fig 4

The harmonic distortion has been calculated for various currents with the series voltage, V1, set equal to one (Fig 5) One line shows the distortion with optimized Vo min/I and -y combinations, and the other shows the case with + equal zero The reduction in harmonic distortion by using optimized combinations is clear, especially for low currents The size of the distortion in the series voltage is shown with contour lines in Fig 6 for the whole operating range

Current (pu)

Fig 6 Harmonic distortion contour lines for the whole voltage-current

operating range

Primary control

|

|

| Ve min,ret RO

Fig 7 Illustration of the primary control system for the MERS in a

3-phase system

By limiting the maximum allowable series voltage for low

currents, the maximum distortion can be reduced With a

limit set to 15% distortion, the rating area is reduced with

approximately 15%

D Primary Control

The basic operation principle was described in section

II-B and consists of controlling the minimum capacitor

voltage and the phase lag The basic task of the primary

control system is to perform this control with given Vo min

and 7 set-points in a three phase system (Fig 7) The

gate logic block performs this action by using current

phase information, performing dc-capacitor voltage check

in defined phase periods, and change from by-pass to next

pair switching mode when current phase passes the + set-

point

Accurate current phase information is important for such

an application and is calculated with a phase locked loop

(PLL) The PLL implementation has been based on a dq-

transform type configuration [12], and was tuned such that

View With limited

4°

order

LP filter

Fig 8 Block diagram of phase lag limiter

phase lock could be achieved for a large range of current magnitudes The dq-transform PLL uses a feedback loop

to control the d-axis current to zero This means that when phase-lock is achieved the q-current will be a good estimation of the rms value of the current

Another important task for the primary control system is

to make sure that the voltage limits of the devices are not violated An example of a potential voltage limit violation is when rated voltage is injected at low current and the current suddenly increases If constant y and Vo min references are kept, the voltage might exceed the rating of the device In

order to avoid this, quick control action is performed in the

phase lag limiter block (Fig 8)

The phase lag limiter uses a feedback control structure, where the voltage peak across the capacitor is estimated and the deviation between the estimated and the limitation

voltage, Vuimit, is fed into a PI controller The resulting reactance set-point, X.,, is filtered and used in the voltage

peak estimation The limited reactance set-point always

chooses the minimum between the actual set-point, Xy rer,

and the limitation control set-point, X j;m Together with

logic for avoiding integral wind up, a smooth transition from normal mode to limitation mode and back can be achieved With the use of a look-up table, the resulting reactance set- point can be translated to a +y set-point

The first part of the primary control is the translation of

an input variable, Us, to X- and Vo min Set-points This is performed such that the reactance first is linearly increased, with the Vomin being zero, and after rated reactance has been reached, Vo min is linearly increased and 7 is adjusted

to reduce the harmonic content (Fig 9) The reason this translation is performed is to simplify the implementation

of the secondary control system Alternatively, the look-up

table can be skipped and y and Vo min set-points can be

generated directly from the secondary control system

Il] EXPERIMENTAL SETUP

In order to investigate the performance and stability of the proposed configuration, some experiments were conducted The configuration of the experimental setup is shown in

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a =<

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1 a =

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Control set-point, Uset (—)

Fig 9 Lookup table for converting Uset to y and Vo min

3*MERS

Inductor

MERS

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Fig 10 ¬ 8 Illustration of experimental setup

Fig 10 and with picture in Fig 11 It consists of a

controllable 3-phase ac power supply, which can control the

applied voltage with good response The MERS, a Y — A

transformer and inductors are connected in series to form

a loop The transformer connection shifts the voltage 30

degrees, meaning that power will automatically flow in the

circuit when voltage is applied In result, the equivalent of

the configuration is as shown in the lower part of Fig 10,

meaning a good representation of a transmission line

The specifications of the experimental circuit are given in

Table I The leakage inductance of the transformer and the

resistance of the transformer and inductor is negligible com-

— - BF

›@wxEX —

Fig 11 Picture of experimental setup

pared to the inductor reactance and has not been included in the specification Virtual rating means a MERS rating set in proportion to the other parts of the experimental setup The actual voltage rating of the MERS device is substantially higher

The control system was implemented using SH7045 microcontroller and was implemented as described in sec- tion II-D The control algorithm was performed 512 times every 50 Hz cycle Monitoring and giving set-points were performed from a desktop pc

IV EXPERIMENTAL RESULTS

A Response During Set-point Changes to Primary Control The set-point to the primary control, U , was varied in steps in order to investigate the response The power supply voltage was set constant to 60V during the test Fig 12 shows the case when a step was applied to U;.¢ from 0.6 to 0.75 The main observation is that the minimum capacitor

TABLE I SPECIFICATIONS OF EXPERIMENTAL CIRCUIT FOR POWER FLOW

CONTROL

Transformer power rating 3000 VA

Transformer rated excitation current 0.325 A

Virtual MERS voltage rating, ViwERS,N 40V

| ƠI oO

.04 S)

0 (

time Fig 12 Response during Use, set-point change from 0.6 to 0.75

voltage, Vomin, is controlled to a new value very rapidly

However, the by-pass period is longer immediately after the

VG min increase is performed, due to faster entry into the

by-pass mode while keeping constant + This means that

the series injected voltage will be smaller for the given half

cycle, initially reducing the current amplitude a few percent

A set-point point change from 0.3 to 0.45 is shown in

Fig 13 For Use, lower than 0.5, the Vomin reference is

zero The resulting step in phase lag reference can be seen

to quickly be adjusted There is no reduction in current after

the step change as could be seen when Vo min was larger

than zero The length of the bypass period uses two cycle to

stabilize When the current increases, the bypass period will

be longer than the set-point due to the decrease of capacitor

voltage being faster than the increase

B Phase Lag Limitation

A limitation control, as shown in Fig 8, was implemented

in the microcontroller The parameters used in the control

are given in Table II The gain is related to a per unit

peak voltage estimation The tuning of the parameters was

performed with the simulator called PSIM, and then applied

to the experiment

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10

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Fig 13 Response during Use, set-point change from 0.3 to 0.45

TABLE II PARAMETERS USED FOR PHASE LAG LIMITATION TEST

Limitation voltage, Vi imit V2VMERS,N

Integral time constant, 7} 0.01 Reactance feedback filter constant, Tp 0.005

A step in input voltage from 87 V to 156 V was applied while keeping a fixed U4 equal 0.71 The results are shown

in Fig 14 The R-phase input voltage is shown in top of the plot The response of the voltage increase is limited by the power supply, with a steady state reached after a bit more than 2 cycles The three MERS capacitor voltages are plotted for both the case with and without limitation control For the case without control, the voltage quickly passes the voltage limit By using the limitation control, the maximum voltage can be kept close to the limit The peaks of the capacitor voltages for the two cases are compared in the lower plot The test indicates that the limitation control is effective at avoiding over-voltages

C Steady State Current Flow Control

The relationship between the loop current flow and the primary control set-point, Use, was investigated for three different power supply voltages The test was performed by applying different U,., and recording the rms value of the series injected voltage and the current

The results are shown in Fig 15 The current is, as expected, increasing for increasing set-points The current increase characteristic is different in the reactance control area and the Vo min control area An irregular shape can

be seen when entering the Vo.min control area This is due

to rather quick reduction in reactance set-point when first

N ro) oO

Nh oO Oo

/) oO oO

S100

— V

0

time (S)

Fig 14 Phase lag limitation control

increasing the Vo.min set-point The irregular characteristic

is more significant for higher power supply voltages, which

is natural since reactance reduction is more visible when the

current is higher To improve the power flow characteristic,

it is possible to change the speed of the reactance decrease

when entering the Vo min area

For high U,.¢ set-points, the voltage is limited The

limitation control limits the peak voltage This means that

various rms voltages can be found for the same peak voltage

depending on the Vc min and reactance set-point This is the

reason the rms voltages in Fig 15 not has a fixed maximum

voltage

D Current Feedback Control

In order to test a simple secondary control system with

the given primary control, a current flow control loop was

implemented as illustrated in Fig 16 The q-axis current

calculated in primary control PLL algorithm was used as a

current measurement The control parameters were adjusted

T

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š oo ¢ ¢@ °

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cL at 0? 2° ^60V

= oe, & c7 e

O ee ® °° M

Uset (-)

Fig 15 Current flow and injected series voltage for various Uset set- points and three different power supply voltages

+

Iset

U PID -

Iq

Fig 16 Block diagram of curren flow feedback control

based on Ziegler-Nichols method The maximum gain was found to be more restricted for high Vo min than for low The slope of the U,.¢ - current curve in Fig 15 changes dependent on the voltage between the two line ends and the size of the U,.4 This also indicates dependency between maximum gain and operating point The parameters used are given in Table III, assuming per unit input and output values

A step was applied in current reference from 0.24 to 0.63pu The response in R-phase capacitor voltage and R- phase current are shown in Fig 17 The current reaches

a steady state value after approximately 0.3 seconds A smaller current step is shown in Fig 17 For this case, the response is slower and illustrates the difference in response when being in different operating area In order

to improve the response, gain scheduling could be used, with changing control parameters depending on operating point In summary, stable response of the current feedback control could be demonstrated

V CONCLUSION The characteristics of a new power flow controller, the Magnetic Energy Recovery Switch(MERS), have been in-

TABLE III PARAMETERS USED FOR CURRENT FLOW FEEDBACK CONTROL

Proportional gain, P 0.32

Integral time constant, ‘Tj 0.03

Derivative time constant, Tq 0.0074

= |

= -

= 20

= oll |

a 0 HN k | Ht TT rrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrr - —]

— 2b

-4 l 1 1 1 1 L 1 1 1 1 L 1

time (s) Fig 17 Current flow control when applying step in current reference

from 0.24 to 0.63pu

vestigated The device is capable of injecting up to rated

voltage within the current rating The device has found to be

similar to a voltage source and a capacitor in series, with the

possibility of both controlling the equivalent reactance and

the series voltage A control algorithm has been developed

in order to facilitate power flow control with these combined

characteristics The control has been optimized in order to

reduce injection of voltage harmonics

Experiments have been conducted in order to demonstrate

the characteristics of the MERS The challenge of injecting

rated voltage at lower currents has been addressed, and a

control method for avoiding overvoltage has been success-

fully demonstrated Also, steady state and step-response

current control experiments suggests that the MERS is a

promising new power flow controller

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E

£

‘Oo |

O 1 1 1 l L L

' ' ' Ỉ ' ' ' ' Ĩ ' ' ' ' Ĩ

2L

= 5 0 | | |

c3 -

time (S) Fig 18 Current flow control when applying step in current reference from 0.24 to 0.39pu

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