MIPS memory references an 8-bit quantity... Loading and storing words accessing memory.. the data memory to a register.. register into main memory... Loading and storing bytes data from
Trang 3We need more space!
each one is just 32-bits wide
whenever possible
Trang 4Harvard Architecture
stored in separate memories:
Trang 5MIPS memory
references an 8-bit quantity
Trang 6Data Memory
word_we byte_we Operation
0 1 Write byte in ADDR
1 0 Write word in ADDR
32
32
Trang 7Loading and storing words
accessing memory
the data memory to a register
register into main memory
sw $12, 4($3)
Trang 8Register File
0x10010000 0x10010001 0x10010002 0x10010003
Trang 10Loading and storing bytes
data from the data memory to a register
register into main memory
sb $12, 2($3)
Trang 11Register File
0x10010000 0x10010001 0x10010002 0x10010003 0x10010000
Trang 12Register File
0x10010000 0x10010001 0x10010002 0x10010003 0x10010000
Trang 14 Keep in mind that memory is byte-addressable, so a 32-bit word actually
occupies four contiguous locations (bytes) of main memory
must start at an address that is divisible by 4
unfortunately seen before
This restriction has relatively little effect on high-level languages and compilers,
0 1 2 3 4 5 6 7 8 9 10 11
Address
8-bit data
Trang 15Example Program that Uses Memory
Trang 16Example Program that Uses Memory
.data a: word 10 b: word 0
Trang 17Example Program that Uses Memory
.data a: word 10 b: word 0 text
Trang 18Example Program that Uses Memory
.data a: word 10 b: word 0 text
main:
la $4, a ….
lw $5, 0($4)
addi $5, $5, 7
sw $5, 0($4)
lw $5, 0($4) addi $5, $5, 7
sw $5, 4($4)
lw $5, 4($4) addi $5, $5, 7
sw $5, 4($4)
Trang 19Example Program that Uses Memory
.data a: word 10 b: word 0 text
main:
la $4, a
lw $5, 0($4) addi $5, $5, 7
sw $5, 4($4)
Trang 20Enconding of loads and stores
Loads and stores use the I-type format
The meaning of the register fields depends on the exact instruction
The address is a 16-bit signed two s-complement value
Trang 21Enconding of loads and stores
sw $5, 4($4)
lw $5, 4($4)
Trang 222 (Add) 32
reset
rdNum
rtData rtNum
rdWriteEnable rdData
zero negative overflow
0 1
4
inst[31:0]
PC[31:0]
ALU 1
nextPC[31:0]
0 1
16
32
32 32
branch offset
32
lw $5, 4($4)
Trang 232 (Add) 32
reset
rdNum
rtData rtNum
rdWriteEnable rdData
zero negative overflow
0 1
in[15:0]
data[31:0]
addr[29:0]
Instruction Memory
4
inst[31:0]
PC[31:0]
ALU 1
nextPC[31:0]
0 1
16
32 32
PC[31:28] (for MSBs)
branch offset
32
lbu $5, 4($4)
Trang 242 (Add) 32
alu_op[2:0]
write_enable itype except opcode[5:0]
B[31:0]
ALU
rsData rsNum
reset
rdNum
rtData rtNum
rdWriteEnable rdData
zero negative overflow
0 1
wr_enable itype
0 1
imm16
imm32
30
32 3
5 5 5
16
32
6 6
32 32
branch offset
branch offset
data_out[31:0]
addr[31:0]
Data Memory
zero
0 1
mem_read
data_out[31:24] data_out[23:16] data_out[15:8] data_out[7:0]
24'b0 0
word_we byte_we
data_in[31:0]
word_we byte_we
reset
32 32
Trang 252 (Add) 32
reset
rdNum
rtData rtNum
rdWriteEnable rdData
zero negative overflow
0 1
in[15:0]
data[31:0]
addr[29:0]
Instruction Memory
4
inst[31:0]
PC[31:0]
ALU 1
nextPC[31:0]
0 1
16
32 32
PC[31:28] (for MSBs)
branch offset
32
sw $5, 4($4)
Trang 262 (Add) 32
alu_op[2:0]
write_enable itype except opcode[5:0]
B[31:0]
ALU
rsData rsNum
reset
rdNum
rtData rtNum
rdWriteEnable rdData
zero negative overflow
0 1
wr_enable itype
0 1
imm16
imm32
30
32 3
5 5 5
16
32
6 6
32 32
branch offset
branch offset
data_out[31:0]
addr[31:0]
Data Memory
zero
0 1
mem_read
data_out[31:24] data_out[23:16] data_out[15:8] data_out[7:0]
24'b0 0
word_we byte_we
data_in[31:0]
word_we byte_we
reset
32 32