The discontinuous PWM DPWM methods of two-level inverters have been studied for many years, and they are introduced as an approach to reduce the switching loss [5]–[11].. A space vector
Trang 1by varying the offset depending on peak values of three-phase load
currents As results of avoiding commutations at high currents, the
switching loss can be reduced The proposed method is
theoreti-cally analyzed and verified by experimental results.
Index Terms—Discontinuous pulse width modulation (DPWM),
multilevel inverter, switching losses.
I INTRODUCTION
IN RECENT YEARS, multilevel inverters have been
in-tensively developed for the high-performance applications
[1]–[4] Their main topologies, such as diode-clamped type,
cascaded type, and capacitor-clamped type, are commonly
used, as shown in Fig 1 Three pulse width modulation (PWM)
techniques, such as selective harmonic elimination PWM (SHE
PWM), carrier-based PWM (CPWM), and space vector PWM
(SVPWM), have been favorably used in practice Because of
having a small number of switching, the SHE PWM method
shows advantage for high-power applications Two remaining
PWM techniques are commonly used in various fields because
of their excellent PWM qualities The discontinuous PWM
(DPWM) methods of two-level inverters have been studied
for many years, and they are introduced as an approach to
reduce the switching loss [5]–[11] DPWM methods can be
realized using the SVPWM approach by eliminating one from
the redundant zero vectors in the switching state sequence [6]
or CPWM ones by adding offset to make some leg-voltage
attain one of two dc-rail levels [7]–[10] Some studies were
concentrated on analyzing the impacts of DPWM waveforms on
the current ripple [5], [7] A space vector DPWM strategy for
two-level inverter was proposed for minimizing the switching
loss [6] The switching state sequence was selected in relation
to the current vector position to avoid commutations at the peak
current Its principle was further extended for the whole range
Manuscript received August 1, 2009; revised January 12, 2010 and March 29,
2010; accepted May 14, 2010 Date of publication January 17, 2011; date of
current version August 12, 2011.
N.-V Nguyen and B.-X Nguyen are with the Department of Electrical
Engineering, Ho Chi Minh City University of Technology, Ho Chi Minh City,
Vietnam (e-mail: nvnho@hcmut.edu.vn; nxbac@hcmut.edu.vn).
H.-H Lee is with the Department of Electrical Engineering, University of
Ulsan, Ulsan 680-749, South Korea (e-mail: hhlee@mail.ulsan.ac.kr).
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TIE.2010.2102312
Fig 1 Circuit diagram of five-level neutral point-clamped (NPC) inverter.
of the load power factor, but with the CPWM approach, the offset is modified to make commutation instants disappear at the highest current amplitudes [9] The description of current situations for the extended range was not clear The drawback was that it was a need of a detector of current vector position, angular conversion, and rotation operation Regarding the load power factor, other offset proposal of the optimal general DPWM was also found in [8] It was proven that the switching loss can be reduced to about 50–63% of the conventional continuous PWM method Studying of the minimized switching loss PWM technique for two-level inverter was then applied for the active power filter [12] There have been recently several studies about DPWM methods for multilevel inverter [13]–[16] The multicarrier-based DPWM methods for multilevel inverters are being deduced, in principle, similar to that of a two-level inverter For two-level inverters, two zero redundant vectors did not cause any complication with offset control The relationship between offset and switching states was simply clarified in [7], [10] However, the obtained results have not extended enough for multilevel inverters
It is due to the complication given by the existence of a larger number of redundant vectors, which offer a lot of possibilities for producing the DPWM offset function One of the typical DPWM methods was proposed for medium common mode [13], [14] Unfortunately, the described algorithm would be hardly applied to other DPWM cases The load current charac-ter and related DPWM algorithms for reducing switching loss have not been considered Obviously, to formulate a universal carrier-based DPWM technique like being attained in two-level inverters requires a comprehensive study
0278-0046/$26.00 © 2011 IEEE
Trang 2Fig 2 Explanation of voltage components in proposed model of multilevel
inverter.
Normally, a CPWM method can be developed in two stages
as follows: 1) producing fundamental reference and common
mode voltages [4] and 2) modifying the common mode voltage
to improve PWM performance
Besides modifying in DPWM, the previously mentioned
PWM method for attaining medium common mode voltage can
be also modified in SVPWM [17] Flexibility of carrier PWM
can be fully analyzed in a general carrier PWM approach with
any reference common mode [16] To have a deep
understand-ing of carrier PWM method in these stages, it should be brought
out the impacts of the common mode components on the control
characteristics of multilevel inverters
In this paper, a novel universal approach of CPWM methods
in multilevel inverters will be presented As an application, a
DPWM algorithm to minimize switching loss with
considera-tion on variable load currents will be proposed
II VOLTAGEMODEL FORMULTILEVELINVERTER
Define reference inverter voltages between the output and
dc-reference point “0,” consisting of active voltages V x12 , x =
a, b, c, and the reference common mode V 0ref, as shown in
Fig 2, as follows [16]:
V xref = V x12 + V 0ref (1)
Active voltages: V x12can be determined from the amplitude
V ref and phase angle θ of the voltage vector as follows:
V a12 = V ref cos θ
V b12 = V ref cos(θ − 2π/3)
V c12 = V ref cos(θ − 4π/3). (2)
Define M AX and M IN as, respectively, the maximum and
minimum values from three-phase active voltages as follows:
M AX = M ax(V a12 , V b12 , V c12) (3a)
M IN = M in(V a12 , V b12 , V c12 ). (3b)
Reference common mode voltage V 0ref is a zero-sequence
component defined within the limited boundaries of V and
Fig 3 Explanation of relationship between carrier PWM method and refer-ence voltages.
V 0M in, as follows:
V 0M in ≤ V 0ref ≤ V 0M ax (4a)
V 0M ax = (n − 1)V dc − MAX (4b)
Define V k , k = 0, 1, 2, , (n − 1) voltage levels on the dc
side as follows:
Among them, define V L(x) and V H(x) two active voltage
levels closest to the reference voltage V xref(Fig 2)
V L(x) ≤ V xref ≤ V H(x)
V H(x) = (V L(x) + V dc ). (6) The relationship between voltage model and modulating signals in a Carrier Phase Disposition PWM method can be
clarified in Fig 3 The voltage quantity V x , x = a, b, c, will be presented in relation to the control signal v x (V dcis the voltage
on one dc cell) as follows:
V x = v x V dc (7)
The following quantities: v xref , v x12 , v 0ref , and v 0add cor-respond to reference inverter voltage, active voltage, reference common mode, and additional common mode voltages, respec-tively For them, their relationship is expressed in vector form
as follows:
ref = v12+ v 0ref I, I = [1, 1, 1] T (8a)
ref = v ref + v 0add (8b) where
ref = [v aref , v bref , v cref]T
12= [v a12 , v b12 , v c12]T (9)
In (8a) and (8b), the reference v 0ref and additional common
mode v 0add are two components of a unified common mode voltage
Trang 3Fig 5 (a) Reference vector in vector triangle, (b) Switching time diagram in
active carrier waveforms in multicarrier PWM.
An inverter voltage is varied between the two active levels
of V H(x) and V L(x) , where indexes L (x) and H (x)are deduced
as two integer values closest to the reference signal v xref , x =
a, b, c, which satisfies the conditions (Figs 3–5) according to
L (x)=
n (x) if 0≤ v xref < (n − 1)
n (x) − 1 if v xref = (n − 1)
where
n (x) = Int(v xref ); x = a, b, c. (11)
Nominal carrier waveform: a carrier waveform varying in the
range of (0, 1)
Nominal modulating signals ξ x, 0≤ ξ x ≤ 1, are defined as
subtractions of the following:
ξ x = v xref − L (x) ; x = a, b, c. (12)
Define maximum, medium, and minimum values of the
three-phase nominal modulating signals as follows:
max = M ax(ξ a , ξ b , ξ c)
mid = M id(ξ a , ξ b , ξ c)
min = M in(ξ a , ξ b , ξ c ). (13)
Define s M ax and s M idvectors as
M ax = [s aM ax , s bM ax , s cM ax]T
M id = [s aM id , s bM id , s cM id]T (14)
where for x = a, b, c
s xM ax=
1 if max = ξ x
s xM id=
1 if mid = ξ
x
Fig 6 Switching diagram in normalized two-level inverter.
TABLE I
N OMINAL S WITCHING S TATES AND S WITCHING T IME D UTIES
The vectors s M ax and s M ididentify the relative position of nominal modulating signals in a nominal carrier waveform For
instance, two vectors s M ax = [1, 0, 0] T and s M id = [0, 0, 1] T
give ξ a > ξ c > ξ b The intersections between the nominal
car-rier waveform and three-phase nominal modulating signals ξ x will define switching state sequence s1, s2, s3, and s4, as shown
in Fig 6 Their corresponding switching time duties K1, K2,
K3, and K4can be deduced in Table I The nominal switching
states s1and s4are corresponding to two active zero redundant
states in a virtual two-level inverter These nominal vectors s1,
2, s3, and s4and switching state sequence S1, S2, S3, and S4
of multicarrier PWM method are closely related as follows:
S j = L + s j , j = 1, 2, 3, 4. (17)
The vectors L, ξ ref , s1, s2, s3, and s4 can be used to characterize switching behavior of multilevel inverters The switching process of multicarrier PWM method can be simply followed by a single-carrier PWM method of the virtual two-level inverter The transforming vector helps to define actual switching states
Similar equations for SVPWM, multicarrier, and single-carrier PWM can be deduced as follows:
V ref = K1V 1+ K2V 2+ K3V 3+ K4V 4 (18)
ref = K1S 1+ K2S 2+ K3S 3+ K4S 4 (19)
ref = K11+ K22+ K33+ K44 (20)
where
V j = V dc S j (21)
ref = v ref − L (22)
Trang 4erence inverter voltage V xref (Fig 4) In carrier PWM
im-plementation, the active components remain unchanged while
an additional offset v 0add can be set within defined limits
The additional offset in multilevel inverter should avoid extra
switching The modified voltages would attain one of some
closest dc-levels with possibly a minimum move of leg
volt-ages In the nominal switching diagram, this happens as adding
an offset ξ0 to the references ξ x The offset ξ0= v 0add is
defined as follows:
ξ 0M in ≤ ξ0≤ ξ 0M ax (24a)
ξ 0M ax= 1− max = K1 (24b)
ξ 0M in=− min = −K4. (24c)
Adding the offset ξ0redistributes time duties as follows:
K1 = K1− ξ0; K2 = K2; K3 = K3
The control characteristics of a CPWM method in multilevel
inverters can be described completely by (4), (24), and (25)
The offset function v 0ref makes carrier PWM in multilevel
inverters different from that in two-level inverters The selected
value of v 0ref determines the active low leg voltage levels (L),
which define the first one from the switching states involved
in the commutation sequence Therefore, the selection of v 0ref
is decisive to switching state sequence For conventional
two-level inverter, this step is not significant because both two two-levels
of the leg voltages and related switching state sequence in the
considered hexagon sector are totally known Adjusting the
second offset ξ0enables to attain the PWM behaviors of
mul-tilevel inverters It is realized in a similar way as in two-level
inverters [7], [10] Its value adjusts the time duty distribution
of the involved redundant vectors that influence PWM quality
Shortly, the first offset v 0ref presents a particular solution of
the carrier PWM control problem in multilevel inverters and
defines switching state sequence The second offset ξ0 (and
nominal signals) will give a common solution and define the
time—duties It becomes a control variable of the universal
CPWM method in multilevel inverters
For DPWM with minimized offset error, the additional offset
ξ0can be deduced as follows:
ξ0=
K1 for K1< K4
−K4 for K4< K1. (26)
The offset error is determined as follows:
Fig 7 Three-level NPC Inverter DPWM without optimized switching loss
for m = 0.9 in (a) minimum and (b) medium common modes Diagrams of modulating signal v aref —(8a) and modified modulating signal v
aref—(8b).
If K1= K4for reducing the common mode voltage against the dc midpoint, it is set as follows:
ξ0=
K1 for d1< d4
−K4 for d1> d4 (28)
where
d1=|v 0ref + K1− 0.5(n − 1)|
d4=||v 0ref − K4| − 0.5(n − 1)| (29) For DPWM method with minimized offset error, the di-agrams of reference modulating signal, the common mode,
and the modified modulating signal for m = 0.9, are shown
in Fig 7 The corresponding offsets are set for minimum and medium common modes, respectively Their related offset
components v 0ref are defined as follows [16]:
v 0ref =
⎧
⎨
⎩
v 0M in if 0.5(n − 1) < v 0M in ≤ v 0M ax
0.5(n − 1) if v 0M in ≤ 0.5(n − 1) ≤ v 0M ax
v 0M ax if v 0M in ≤ v 0M ax < 0.5(n − 1).
(30b)
Trang 5Fig 8 (a) Algorithm diagram for producing reference modulating signals in the optimized DPWM method.
B Optimized DPWM for Variable Load Power Factor
The principle is that an additional common mode will be
adjusted for producing a DPWM mode, which avoids
com-mutation for the phase of the absolute highest current If it
does not happen, the phase of the second highest current value
will be set for no commutation For variable load power factor,
the idea of optimized switching loss in two-level inverters [6],
[9] can be extended for multilevel inverters Some
modifica-tions are needed and with the help of the proposed carrier
PWM method
The proposed algorithm is shown in Fig 8 From the original
voltage reference v xref given by (8a) and (30), the three-phase
nominal modulating signals ξ a , ξ b , and ξ c can be deduced
using (10)–(12), whose maximum and minimum values are
determined as max and min (13) Additional common mode
is designed to limit resulting signals within the active carrier
range First, an additional offset is proposed to avoid
commu-tation at the phase of absolutely maximum current If not, an
extra offset to avoid commutation at medium current will be
selected As a result, commutations will be disappeared either
in a phase of maximum peak current or a medium one The
algorithm requires measuring load currents
In the diagram, parameters I max and I mid are, respectively,
the largest and medium absolute values from three-phase load
currents, i.e.,
Imax= M ax ( |i a |, |i b |, |i c |)
I = M id ( |i |, |i |, |i |) (31)
Parameters x IM ax and x IM id are two indexes from three abc
coordinates, corresponding to maximum and medium currents
in (31) Because there is no need of the detector of current vector position, the proposed implementation is more advan-tageous than the algorithm in [9] An investigation on the effect
of the proposed algorithm for various load power factors has been realized For demonstration, a simulation of the DPWM
algorithm with medium common mode for m = 0.5 was
imple-mented The simulation results are shown in Fig 9 Three-phase
load R − L was set as R = 3 Ω and L = 0.08 H(PF = 0.125).
Finding the exact DPWM offset functions v 0ref for dc voltage balancing while attaining optimized switching loss is beyond the scope of this paper The three nearest vectors—NTV with a minimized number of switching could almost achieve dc voltage balance, by selecting the starting state (corresponding
to the lowest levels of the leg voltages) of the sampling period
[18], [19] The selected vector could give an equivalent v 0ref,
then the introduced algorithm can be applied for deducing ξ0 However, the previous algorithm which was presented makes the dc balancing slow down [18] To get a better response for balancing dc voltages, multiple-switching algorithms can
be used, but they cause more switching loss [20] Generally, they have a different character from conventional CPWM techniques
C Comparison of Switching Loss
In conventional carrier PWM method, there is only one switch involved in sampling period during transient in each
Trang 6Fig 9 Three-level inverter: Optimized DPWM for modulation index of m =
0.5 Diagrams of optimized modulating signal A-phase, load currents, and
trigger pulses to switching pairs of A-phase Load R = 3 Ω and L = 0.08 H.
phase Let us suppose diodes to be ideal, the active switch
would have to maintain 100% voltage during the current
transi-tion For n-level NPC inverter, the voltage across the switch is
high as the current changes, equal to the off-state voltage V of f
as follows:
V of f = V dc (32)
A linear and rectangular commutation can be used to calculate
the average value of the local switching loss over the
fundamen-tal cycle T sof any phase as follows [8], [21]:
P swave= 1
2π
V of f (t on + t of f)
2T s
2π
0
f i (θ)dθ (33)
where
f i (θ) =
|i a |, ξ a = 1 ∧ ξ a = 0
The switching loss function (SLF) is found as follows:
SLF = P swave
P0=V of f (t on + t of f )I m
πT s
1
where I m is the amplitude of the load phase current; and P0is
the switching loss value under continuous PWM condition
In two-level inverter, the offset range is limited within the
defined two dc rails As a result, the optimized SLF is easily
deduced, dependent on only the load power factor Applying
the proposed optimized algorithm for the two-level inverter, the
diagram of the SLF function was drawn, as shown in Fig 10
The obtained SLF diagram is similar to that of the optimal
PWM method in [8], but in comparison with its diagram, the
Fig 10 Optimal DPWM SLF diagram deduced for two-level inverter.
Fig 11. Three-level NPC inverter Function SLF = f(m, ϕ) for medium
common mode optimized DPWM.
SLF function of the proposed DPWM attains smaller values close to±75 ◦.
In the multilevel inverter, the reference three-phase voltages can appear differently among carrier bands Any change in the fundamental voltage or the offset may change relative positions
of the three phases to the closest dc-levels The SLF function can be properly used to evaluate the effectiveness of the pro-posed DPWM method, which for given offset function, depends
on the load power factor and modulation index To demonstrate
it, the SLF of two popular cases as the minimum and medium common mode DPWM, has been calculated for three- and five-level inverters and shown in Figs 11–14, respectively
For the three-level inverter, because of the small difference
of the SLF function in two previously mentioned DPWM methods, only one of them is shown in Fig 11 Different behaviors from both DPWM methods appear obviously for the
five-level inverter for modulation index range of m > 0.25.
The influence of the load power factor on the SLF function of
DPWM methods can be investigated For example, if ϕ = 0 ◦,
two DPWM methods have similar behaviors for m < 0.5, as shown in Fig 12 For 0.63 < m < 0.73 and 0.825 < m < 1,
the SLF of the minimum common mode DPWM attains value less than 0.56 and 0.54, respectively, while the medium com-mon mode DPWM introduces SLF values less than 0.54 and
0.57 for 0.5 < m < 0.63 and 0.73 < m < 0.825, respectively.
Trang 7Fig 12 Five-level inverter Functions SLF for (curve 1) minimum and
(curve 2) medium common mode for (a) ϕ = 0 ◦ and (b) ϕ = 30 ◦.
Fig 13. Five-level NPC inverter Function SLF = f(m, ϕ) for medium
com-mon mode optimized DPWM.
As a result, if a combination of two DPWM methods is
applied, the SLF function will attain a value less than 0.57 for
the whole modulation index It is except the vicinity of m =
0.3, where SLF can reach a maximum value of 0.63 Similarly,
for ϕ = 30 ◦, the SLF can achieve values less than 0.57, as
shown in Fig 12(b) The complete space diagrams to describe
the SLF function of variables m and ϕ for the five-level inverter
are drawn for medium and minimum common mode optimized
DPWM methods, as shown in Figs 13 and 14, respectively
IV EXPERIMENTALRESULTS
The proposed algorithm was verified with the use of
three-phase three-level NPC inverter Experimental
hard-ware used power devices insulated-gate bipolar transistor
FG60N100BNTD and the control kit DSPACE DS1104 Two
dc voltages obtained from the output of a single-phase rectifier
were then filtered out by two capacitors of 4700 μF They were
measured utilizing the LEM LV25 NP; the load currents were
Fig 14. Five-level NPC inverter Function SLF = f(m, ϕ) for minimum
common mode optimized DPWM.
Fig 15. Experimental results: Modulation index of m = 0.5 Modulating
sig-nal corresponding to two switching pairs of A-phase and three-phase currents
on DSPACE Control Desk.
Fig 16. Experimental results: Modulation index of m = 0.5 Two-phase load
currents.
measured with the Hall sensors LEM LA 25NP via the low-pass filter, whose cutoff frequency was set at 500 Hz The resulting data were passed to the DS1104 processor Control parameters and diagrams, such as load currents and modulating signals, were also monitored and viewed on a DS1104 Control Desk Developer The frequency of the triangle carrier waveform was selected as 5 kHz Parameters were set as Vc1 = 75 V,
Vc2 = 75 V; fout= 50 Hz A 3-hp three-phase induction motor
at a balanced load was used For demonstration, the PWM
algo-rithm to optimize switching loss was implemented for m = 0.5
(Figs 15–18) For these experiments, the power factor of the
Trang 8Fig 17. FFT diagram of A phase load current for m = 0.5.
Fig 18. FFT of A-phase load voltage for m = 0.5.
Fig 19 Diagrams of three-phase load currents and A-phase modulating
signals when modulation index changed abruptly from m = 0.2 to m = 1
load was determined to be 0.125, the same as that in the
previous simulation In these figures, the corresponding
dia-grams of modified modulating signal of two switching pairs of
A-phase, two-phase load currents, and related fast Fourier
trans-form (FFT) analysis are drawn A discontinuous commutation
happened at the maximum current values, as shown in Fig 15
In other experiments with R − L load, R = 10 Ω and L =
0.18 H, the response of modulating signals in the proposed
DPWM algorithm after a step change of modulation index
from 0.2 to 1 was followed in Fig 19 Finally, the dc neutral
fluctuations for the continuous PWM and the proposed DPWM
were tested for m = 0.5 and m = 0.9 were shown in Figs 20
and 21, respectively Their response was shown the same For
limited pages, there were presented only the diagrams of the
proposed DPWM method For small modulation index, the
voltage fluctuation was negligible
Fig 20. DC voltages measured on two capacitors for m = 0.5.
Fig 21. DC voltages measured on two capacitors for m = 0.9.
V CONCLUSION
In this paper, a novel analysis of the multilevel inverter model has been proposed Two offset components have char-acterized entirely features of CPWM methods The proposed PWM method was then applied to optimize the switching loss
by avoiding commutations at the peak load currents Being different from the two-level inverter, the optimized DPWM SLF function is dependent on the modulation index The two popular
as the minimum and medium common mode-based optimized switching loss DPWM algorithms would properly give a ben-eficial reduction of switching loss Moreover, the method is advantageous for its simple algorithm The proposed method has been verified by the simulation and the experimental results
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Bac-Xuan Nguyen received the M.S degree in
automatic control engineering from the Ho Chi Minh City University of Technology, Ho Chi Minh City, Vietnam, in 2009.
He is a Lecturer in the Faculty of Electrical and Electronics Engineering, Ho Chi Minh City Uni-versity of Technology His research interests mainly include advanced control of electrical machines and power electronics.
Hong-Hee Lee (S’88–M’91) received the B.S.,
M.S., and Ph.D degrees in electrical engineering from Seoul National University, Seoul, South Korea,
in 1980, 1982, and 1990, respectively.
From 1994 to 1995, he was a Visiting Professor at Texas A&M University, College Station Since 1985,
he has been a Professor of electrical engineering at the University of Ulsan, Ulsan, South Korea He is also the Director of the Network-based Automation Research Center, which is sponsored by the Ministry
of Knowledge Economy His research interests are power electronics, network-based motor control, and control networks.
Dr Lee is a member of the Korean Institute of Power Electronics, the Korean Institute of Electrical Engineers, and the Institute of Control, Robotics, and Systems.